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<li id="toc-Lane" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Lane"> <div class="vector-toc-text"> 1.2 Lane </div> </a> <ul id="toc-Lane-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Serial_bus" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Serial_bus"> <div class="vector-toc-text"> 1.3 Serial bus </div> </a> <ul id="toc-Serial_bus-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Form_factors" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Form_factors"> <div class="vector-toc-text"> 2 Form factors </div> </a> <button aria-controls="toc-Form_factors-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Form factors subsection </button> <ul id="toc-Form_factors-sublist" class="vector-toc-list"> <li id="toc-PCI_Express_(standard)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_(standard)"> <div class="vector-toc-text"> 2.1 PCI Express (standard) </div> </a> <ul id="toc-PCI_Express_(standard)-sublist" class="vector-toc-list"> <li id="toc-Non-standard_video_card_form_factors" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Non-standard_video_card_form_factors"> <div class="vector-toc-text"> 2.1.1 Non-standard video card form factors </div> </a> <ul id="toc-Non-standard_video_card_form_factors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Pinout" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Pinout"> <div class="vector-toc-text"> 2.1.2 Pinout </div> </a> <ul id="toc-Pinout-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Power" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Power"> <div class="vector-toc-text"> 2.1.3 Power </div> </a> <ul id="toc-Power-sublist" class="vector-toc-list"> <li id="toc-Slot_power" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Slot_power"> <div class="vector-toc-text"> 2.1.3.1 Slot power </div> </a> <ul id="toc-Slot_power-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-6-_and_8-pin_power_connectors" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#6-_and_8-pin_power_connectors"> <div class="vector-toc-text"> 2.1.3.2 6- and 8-pin power connectors </div> </a> <ul id="toc-6-_and_8-pin_power_connectors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-12VHPWR_connector" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#12VHPWR_connector"> <div class="vector-toc-text"> 2.1.3.3 12VHPWR connector </div> </a> <ul id="toc-12VHPWR_connector-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-PCI_Express_Mini_Card" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_Mini_Card"> <div class="vector-toc-text"> 2.2 PCI Express Mini Card </div> </a> <ul id="toc-PCI_Express_Mini_Card-sublist" class="vector-toc-list"> <li id="toc-Physical_dimensions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Physical_dimensions"> <div class="vector-toc-text"> 2.2.1 Physical dimensions </div> </a> <ul id="toc-Physical_dimensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Electrical_interface" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Electrical_interface"> <div class="vector-toc-text"> 2.2.2 Electrical interface </div> </a> <ul id="toc-Electrical_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mini-SATA_(mSATA)_variant" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Mini-SATA_(mSATA)_variant"> <div class="vector-toc-text"> 2.2.3 Mini-SATA (mSATA) variant </div> </a> <ul id="toc-Mini-SATA_(mSATA)_variant-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-PCI_Express_M.2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_M.2"> <div class="vector-toc-text"> 2.3 PCI Express M.2 </div> </a> <ul id="toc-PCI_Express_M.2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI_Express_External_Cabling" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_External_Cabling"> <div class="vector-toc-text"> 2.4 PCI Express External Cabling </div> </a> <ul id="toc-PCI_Express_External_Cabling-sublist" class="vector-toc-list"> <li id="toc-PCI_Express_OCuLink" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PCI_Express_OCuLink"> <div class="vector-toc-text"> 2.4.1 PCI Express OCuLink </div> </a> <ul id="toc-PCI_Express_OCuLink-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Derivative_forms" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Derivative_forms"> <div class="vector-toc-text"> 2.5 Derivative forms </div> </a> <ul id="toc-Derivative_forms-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-History_and_revisions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#History_and_revisions"> <div class="vector-toc-text"> 3 History and revisions </div> </a> <button aria-controls="toc-History_and_revisions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle History and revisions subsection </button> <ul id="toc-History_and_revisions-sublist" class="vector-toc-list"> <li id="toc-Comparison_table" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Comparison_table"> <div class="vector-toc-text"> 3.1 Comparison table </div> </a> <ul id="toc-Comparison_table-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI_Express_1.0a" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_1.0a"> <div class="vector-toc-text"> 3.2 PCI Express 1.0a </div> </a> <ul id="toc-PCI_Express_1.0a-sublist" class="vector-toc-list"> <li id="toc-PCI_Express_1.1" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PCI_Express_1.1"> <div class="vector-toc-text"> 3.2.1 PCI Express 1.1 </div> </a> <ul id="toc-PCI_Express_1.1-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-PCI_Express_2.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_2.0"> <div class="vector-toc-text"> 3.3 PCI Express 2.0 </div> </a> <ul id="toc-PCI_Express_2.0-sublist" class="vector-toc-list"> <li id="toc-PCI_Express_2.1" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PCI_Express_2.1"> <div class="vector-toc-text"> 3.3.1 PCI Express 2.1 </div> </a> <ul id="toc-PCI_Express_2.1-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-PCI_Express_3.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_3.0"> <div class="vector-toc-text"> 3.4 PCI Express 3.0 </div> </a> <ul id="toc-PCI_Express_3.0-sublist" class="vector-toc-list"> <li id="toc-PCI_Express_3.1" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PCI_Express_3.1"> <div class="vector-toc-text"> 3.4.1 PCI Express 3.1 </div> </a> <ul id="toc-PCI_Express_3.1-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-PCI_Express_4.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_4.0"> <div class="vector-toc-text"> 3.5 PCI Express 4.0 </div> </a> <ul id="toc-PCI_Express_4.0-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI_Express_5.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_5.0"> <div class="vector-toc-text"> 3.6 PCI Express 5.0 </div> </a> <ul id="toc-PCI_Express_5.0-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI_Express_6.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_6.0"> <div class="vector-toc-text"> 3.7 PCI Express 6.0 </div> </a> <ul id="toc-PCI_Express_6.0-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI_Express_7.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI_Express_7.0"> <div class="vector-toc-text"> 3.8 PCI Express 7.0 </div> </a> <ul id="toc-PCI_Express_7.0-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Extensions_and_future_directions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Extensions_and_future_directions"> <div class="vector-toc-text"> 4 Extensions and future directions </div> </a> <button aria-controls="toc-Extensions_and_future_directions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Extensions and future directions subsection </button> <ul id="toc-Extensions_and_future_directions-sublist" class="vector-toc-list"> <li id="toc-Draft_process" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Draft_process"> <div class="vector-toc-text"> 4.1 Draft process </div> </a> <ul id="toc-Draft_process-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Hardware_protocol_summary" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Hardware_protocol_summary"> <div class="vector-toc-text"> 5 Hardware protocol summary </div> </a> <button aria-controls="toc-Hardware_protocol_summary-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Hardware protocol summary subsection </button> <ul id="toc-Hardware_protocol_summary-sublist" class="vector-toc-list"> <li id="toc-Physical_layer" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Physical_layer"> <div class="vector-toc-text"> 5.1 Physical layer </div> </a> <ul id="toc-Physical_layer-sublist" class="vector-toc-list"> <li id="toc-Data_transmission" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Data_transmission"> <div class="vector-toc-text"> 5.1.1 Data transmission </div> </a> <ul id="toc-Data_transmission-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Data_link_layer" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Data_link_layer"> <div class="vector-toc-text"> 5.2 Data link layer </div> </a> <ul id="toc-Data_link_layer-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Transaction_layer" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Transaction_layer"> <div class="vector-toc-text"> 5.3 Transaction layer </div> </a> <ul id="toc-Transaction_layer-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Efficiency_of_the_link" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Efficiency_of_the_link"> <div class="vector-toc-text"> 5.4 Efficiency of the link </div> </a> <ul id="toc-Efficiency_of_the_link-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Applications" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Applications"> <div class="vector-toc-text"> 6 Applications </div> </a> <button aria-controls="toc-Applications-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Applications subsection </button> <ul id="toc-Applications-sublist" class="vector-toc-list"> <li id="toc-External_GPUs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#External_GPUs"> <div class="vector-toc-text"> 6.1 External GPUs </div> </a> <ul id="toc-External_GPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Storage_devices" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Storage_devices"> <div class="vector-toc-text"> 6.2 Storage devices </div> </a> <ul id="toc-Storage_devices-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cluster_interconnect" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Cluster_interconnect"> <div class="vector-toc-text"> 6.3 Cluster interconnect </div> </a> <ul id="toc-Cluster_interconnect-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Competing_protocols" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Competing_protocols"> <div class="vector-toc-text"> 7 Competing protocols </div> </a> <ul id="toc-Competing_protocols-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Integrators_list" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Integrators_list"> <div class="vector-toc-text"> 8 Integrators list </div> </a> <ul id="toc-Integrators_list-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 9 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> 10 Notes </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 11 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> 12 Further reading </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 13 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" > Toggle the table of contents </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading">PCI Express</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 40 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-40" aria-hidden="true" > 40 languages </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B3%D8%B1%D9%89_%D8%A7%D9%84%D8%B1%D8%A8%D8%B7_%D8%A7%D9%84%D8%B3%D8%B1%D9%8A%D8%B9_%D8%A8%D9%8A%D9%86_%D8%A7%D9%84%D9%85%D9%83%D9%88%D9%86%D8%A7%D8%AA_%D8%A7%D9%84%D8%B7%D8%B1%D9%81%D9%8A%D8%A9" title="مسرى الربط السريع بين المكونات الطرفية – Arabic" lang="ar" hreflang="ar" data-title="مسرى الربط السريع بين المكونات الطرفية" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target">العربية</a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/PCI_Express" title="PCI Express – Bosnian" lang="bs" hreflang="bs" data-title="PCI Express" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target">Bosanski</a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/PCI_Express" title="PCI Express – Catalan" lang="ca" hreflang="ca" data-title="PCI Express" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target">Català</a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/PCI-Express" title="PCI-Express – Czech" lang="cs" hreflang="cs" data-title="PCI-Express" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target">Čeština</a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/PCI_Express" title="PCI Express – German" lang="de" hreflang="de" data-title="PCI Express" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target">Deutsch</a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/PCI_Express" title="PCI Express – Estonian" lang="et" hreflang="et" data-title="PCI Express" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target">Eesti</a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/PCI_Express" title="PCI Express – Greek" lang="el" hreflang="el" data-title="PCI Express" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target">Ελληνικά</a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/PCI_Express" title="PCI Express – Spanish" lang="es" hreflang="es" data-title="PCI Express" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target">Español</a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/PCI-Express" title="PCI-Express – Esperanto" lang="eo" hreflang="eo" data-title="PCI-Express" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target">Esperanto</a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%BE%DB%8C%E2%80%8C%D8%B3%DB%8C%E2%80%8C%D8%A2%DB%8C_%D8%A7%DA%A9%D8%B3%E2%80%8C%D9%BE%D8%B1%D8%B3" title="پی‌سی‌آی اکس‌پرس – Persian" lang="fa" hreflang="fa" data-title="پی‌سی‌آی اکس‌پرس" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target">فارسی</a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/PCI_Express" title="PCI Express – French" lang="fr" hreflang="fr" data-title="PCI Express" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target">Français</a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/PCI_Express" title="PCI Express – Galician" lang="gl" hreflang="gl" data-title="PCI Express" data-language-autonym="Galego" data-language-local-name="Galician" class="interlanguage-link-target">Galego</a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/PCI_%EC%9D%B5%EC%8A%A4%ED%94%84%EB%A0%88%EC%8A%A4" title="PCI 익스프레스 – Korean" lang="ko" hreflang="ko" data-title="PCI 익스프레스" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target">한국어</a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/PCI_Express" title="PCI Express – Croatian" lang="hr" hreflang="hr" data-title="PCI Express" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target">Hrvatski</a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/PCI_Express" title="PCI Express – Indonesian" lang="id" hreflang="id" data-title="PCI Express" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target">Bahasa Indonesia</a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/PCI_Express" title="PCI Express – Italian" lang="it" hreflang="it" data-title="PCI Express" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target">Italiano</a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/PCI_Express" title="PCI Express – Hebrew" lang="he" hreflang="he" data-title="PCI Express" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target">עברית</a></li><li class="interlanguage-link interwiki-kn mw-list-item"><a href="https://kn.wikipedia.org/wiki/%E0%B2%AA%E0%B2%BF%E0%B2%B8%E0%B2%BF%E0%B2%90_%E0%B2%8E%E0%B2%95%E0%B3%8D%E0%B2%B8%E0%B3%8D%E2%80%8C%E0%B2%AA%E0%B3%8D%E0%B2%B0%E0%B3%86%E0%B2%B8%E0%B3%8D%E2%80%8C" title="ಪಿಸಿಐ ಎಕ್ಸ್‌ಪ್ರೆಸ್‌ – Kannada" lang="kn" hreflang="kn" data-title="ಪಿಸಿಐ ಎಕ್ಸ್‌ಪ್ರೆಸ್‌" data-language-autonym="ಕನ್ನಡ" data-language-local-name="Kannada" class="interlanguage-link-target">ಕನ್ನಡ</a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/PCI_Express" title="PCI Express – Lithuanian" lang="lt" hreflang="lt" data-title="PCI Express" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target">Lietuvių</a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/PCI_Express" title="PCI Express – Hungarian" lang="hu" hreflang="hu" data-title="PCI Express" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target">Magyar</a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/PCI_Express" title="PCI Express – Dutch" lang="nl" hreflang="nl" data-title="PCI Express" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target">Nederlands</a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/PCI_Express" title="PCI Express – Japanese" lang="ja" hreflang="ja" data-title="PCI Express" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target">日本語</a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/PCI_Express" title="PCI Express – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="PCI Express" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target">Norsk bokmål</a></li><li class="interlanguage-link interwiki-or mw-list-item"><a href="https://or.wikipedia.org/wiki/%E0%AC%AA%E0%AC%BF_%E0%AC%B8%E0%AC%BF_%E0%AC%86%E0%AC%87_%E0%AC%8F%E0%AC%95%E0%AD%8D%E0%AC%B8%E0%AC%AA%E0%AD%8D%E0%AC%B0%E0%AD%87%E0%AC%B8" title="ପି ସି ଆଇ ଏକ୍ସପ୍ରେସ – Odia" lang="or" hreflang="or" data-title="ପି ସି ଆଇ ଏକ୍ସପ୍ରେସ" data-language-autonym="ଓଡ଼ିଆ" data-language-local-name="Odia" class="interlanguage-link-target">ଓଡ଼ିଆ</a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/PCI_Express" title="PCI Express – Polish" lang="pl" hreflang="pl" data-title="PCI Express" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target">Polski</a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/PCI_Express" title="PCI Express – Portuguese" lang="pt" hreflang="pt" data-title="PCI Express" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target">Português</a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/PCI_Express" title="PCI Express – Romanian" lang="ro" hreflang="ro" data-title="PCI Express" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target">Română</a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/PCI_Express" title="PCI Express – Russian" lang="ru" hreflang="ru" data-title="PCI Express" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target">Русский</a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/PCI_Express" title="PCI Express – Albanian" lang="sq" hreflang="sq" data-title="PCI Express" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target">Shqip</a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/PCI_Express" title="PCI Express – Simple English" lang="en-simple" hreflang="en-simple" data-title="PCI Express" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target">Simple English</a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/PCI-Express" title="PCI-Express – Slovak" lang="sk" hreflang="sk" data-title="PCI-Express" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target">Slovenčina</a></li><li class="interlanguage-link interwiki-sl mw-list-item"><a href="https://sl.wikipedia.org/wiki/PCI_Express" title="PCI Express – Slovenian" lang="sl" hreflang="sl" data-title="PCI Express" data-language-autonym="Slovenščina" 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class="interlanguage-link-target">Svenska</a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Pci-e" title="Pci-e – Turkish" lang="tr" hreflang="tr" data-title="Pci-e" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target">Türkçe</a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/PCI_Express" title="PCI Express – Ukrainian" lang="uk" hreflang="uk" data-title="PCI Express" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target">Українська</a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/PCI_Express" title="PCI Express – Vietnamese" lang="vi" hreflang="vi" data-title="PCI Express" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target">Tiếng Việt</a></li><li class="interlanguage-link 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free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Computer expansion bus standard</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/PCI-X" title="PCI-X">PCI-X</a> or <a href="/wiki/UCIe" title="UCIe">UCIe</a>.</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For Engineering, Procurement, Construction and Installation, see <a href="/wiki/EPCI" title="EPCI">EPCI</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">PCI Express</caption><tbody><tr><td colspan="2" class="infobox-subheader">Peripheral Component Interconnect Express</td></tr><tr><td colspan="2" class="infobox-image"><a href="/wiki/File:PCI_Express.svg" class="mw-file-description"><img alt="Logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e5/PCI_Express.svg/220px-PCI_Express.svg.png" decoding="async" width="220" height="89" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e5/PCI_Express.svg/330px-PCI_Express.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e5/PCI_Express.svg/440px-PCI_Express.svg.png 2x" data-file-width="595" data-file-height="241" /></a><div class="infobox-caption">Logo</div></td></tr><tr><th scope="row" class="infobox-label">Year created</th><td class="infobox-data">2003; 21 years ago (2003)</td></tr><tr><th scope="row" class="infobox-label">Created by</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}</style><div class="hlist"><ul><li><a href="/wiki/Intel" title="Intel">Intel</a></li><li><a href="/wiki/Dell" title="Dell">Dell</a></li><li><a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a></li><li><a href="/wiki/IBM" title="IBM">IBM</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Supersedes</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><div class="hlist"><ul><li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a></li><li><a href="/wiki/PCI-X" title="PCI-X">PCI-X</a></li><li><a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Width in bits</th><td class="infobox-data">1 per lane<a href="#cite_note-1">[1]</a> (up to 16 lanes)</td></tr><tr><th scope="row" class="infobox-label"><abbr title="Number">No.</abbr> of devices</th><td class="infobox-data">1 on each endpoint of each connection.<a href="#cite_note-2">[a]</a></td></tr><tr><th scope="row" class="infobox-label">Speed</th><td class="infobox-data"><a href="/wiki/Dual_simplex" class="mw-redirect" title="Dual simplex">Dual simplex</a>, up to 242 GB/s</td></tr><tr><th scope="row" class="infobox-label">Style</th><td class="infobox-data"><a href="/wiki/Serial_communication" title="Serial communication">Serial</a></td></tr><tr><th scope="row" class="infobox-label">Hotplugging interface</th><td class="infobox-data">Yes (with <a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a>, <a href="#PCI_Express_OCuLink">OCuLink</a>, <a href="/wiki/CFexpress" title="CFexpress">CFexpress</a> or <a href="/wiki/U.2" title="U.2">U.2</a>)</td></tr><tr><th scope="row" class="infobox-label">External interface</th><td class="infobox-data">Yes (with <a href="#PCI_Express_OCuLink">OCuLink</a> or <a href="#PCI_Express_External_Cabling">PCI Express External Cabling</a>)</td></tr><tr><th scope="row" class="infobox-label">Website</th><td class="infobox-data"><a rel="nofollow" class="external text" href="https://pcisig.com/">pcisig.com</a></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIeX16andX1OnAsusH81MKMB.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f4/PCIeX16andX1OnAsusH81MKMB.jpg/220px-PCIeX16andX1OnAsusH81MKMB.jpg" decoding="async" width="220" height="132" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f4/PCIeX16andX1OnAsusH81MKMB.jpg/330px-PCIeX16andX1OnAsusH81MKMB.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f4/PCIeX16andX1OnAsusH81MKMB.jpg/440px-PCIeX16andX1OnAsusH81MKMB.jpg 2x" data-file-width="3440" data-file-height="2064" /></a><figcaption>Two types of PCIe slot on an Asus H81M-K motherboard</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3e/PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg/220px-PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg" decoding="async" width="220" height="149" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3e/PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg/330px-PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3e/PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg/440px-PCI-E_%26_PCI_slots_on_DFI_LanParty_nF4_SLI-DR_20050531.jpg 2x" data-file-width="927" data-file-height="629" /></a><figcaption>Various slots on a <a href="/wiki/Computer_motherboard" class="mw-redirect" title="Computer motherboard">computer motherboard</a>, from top to bottom: <div><ul><li>PCI Express x4</li><li>PCI Express x16</li><li>PCI Express x1</li><li>PCI Express x16</li><li><a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">Conventional PCI</a> (32-bit, 5 V)</li></ul></div></figcaption></figure> PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e,<a href="#cite_note-s5NDG-3">[2]</a> is a high-speed <a href="/wiki/Serial_communication" title="Serial communication">serial</a> <a href="/wiki/Computer" title="Computer">computer</a> <a href="/wiki/Expansion_bus" class="mw-redirect" title="Expansion bus">expansion bus</a> standard, designed to replace the older <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">PCI</a>, <a href="/wiki/PCI-X" title="PCI-X">PCI-X</a> and <a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> bus standards. It is the common <a href="/wiki/Motherboard" title="Motherboard">motherboard</a> interface for personal computers' <a href="/wiki/Video_card" class="mw-redirect" title="Video card">graphics cards</a>, <a href="/wiki/Capture_card" class="mw-redirect" title="Capture card">capture cards</a>, <a href="/wiki/Sound_card" title="Sound card">sound cards</a>, <a href="/wiki/Hard_disk_drive" title="Hard disk drive">hard disk drive</a> <a href="/wiki/Host_adapter" title="Host adapter">host adapters</a>, <a href="/wiki/Solid-state_drive" title="Solid-state drive">SSDs</a>, <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a>, and <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> hardware connections.<a href="#cite_note-DQmzv-4">[3]</a> PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER),<a href="#cite_note-gf9Lm-5">[4]</a> and native <a href="/wiki/Hot_swapping" title="Hot swapping">hot-swap</a> functionality. More recent revisions of the PCIe standard provide hardware support for <a href="/wiki/I/O_virtualization" title="I/O virtualization">I/O virtualization</a>. The PCI Express electrical interface is measured by the number of simultaneous lanes.<a href="#cite_note-sxOen-6">[5]</a> (A lane is a single send/receive line of data, analogous to a "one-lane road" having one lane of traffic in both directions.) The interface is also used in a variety of other standards — most notably the <a href="/wiki/Laptop" title="Laptop">laptop</a> expansion card interface called <a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a>. It is also used in the storage interfaces of <a href="/wiki/SATA_Express" title="SATA Express">SATA Express</a>, <a href="/wiki/U.2" title="U.2">U.2</a> (SFF-8639) and <a href="/wiki/M.2" title="M.2">M.2</a>. Formal specifications are maintained and developed by the <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a> (PCI <a href="/wiki/Special_Interest_Group" class="mw-redirect" title="Special Interest Group">Special Interest Group</a>) — a group of more than 900 companies that also maintains the <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">conventional PCI</a> specifications. <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Architecture">Architecture</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=1" title="Edit section: Architecture">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Example_PCI_Express_Topology.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Example_PCI_Express_Topology.svg/280px-Example_PCI_Express_Topology.svg.png" decoding="async" width="280" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Example_PCI_Express_Topology.svg/420px-Example_PCI_Express_Topology.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Example_PCI_Express_Topology.svg/560px-Example_PCI_Express_Topology.svg.png 2x" data-file-width="830" data-file-height="490" /></a><figcaption>Example of the PCI Express topology: white "junction boxes" represent PCI Express device downstream ports, while the gray ones represent upstream ports.<a href="#cite_note-pcie-basics-7">[6]</a>: 7 </figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:RouterBOARD_RB14e,_top_view.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/86/RouterBOARD_RB14e%2C_top_view.jpg/280px-RouterBOARD_RB14e%2C_top_view.jpg" decoding="async" width="280" height="210" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/86/RouterBOARD_RB14e%2C_top_view.jpg/420px-RouterBOARD_RB14e%2C_top_view.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/86/RouterBOARD_RB14e%2C_top_view.jpg/560px-RouterBOARD_RB14e%2C_top_view.jpg 2x" data-file-width="1280" data-file-height="960" /></a><figcaption>PCI Express x1 card containing a PCI Express switch (covered by a small <a href="/wiki/Heat_sink" title="Heat sink">heat sink</a>), which creates multiple endpoints out of one endpoint and lets multiple devices share it</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCie_lanes.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/PCie_lanes.jpg/220px-PCie_lanes.jpg" decoding="async" width="220" height="131" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/PCie_lanes.jpg/330px-PCie_lanes.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3a/PCie_lanes.jpg/440px-PCie_lanes.jpg 2x" data-file-width="1371" data-file-height="817" /></a><figcaption>The PCIe slots on a motherboard are often labeled with the number of PCIe lanes they have. Sometimes what may seem like a large slot may only have a few lanes. For instance, a x16 slot with only 4 PCIe lanes (bottom slot) is quite common.<a href="#cite_note-8">[7]</a></figcaption></figure> Conceptually, the PCI Express bus is a high-speed <a href="/wiki/Serial_communication" title="Serial communication">serial</a> replacement of the older PCI/PCI-X bus.<a href="#cite_note-howstuffworks1-9">[8]</a> One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared <a href="/wiki/Parallel_communications" class="mw-redirect" title="Parallel communications">parallel</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">bus</a> architecture, in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on point-to-point <a href="/wiki/Network_topology" title="Network topology">topology</a>, with separate <a href="/wiki/Serial_communication" title="Serial communication">serial</a> links connecting every device to the <a href="/wiki/Root_complex" title="Root complex">root complex</a> (host). Because of its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports <a href="/wiki/Full-duplexed" class="mw-redirect" title="Full-duplexed">full-duplex</a> communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints. In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible. The PCI Express link between two devices can vary in size from one to 16 <a href="#Lane">lanes</a>. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The lane count is automatically negotiated during device initialization and can be restricted by either endpoint. For example, a single-lane PCI Express (x1) card can be inserted into a multi-lane slot (x4, x8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of x1, x2, x4, x8, and x16. Up to and including PCIe 5.0, x12, and x32 links were defined as well but never used.<a href="#cite_note-4TrCr-10">[9]</a> This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking (<a href="/wiki/10_Gigabit_Ethernet" title="10 Gigabit Ethernet">10 Gigabit Ethernet</a> or multiport <a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">Gigabit Ethernet</a>), and enterprise storage (<a href="/wiki/Serial_attached_SCSI" class="mw-redirect" title="Serial attached SCSI">SAS</a> or <a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a>). Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size. As a point of reference, a PCI-X (133 MHz 64-bit) device and a PCI Express 1.0 device using four lanes (x4) have roughly the same peak single-direction transfer rate of 1064 MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is <a href="/wiki/Two-way_communication" title="Two-way communication">bidirectional</a>. <div class="mw-heading mw-heading3"><h3 id="Interconnect">Interconnect</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=2" title="Edit section: Interconnect">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCI_Express_Terminology.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a1/PCI_Express_Terminology.svg/220px-PCI_Express_Terminology.svg.png" decoding="async" width="220" height="182" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a1/PCI_Express_Terminology.svg/330px-PCI_Express_Terminology.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a1/PCI_Express_Terminology.svg/440px-PCI_Express_Terminology.svg.png 2x" data-file-width="574" data-file-height="474" /></a><figcaption>A PCI Express link between two devices consists of one or more lanes, which are <a href="/wiki/Dual_simplex" class="mw-redirect" title="Dual simplex">dual simplex</a> channels using two <a href="/wiki/Differential_signaling" class="mw-redirect" title="Differential signaling">differential signaling</a> pairs.<a href="#cite_note-pcie-basics-7">[6]</a>: 3 </figcaption></figure> PCI Express devices communicate via a logical connection called an interconnect<a href="#cite_note-faq1-11">[10]</a> or link. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and <a href="/wiki/Interrupt" title="Interrupt">interrupts</a> (<a href="/wiki/Peripheral_Component_Interconnect#Interrupts" title="Peripheral Component Interconnect">INTx</a>, <a href="/wiki/Message_Signaled_Interrupts" title="Message Signaled Interrupts">MSI or MSI-X</a>). At the physical level, a link is composed of one or more lanes.<a href="#cite_note-faq1-11">[10]</a> Low-speed peripherals (such as an <a href="/wiki/IEEE_802.11" title="IEEE 802.11">802.11</a> <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a> <a href="/wiki/Wireless_network_interface_card" class="mw-redirect" title="Wireless network interface card">card</a>) use a single-lane (x1) link, while a graphics adapter typically uses a much wider and therefore faster 16-lane (x16) link. <div class="mw-heading mw-heading3"><h3 id="Lane">Lane</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=3" title="Edit section: Lane">edit</a>]</div> A lane is composed of two <a href="/wiki/Differential_signaling" class="mw-redirect" title="Differential signaling">differential signaling</a> pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or <a href="/wiki/Signal_trace" title="Signal trace">signal traces</a>. Conceptually, each lane is used as a <a href="/wiki/Full-duplex" class="mw-redirect" title="Full-duplex">full-duplex</a> <a href="/wiki/Byte_stream" class="mw-redirect" title="Byte stream">byte stream</a>, transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link.<a href="#cite_note-2Nt8T-12">[11]</a> Physical PCI Express links may contain 1, 4, 8 or 16 lanes.<a href="#cite_note-Gchhw-13">[12]</a><a href="#cite_note-pcie-basics-7">[6]</a>: 4, 5 <a href="#cite_note-faq1-11">[10]</a> Lane counts are written with an "x" prefix (for example, "x8" represents an eight-lane card or slot), with x16 being the largest size in common use.<a href="#cite_note-odC7t-14">[13]</a> Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide." For mechanical card sizes, see <a href="#Form_factors">below</a>. <div class="mw-heading mw-heading3"><h3 id="Serial_bus">Serial bus</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=4" title="Edit section: Serial bus">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Unreferenced_section plainlinks metadata ambox ambox-content ambox-Unreferenced" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></div></td><td class="mbox-text"><div class="mbox-text-span">This section does not <a href="/wiki/Wikipedia:Citing_sources" title="Wikipedia:Citing sources">cite</a> any <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">sources</a>. Please help <a href="/wiki/Special:EditPage/PCI_Express" title="Special:EditPage/PCI Express">improve this section</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and <a href="/wiki/Wikipedia:Verifiability#Burden_of_evidence" title="Wikipedia:Verifiability">removed</a>. (March 2018) (<a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a>)</div></td></tr></tbody></table> The bonded serial <a href="/wiki/Bus_(computing)" title="Bus (computing)">bus</a> architecture was chosen over the traditional parallel bus because of the inherent limitations of the latter, including <a href="/wiki/Half-duplex" class="mw-redirect" title="Half-duplex">half-duplex</a> operation, excess signal count, and inherently lower <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> due to <a href="/wiki/Timing_skew" class="mw-redirect" title="Timing skew">timing skew</a>. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a> (PCB) layers, and at possibly different <a href="/wiki/Signal_velocity" title="Signal velocity">signal velocities</a>. Despite being transmitted simultaneously as a single <a href="/wiki/Word_(data_type)" class="mw-redirect" title="Word (data type)">word</a>, signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz. <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIe_vs_PCI.gif" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/24/PCIe_vs_PCI.gif/220px-PCIe_vs_PCI.gif" decoding="async" width="220" height="94" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/24/PCIe_vs_PCI.gif/330px-PCIe_vs_PCI.gif 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/24/PCIe_vs_PCI.gif/440px-PCIe_vs_PCI.gif 2x" data-file-width="1550" data-file-height="660" /></a><figcaption>Highly simplified topologies of the Legacy PCI Shared (Parallel) Interface and the PCIe Serial Point-to-Point Interface<a href="#cite_note-P7MD8-15">[14]</a></figcaption></figure> A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is <a href="/wiki/Clock_recovery" title="Clock recovery">embedded</a> within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include <a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">Serial ATA</a> (SATA), <a href="/wiki/USB" title="USB">USB</a>, <a href="/wiki/Serial_Attached_SCSI" title="Serial Attached SCSI">Serial Attached SCSI</a> (SAS), <a href="/wiki/FireWire" class="mw-redirect" title="FireWire">FireWire</a> (IEEE 1394), and <a href="/wiki/RapidIO" title="RapidIO">RapidIO</a>. In digital video, examples in common use are <a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a>, <a href="/wiki/HDMI" title="HDMI">HDMI</a>, and <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>. Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices. <div class="mw-heading mw-heading2"><h2 id="Form_factors">Form factors</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=5" title="Edit section: Form factors">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_(standard)">PCI Express (standard)</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=6" title="Edit section: PCI Express (standard)">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_P3608_NVMe_flash_SSD,_PCI-E_add-in_card.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg/220px-Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg" decoding="async" width="220" height="141" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg/330px-Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg/440px-Intel_P3608_NVMe_flash_SSD%2C_PCI-E_add-in_card.jpg 2x" data-file-width="3000" data-file-height="1928" /></a><figcaption>Intel P3608 NVMe flash SSD, PCIe add-in card</figcaption></figure>A PCI Express card fits into a slot of its physical size or larger (with x16 as the largest used), but may not fit into a smaller PCI Express slot; for example, a x16 card may not fit into a x4 or x8 slot. Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical and logical connection. The number of lanes actually connected to a slot may also be fewer than the number supported by the physical slot size. An example is a x16 slot that runs at x4, which accepts any x1, x2, x4, x8 or x16 card, but provides only four lanes. Its specification may read as "x16 (x4 mode)", while "mechanical @ electrical" notation (e.g. "x16 @ x4") is also common.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] The advantage is that such slots can accommodate a larger range of PCI Express cards without requiring motherboard hardware to support the full transfer rate. Standard mechanical sizes are x1, x4, x8, and x16. Cards using a number of lanes other than the standard mechanical sizes need to physically fit the next larger mechanical size (e.g. an x2 card uses the x4 size, or an x12 card uses the x16 size). The cards themselves are designed and manufactured in various sizes. For example, <a href="/wiki/Solid-state_drive" title="Solid-state drive">solid-state drives</a> (SSDs) that come in the form of PCI Express cards often use <a href="/wiki/Conventional_PCI#Low-profile_cards" class="mw-redirect" title="Conventional PCI">HHHL</a> (half height, half length) and <a href="/wiki/Conventional_PCI#Half-length_full-height_card" class="mw-redirect" title="Conventional PCI">FHHL</a> (full height, half length) to describe the physical dimensions of the card.<a href="#cite_note-8AKZj-16">[15]</a><a href="#cite_note-c1yve-17">[16]</a> <table class="wikitable"> <tbody><tr> <th rowspan="2"">PCI card type </th> <th colspan="2">Dimensions height × length × width, maximum </th></tr> <tr> <th>(mm) </th> <th>(in) </th></tr> <tr> <td>Full-Length </td> <td>111.15 × 312.00 × 20.32 </td> <td>4.376 × 12.283 × 0.8 </td></tr> <tr> <td>Half-Length </td> <td>111.15 × 167.65 × 20.32 </td> <td>4.376 × 06.600 × 0.8 </td></tr> <tr> <td>Low-Profile/Slim </td> <td>068.90 × 167.65 × 20.32 </td> <td>2.731 × 06.600 × 0.8 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Non-standard_video_card_form_factors">Non-standard video card form factors</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=7" title="Edit section: Non-standard video card form factors">edit</a>]</div> Modern (since <abbr title="circa">c.</abbr> 2012<a href="#cite_note-j6TTS-18">[17]</a>) gaming <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video cards</a> usually exceed the height as well as thickness specified in the PCI Express standard, due to the need for more capable and quieter <a href="/wiki/Computer_fan" title="Computer fan">cooling fans</a>, as gaming video cards often emit hundreds of watts of heat.<a href="#cite_note-RAreG-19">[18]</a> Modern computer cases are often wider to accommodate these taller cards, but not always. Since full-length cards (312 mm) are uncommon, modern cases sometimes cannot fit those. The thickness of these cards also typically occupies the space of 2 to 5<a href="#cite_note-20">[19]</a> PCIe slots. In fact, even the methodology of how to measure the cards varies between vendors, with some including the metal bracket size in dimensions and others not. For instance, comparing three high-end video cards released in 2020: a <a href="/wiki/Sapphire_Technology" title="Sapphire Technology">Sapphire</a> <a href="/wiki/Radeon_RX_5000_series" title="Radeon RX 5000 series">Radeon RX 5700 XT</a> card measures 135 mm in height (excluding the metal bracket), which exceeds the PCIe standard height by 28 mm,<a href="#cite_note-E0Tsg-21">[20]</a> another Radeon RX 5700 XT card by <a href="/wiki/XFX" title="XFX">XFX</a> measures 55 mm thick (i.e. 2.7 PCI slots at 20.32 mm), taking up 3 PCIe slots,<a href="#cite_note-mAt96-22">[21]</a> while an <a href="/wiki/Asus" title="Asus">Asus</a> <a href="/wiki/GeForce_30_series" title="GeForce 30 series">GeForce RTX 3080</a> video card takes up two slots and measures 140.1 mm × 318.5 mm × 57.8 mm, exceeding PCI Express' maximum height, length, and thickness respectively.<a href="#cite_note-kk3xz-23">[22]</a> <div class="mw-heading mw-heading4"><h4 id="Pinout">Pinout</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=8" title="Edit section: Pinout">edit</a>]</div> The following table identifies the conductors on each side of the <a href="/wiki/Edge_connector" title="Edge connector">edge connector</a> on a PCI Express card. The solder side of the <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a> (PCB) is the A-side, and the component side is the B-side.<a href="#cite_note-IM1RH-24">[23]</a> PRSNT1# and PRSNT2# pins must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted. The WAKE# pin uses full voltage to wake the computer, but must be <a href="/wiki/Pull_up_resistor" class="mw-redirect" title="Pull up resistor">pulled high</a> from the standby power to indicate that the card is wake capable.<a href="#cite_note-PCIe_card_2-25">[24]</a> <table class="wikitable"> <caption>PCI Express connector pinout (x1, x4, x8 and x16 variants) </caption> <tbody><tr> <th>Pin</th> <th>Side B</th> <th>Side A</th> <th>Description </th> <td rowspan="54"> </td> <th>Pin</th> <th>Side B</th> <th>Side A</th> <th>Description </th></tr> <tr> <th>01 </th> <td style="background:silver">+12 V</td> <td style="background:#9f9">PRSNT1#</td> <td align="left">Must connect to farthest PRSNT2# pin </td> <th>50 </th> <td style="background:#99f">HSOp(8)</td> <td style="background:#ff9">Reserved</td> <td rowspan="2" style="text-align:left;">Lane 8 transmit data, + and − </td></tr> <tr> <th>02 </th> <td style="background:silver">+12 V</td> <td style="background:silver">+12 V</td> <td rowspan="2" style="text-align:left;">Main power pins </td> <th>51 </th> <td style="background:#99f">HSOn(8)</td> <td style="background:#999">Ground </td></tr> <tr> <th>03 </th> <td style="background:silver">+12 V</td> <td style="background:silver">+12 V </td> <th>52 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(8)</td> <td rowspan="2" style="text-align:left;">Lane 8 receive data, + and − </td></tr> <tr> <th>04 </th> <td style="background:#999">Ground</td> <td style="background:#999">Ground</td> <td> </td> <th>53 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(8) </td></tr> <tr> <th>05 </th> <td style="background:#fc6">SMCLK</td> <td style="background:#99f">TCK</td> <td rowspan="5" style="text-align:left;"><a href="/wiki/SMBus" class="mw-redirect" title="SMBus">SMBus</a> and <a href="/wiki/JTAG" title="JTAG">JTAG</a> port pins </td> <th>54 </th> <td style="background:#99f">HSOp(9)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 9 transmit data, + and − </td></tr> <tr> <th>06 </th> <td style="background:#fc6">SMDAT</td> <td style="background:#99f">TDI </td> <th>55 </th> <td style="background:#99f">HSOn(9)</td> <td style="background:#999">Ground </td></tr> <tr> <th>07 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">TDO </td> <th>56 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(9)</td> <td rowspan="2" style="text-align:left;">Lane 9 receive data, + and − </td></tr> <tr> <th>08 </th> <td style="background:silver">+3.3 V</td> <td style="background:#99f">TMS </td> <th>57 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(9) </td></tr> <tr> <th>09 </th> <td style="background:#99f">TRST#</td> <td style="background:silver">+3.3 V </td> <th>58 </th> <td style="background:#99f">HSOp(10)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 10 transmit data, + and − </td></tr> <tr> <th>10 </th> <td style="background:silver">+3.3 V aux</td> <td style="background:silver">+3.3 V</td> <td align="left">Aux power & <a href="/wiki/Standby_power" title="Standby power">Standby power</a> </td> <th>59 </th> <td style="background:#99f">HSOn(10)</td> <td style="background:#999">Ground </td></tr> <tr> <th>11 </th> <td style="background:#fc6">WAKE#</td> <td style="background:#fc6">PERST#</td> <td align="left">Link reactivation; fundamental reset <a href="#cite_note-ajnim-26">[25]</a> </td> <th>60 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(10)</td> <td rowspan="2" style="text-align:left;">Lane 10 receive data, + and − </td></tr> <tr> <th colspan="4">Key notch </th> <th>61 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(10) </td></tr> <tr> <th>12 </th> <td style="background:#f9f">CLKREQ#<a href="#cite_note-vj2hg-27">[26]</a></td> <td style="background:#999">Ground</td> <td align="left">Clock Request Signal </td> <th>62 </th> <td style="background:#99f">HSOp(11)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 11 transmit data, + and − </td></tr> <tr> <th>13 </th> <td style="background:#999">Ground</td> <td style="background:#99f">REFCLK+</td> <td align="left">Reference clock differential pair </td> <th>63 </th> <td style="background:#99f">HSOn(11)</td> <td style="background:#999">Ground </td></tr> <tr> <th>14 </th> <td style="background:#99f">HSOp(0)</td> <td style="background:#99f">REFCLK−</td> <td rowspan="2" style="text-align:left;">Lane 0 transmit data, + and − </td> <th>64 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(11)</td> <td rowspan="2" style="text-align:left;">Lane 11 receive data, + and − </td></tr> <tr> <th>15 </th> <td style="background:#99f">HSOn(0)</td> <td style="background:#999">Ground </td> <th>65 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(11) </td></tr> <tr> <th>16 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(0)</td> <td rowspan="2" style="text-align:left;">Lane 0 receive data, + and − </td> <th>66 </th> <td style="background:#99f">HSOp(12)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 12 transmit data, + and − </td></tr> <tr> <th>17 </th> <td style="background:#9f9">PRSNT2#</td> <td style="background:#f9f">HSIn(0) </td> <th>67 </th> <td style="background:#99f">HSOn(12)</td> <td style="background:#999">Ground </td></tr> <tr> <th>18 </th> <td style="background:#999">Ground</td> <td style="background:#999">Ground</td> <td> </td> <th>68 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(12)</td> <td rowspan="2" style="text-align:left;">Lane 12 receive data, + and − </td></tr> <tr> <td colspan="4">PCI Express x1 cards end at pin 18 </td> <th>69 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(12) </td></tr> <tr> <th>19 </th> <td style="background:#99f">HSOp(1)</td> <td style="background:#ff9">Reserved</td> <td rowspan="2" style="text-align:left;">Lane 1 transmit data, + and − </td> <th>70 </th> <td style="background:#99f">HSOp(13)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 13 transmit data, + and − </td></tr> <tr> <th>20 </th> <td style="background:#99f">HSOn(1)</td> <td style="background:#999">Ground </td> <th>71 </th> <td style="background:#99f">HSOn(13)</td> <td style="background:#999">Ground </td></tr> <tr> <th>21 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(1)</td> <td rowspan="2" style="text-align:left;">Lane 1 receive data, + and − </td> <th>72 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(13)</td> <td rowspan="2" style="text-align:left;">Lane 13 receive data, + and − </td></tr> <tr> <th>22 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(1) </td> <th>73 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(13) </td></tr> <tr> <th>23 </th> <td style="background:#99f">HSOp(2)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 2 transmit data, + and − </td> <th>74 </th> <td style="background:#99f">HSOp(14)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 14 transmit data, + and − </td></tr> <tr> <th>24 </th> <td style="background:#99f">HSOn(2)</td> <td style="background:#999">Ground </td> <th>75 </th> <td style="background:#99f">HSOn(14)</td> <td style="background:#999">Ground </td></tr> <tr> <th>25 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(2)</td> <td rowspan="2" style="text-align:left;">Lane 2 receive data, + and − </td> <th>76 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(14)</td> <td rowspan="2" style="text-align:left;">Lane 14 receive data, + and − </td></tr> <tr> <th>26 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(2) </td> <th>77 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(14) </td></tr> <tr> <th>27 </th> <td style="background:#99f">HSOp(3)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 3 transmit data, + and − </td> <th>78 </th> <td style="background:#99f">HSOp(15)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 15 transmit data, + and − </td></tr> <tr> <th>28 </th> <td style="background:#99f">HSOn(3)</td> <td style="background:#999">Ground </td> <th>79 </th> <td style="background:#99f">HSOn(15)</td> <td style="background:#999">Ground </td></tr> <tr> <th>29 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(3)</td> <td rowspan="2" style="text-align:left;">Lane 3 receive data, + and − "Power brake", active-low to reduce device power </td> <th>80 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(15)</td> <td rowspan="2" style="text-align:left;">Lane 15 receive data, + and − </td></tr> <tr> <th>30 </th> <td style="background:#fc6">PWRBRK#<a href="#cite_note-YpQVq-28">[27]</a></td> <td style="background:#f9f">HSIn(3) </td> <th>81 </th> <td style="background:#9f9">PRSNT2#</td> <td style="background:#f9f">HSIn(15) </td></tr> <tr> <th>31 </th> <td style="background:#9f9">PRSNT2#</td> <td style="background:#999">Ground</td> <td rowspan="2"> </td> <th>82 </th> <td style="background:#ff9">Reserved</td> <td style="background:#999">Ground</td> <td> </td></tr> <tr> <th>32 </th> <td style="background:#999">Ground</td> <td style="background:#ff9">Reserved </td></tr> <tr> <td colspan="4">PCI Express x4 cards end at pin 32 </td></tr> <tr> <th>33 </th> <td style="background:#99f">HSOp(4)</td> <td style="background:#ff9">Reserved</td> <td rowspan="2" style="text-align:left;">Lane 4 transmit data, + and − </td></tr> <tr> <th>34 </th> <td style="background:#99f">HSOn(4)</td> <td style="background:#999">Ground </td></tr> <tr> <th>35 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(4)</td> <td rowspan="2" style="text-align:left;">Lane 4 receive data, + and − </td></tr> <tr> <th>36 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(4) </td></tr> <tr> <th>37 </th> <td style="background:#99f">HSOp(5)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 5 transmit data, + and − </td></tr> <tr> <th>38 </th> <td style="background:#99f">HSOn(5)</td> <td style="background:#999">Ground </td></tr> <tr> <th>39 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(5)</td> <td rowspan="2" style="text-align:left;">Lane 5 receive data, + and − </td></tr> <tr> <th>40 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(5) </td></tr> <tr> <th>41 </th> <td style="background:#99f">HSOp(6)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 6 transmit data, + and − </td></tr> <tr> <th>42 </th> <td style="background:#99f">HSOn(6)</td> <td style="background:#999">Ground </td></tr> <tr> <th>43 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(6)</td> <td rowspan="2" style="text-align:left;">Lane 6 receive data, + and − </td> <th colspan="4">Legend </th></tr> <tr> <th>44 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIn(6) </td> <th style="background:#999" colspan="2">Ground pin </th> <td colspan="2" style="text-align:left;">Zero volt reference </td></tr> <tr> <th>45 </th> <td style="background:#99f">HSOp(7)</td> <td style="background:#999">Ground</td> <td rowspan="2" style="text-align:left;">Lane 7 transmit data, + and − </td> <th style="background:silver" colspan="2">Power pin </th> <td colspan="2" style="text-align:left;">Supplies power to the PCIe card </td></tr> <tr> <th>46 </th> <td style="background:#99f">HSOn(7)</td> <td style="background:#999">Ground </td> <th style="background:#f9f" colspan="2">Card-to-host pin </th> <td colspan="2" style="text-align:left;">Signal from the card to the motherboard </td></tr> <tr> <th>47 </th> <td style="background:#999">Ground</td> <td style="background:#f9f">HSIp(7)</td> <td rowspan="2" style="text-align:left;">Lane 7 receive data, + and − </td> <th style="background:#99f" colspan="2">Host-to-card pin </th> <td colspan="2" style="text-align:left;">Signal from the motherboard to the card </td></tr> <tr> <th>48 </th> <td style="background:#9f9">PRSNT2#</td> <td style="background:#f9f">HSIn(7) </td> <th style="background:#fc6" colspan="2"><a href="/wiki/Open_drain" class="mw-redirect" title="Open drain">Open drain</a> </th> <td colspan="2" style="text-align:left;">May be pulled low or sensed by multiple cards </td></tr> <tr> <th>49 </th> <td style="background:#999">Ground</td> <td style="background:#999">Ground</td> <td> </td> <th style="background:#9f9" colspan="2">Sense pin </th> <td colspan="2" style="text-align:left;">Tied together on card </td></tr> <tr> <td colspan="4">PCI Express x8 cards end at pin 49 </td> <th style="background:#ff9" colspan="2">Reserved </th> <td colspan="2" style="text-align:left;">Not presently used, do not connect </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Power">Power</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=9" title="Edit section: Power">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Powering_of_PCIe_Slot.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/ac/Powering_of_PCIe_Slot.png/280px-Powering_of_PCIe_Slot.png" decoding="async" width="280" height="199" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/ac/Powering_of_PCIe_Slot.png/420px-Powering_of_PCIe_Slot.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/ac/Powering_of_PCIe_Slot.png/560px-Powering_of_PCIe_Slot.png 2x" data-file-width="1200" data-file-height="851" /></a><figcaption>The main 12 <a href="/wiki/Volt" title="Volt">V</a> power supply for the PCIe slot is pins B2, B3 (side B) and pins A2, A3 (side A). Power standby 3.3 <a href="/wiki/Volt" title="Volt">V</a> is pin B10 and A10. PCIe x1 cards can receive up to 25 <a href="/wiki/Watt" title="Watt">W</a> and x16 graphics cards can receive up to 75 <a href="/wiki/Watt" title="Watt">W</a>, combined.<a href="#cite_note-29">[28]</a></figcaption></figure> <div class="mw-heading mw-heading5"><h5 id="Slot_power">Slot power</h5>[<a href="/w/index.php?title=PCI_Express&action=edit&section=10" title="Edit section: Slot power">edit</a>]</div> All PCI express cards may consume up to 3 <a href="/wiki/Ampere" title="Ampere">A</a> at +3.3 <a href="/wiki/Volt" title="Volt">V</a> (9.9 <a href="/wiki/Watt" title="Watt">W</a>). The amount of +12 V and total power they may consume depends on the form factor and the role of the card:<a href="#cite_note-CEM1.1-30">[29]</a>: 35–36 <a href="#cite_note-jArAO-31">[30]</a><a href="#cite_note-32">[31]</a> <ul><li>x1 cards are limited to 0.5 A at +12 V (6 W) and 10 W combined.</li> <li>x4 and wider cards are limited to 2.1 A at +12 V (25 W) and 25 W combined.</li> <li>A full-sized x1 card may draw up to the 25 W limits after initialization and software configuration as a high-power device.</li> <li>A full-sized x16 graphics card may draw up to 5.5 A at +12 V (66 W) and 75 W combined after initialization and software configuration as a high-power device.<a href="#cite_note-PCIe_card_2-25">[24]</a>: 38–39 </li></ul> <div class="mw-heading mw-heading5"><h5 id="6-_and_8-pin_power_connectors">6- and 8-pin power connectors</h5>[<a href="/w/index.php?title=PCI_Express&action=edit&section=11" title="Edit section: 6- and 8-pin power connectors">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg/280px-PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg" decoding="async" width="280" height="104" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg/420px-PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/af/PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg/560px-PCI_Express_Power_Supply_Connector-female_PNr%C2%B00438.jpg 2x" data-file-width="3772" data-file-height="1398" /></a><figcaption>8-pin (left) and 6-pin (right) <a href="/wiki/Molex_Mini-fit_Jr." class="mw-redirect" title="Molex Mini-fit Jr.">power connectors</a> used on PCI Express cards</figcaption></figure> Optional connectors add 75 <a href="/wiki/Watt" title="Watt">W</a> (6-pin) or 150 <a href="/wiki/Watt" title="Watt">W</a> (8-pin) of +12 V power for up to 300 <a href="/wiki/Watt" title="Watt">W</a> total (2 × 75 W + 1 × 150 W). <ul><li>Sense0 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.</li> <li>Sense1 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.</li></ul> Some cards use two 8-pin connectors, but this has not been standardized yet as of 2018<a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&action=edit">[update]</a>, therefore such cards must not carry the official PCI Express logo. This configuration allows 375 W total (1 × 75 W + 2 × 150 W) and will likely be standardized by PCI-SIG with the PCI Express 4.0 standard.[<a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers">needs update</a>] The 8-pin PCI Express connector could be confused with the <a href="/wiki/EPS12V" class="mw-redirect" title="EPS12V">EPS12V</a> connector, which is mainly used for powering SMP and multi-core systems. The power connectors are variants of the Molex Mini-Fit Jr. series connectors.<a href="#cite_note-JuErgh-33">[32]</a> <table class="wikitable"> <caption>Molex Mini-Fit Jr. part numbers<a href="#cite_note-JuErgh-33">[32]</a> </caption> <tbody><tr> <th>Pins </th> <th>Female/receptacle on PS cable </th> <th>Male/right-angle header on PCB </th></tr> <tr> <td>6-pin </td> <td>45559-0002 </td> <td>45558-0003 </td></tr> <tr> <td>8-pin </td> <td>45587-0004 </td> <td>45586-0005, 45586-0006 </td></tr></tbody></table> <table class="wikitable"> <tbody><tr> <th colspan="2">6-pin power connector (75 W)<a href="#cite_note-o2GFI-34">[33]</a> </th> <td rowspan="10"> </td> <th colspan="2">8-pin power connector (150 W)<a href="#cite_note-uLc7Q-35">[34]</a><a href="#cite_note-CEM3.0-36">[35]</a><a href="#cite_note-mcd6L-37">[36]</a> </th> <td rowspan="10"><figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIe6connector.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/f/fa/PCIe6connector.png" decoding="async" width="58" height="34" class="mw-file-element" data-file-width="58" data-file-height="34" /></a><figcaption>6 pin power connector pin map</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIe8connector.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/e/e0/PCIe8connector.png" decoding="async" width="72" height="34" class="mw-file-element" data-file-width="72" data-file-height="34" /></a><figcaption>8 pin power connector pin map</figcaption></figure> </td></tr> <tr> <th>Pin</th> <th>Description </th> <th>Pin</th> <th>Description </th></tr> <tr> <td>1</td> <td>+12 V </td> <td>1</td> <td>+12 V </td></tr> <tr> <td>2</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Not connected (usually +12 V as well) </td> <td>2</td> <td>+12 V </td></tr> <tr> <td>3</td> <td>+12 V </td> <td>3</td> <td>+12 V </td></tr> <tr> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"> </td> <td>4</td> <td>Sense1 (8-pin connected<a href="#cite_note-38">[A]</a>) </td></tr> <tr> <td>4</td> <td>Ground </td> <td>5</td> <td>Ground </td></tr> <tr> <td>5</td> <td>Sense </td> <td>6</td> <td>Sense0 (6-pin or 8-pin connected) </td></tr> <tr> <td>6</td> <td>Ground </td> <td>7</td> <td>Ground </td></tr> <tr> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"> </td> <td>8</td> <td>Ground </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-upper-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-38"><a href="#cite_ref-38">^</a> When a 6-pin connector is plugged into an 8-pin receptacle the card is notified by a missing Sense1 that it may only use up to 75 W. </li> </ol></div></div> <div class="mw-heading mw-heading5"><h5 id="12VHPWR_connector">12VHPWR connector</h5>[<a href="/w/index.php?title=PCI_Express&action=edit&section=12" title="Edit section: 12VHPWR connector">edit</a>]</div> <div class="excerpt-block"><style data-mw-deduplicate="TemplateStyles:r1066933788">.mw-parser-output .excerpt-hat .mw-editsection-like{font-style:normal}</style><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable dablink excerpt-hat selfref">This section is an excerpt from <a href="/wiki/16-pin_12VHPWR_connector" title="16-pin 12VHPWR connector">16-pin 12VHPWR connector</a>.[<a class="external text" href="https://en.wikipedia.org/w/index.php?title=16-pin_12VHPWR_connector&action=edit">edit</a>]</div><div class="excerpt"> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Nvidia_12VHPWR_adapter.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Nvidia_12VHPWR_adapter.jpg/220px-Nvidia_12VHPWR_adapter.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Nvidia_12VHPWR_adapter.jpg/330px-Nvidia_12VHPWR_adapter.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Nvidia_12VHPWR_adapter.jpg/440px-Nvidia_12VHPWR_adapter.jpg 2x" data-file-width="4000" data-file-height="3000" /></a><figcaption>12VHPWR adapter (12VHPWR output on the left, four 8-pin inputs on the right) supplied with Nvidia RTX 4090 cards</figcaption></figure> The <a href="/wiki/16-pin_12VHPWR_connector" title="16-pin 12VHPWR connector">16-pin 12VHPWR connector</a> is a standard for connecting <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs) to <a href="/wiki/Power_supply_unit_(computer)" title="Power supply unit (computer)">computer power supplies</a> for up to 600 W power delivery. It was introduced in 2022 to supersede the previous 6- and 8-pin power connectors for GPUs. The primary aim was to cater to the increasing power requirements of high-performance GPUs. It was replaced by a minor revision called 12V-2x6, which changed the connector to ensure that the sense pins only make contact if the power pins are seated properly. The original connector was formally adopted as part of PCI Express 5.x,<a href="#cite_note-39">[37]</a> while the revised 12V-2x6 connector design was adopted later.<a href="#cite_note-40">[38]</a></div></div> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_Mini_Card">PCI Express Mini Card</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=13" title="Edit section: PCI Express Mini Card">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg/220px-Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg" decoding="async" width="220" height="134" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg/330px-Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0f/Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg/440px-Intel_WM3945ABG_MOW2_and_its_connector_20070216.jpg 2x" data-file-width="1191" data-file-height="727" /></a><figcaption>A <a href="/wiki/WLAN" class="mw-redirect" title="WLAN">WLAN</a> PCI Express Mini Card and its connector</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:MiniPCI_and_MiniPCI_Express_cards.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d8/MiniPCI_and_MiniPCI_Express_cards.jpg/220px-MiniPCI_and_MiniPCI_Express_cards.jpg" decoding="async" width="220" height="168" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d8/MiniPCI_and_MiniPCI_Express_cards.jpg/330px-MiniPCI_and_MiniPCI_Express_cards.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d8/MiniPCI_and_MiniPCI_Express_cards.jpg/440px-MiniPCI_and_MiniPCI_Express_cards.jpg 2x" data-file-width="969" data-file-height="738" /></a><figcaption>MiniPCI and MiniPCI Express cards in comparison</figcaption></figure> PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the <a href="/wiki/Mini_PCI" class="mw-redirect" title="Mini PCI">Mini PCI</a> form factor. It is developed by the <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a>. The host device supports both PCI Express and <a href="/wiki/USB" title="USB">USB</a> 2.0 connectivity, and each card may use either standard. Most laptop computers built after 2005 use PCI Express for expansion cards; however, as of 2015<a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&action=edit">[update]</a>, many vendors are moving toward using the newer <a href="/wiki/M.2" title="M.2">M.2</a> form factor for this purpose.<a href="#cite_note-41">[39]</a> Due to different dimensions, PCI Express Mini Cards are not physically compatible with standard full-size PCI Express slots; however, passive adapters exist that let them be used in full-size slots.<a href="#cite_note-DmwJz-42">[40]</a> <div class="mw-heading mw-heading4"><h4 id="Physical_dimensions">Physical dimensions</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=14" title="Edit section: Physical dimensions">edit</a>]</div> Dimensions of PCI Express Mini Cards are 30 mm × 50.95 mm (width × length) for a Full Mini Card. There is a 52-pin <a href="/wiki/Edge_connector" title="Edge connector">edge connector</a>, consisting of two staggered rows on a 0.8 mm pitch. Each row has eight contacts, a gap equivalent to four contacts, then a further 18 contacts. <a href="/wiki/Printed_circuit_board" title="Printed circuit board">Boards</a> have a thickness of 1.0 mm, excluding the components. A "Half Mini Card" (sometimes abbreviated as HMC) is also specified, having approximately half the physical length of 26.8 mm. There are also half size mini PCIe cards that are 30 x 31.90 mm which is about half the length of a full size mini PCIe card.<a href="#cite_note-43">[41]</a><a href="#cite_note-44">[42]</a> <div class="mw-heading mw-heading4"><h4 id="Electrical_interface">Electrical interface</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=15" title="Edit section: Electrical interface">edit</a>]</div> PCI Express Mini Card edge connectors provide multiple connections and buses: <ul><li>PCI Express x1 (with SMBus)</li> <li>USB 2.0</li> <li>Wires to diagnostics LEDs for wireless network (i.e., <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a>) status on computer's chassis</li> <li><a href="/wiki/Subscriber_Identity_Module" class="mw-redirect" title="Subscriber Identity Module">SIM</a> card for <a href="/wiki/GSM" title="GSM">GSM</a> and <a href="/wiki/WCDMA" class="mw-redirect" title="WCDMA">WCDMA</a> applications (UIM signals on spec.)</li> <li>Future extension for another PCIe lane</li> <li>1.5 V and 3.3 V power</li></ul> <div class="mw-heading mw-heading4"><h4 id="Mini-SATA_(mSATA)_variant">Mini-SATA (mSATA) variant</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=16" title="Edit section: Mini-SATA (mSATA) variant">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_525_mSATA_SSD.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Intel_525_mSATA_SSD.jpg/170px-Intel_525_mSATA_SSD.jpg" decoding="async" width="170" height="267" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Intel_525_mSATA_SSD.jpg/255px-Intel_525_mSATA_SSD.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Intel_525_mSATA_SSD.jpg/340px-Intel_525_mSATA_SSD.jpg 2x" data-file-width="1948" data-file-height="3064" /></a><figcaption>An Intel mSATA SSD</figcaption></figure> Despite sharing the Mini PCI Express form factor, an <a href="/wiki/MSATA" class="mw-redirect" title="MSATA">mSATA</a> slot is not necessarily electrically compatible with Mini PCI Express. For this reason, only certain notebooks are compatible with mSATA drives. Most compatible systems are based on Intel's Sandy Bridge processor architecture, using the Huron River platform. Notebooks such as Lenovo's ThinkPad T, W and X series, released in March–April 2011, have support for an mSATA SSD card in their <a href="/wiki/Wireless_WAN" title="Wireless WAN">WWAN</a> card slot. The ThinkPad Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560/Y570/Y580 also support mSATA.<a href="#cite_note-5xxpo-45">[43]</a> On the contrary, the L-series among others can only support M.2 cards using the PCIe standard in the WWAN slot. Some notebooks (notably the <a href="/wiki/Asus_Eee_PC" title="Asus Eee PC">Asus Eee PC</a>, the <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> <a href="/wiki/MacBook_Air" title="MacBook Air">MacBook Air</a>, and the Dell mini9 and mini10) use a variant of the PCI Express Mini Card as an <a href="/wiki/Solid-state_drive" title="Solid-state drive">SSD</a>. This variant uses the reserved and several non-reserved pins to implement SATA and IDE interface passthrough, keeping only USB, ground lines, and sometimes the core PCIe x1 bus intact.<a href="#cite_note-EeePC-46">[44]</a> This makes the "miniPCIe" flash and solid-state drives sold for netbooks largely incompatible with true PCI Express Mini implementations. Also, the typical Asus miniPCIe SSD is 71 mm long, causing the Dell 51 mm model to often be (incorrectly) referred to as half length. A true 51 mm Mini PCIe SSD was announced in 2009, with two stacked PCB layers that allow for higher storage capacity. The announced design preserves the PCIe interface, making it compatible with the standard mini PCIe slot. No working product has yet been developed. Intel has numerous desktop boards with the PCIe x1 Mini-Card slot that typically do not support mSATA SSD. A list of desktop boards that natively support mSATA in the PCIe x1 Mini-Card slot (typically multiplexed with a SATA port) is provided on the Intel Support site.<a href="#cite_note-xpI66-47">[45]</a> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_M.2">PCI Express M.2</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=17" title="Edit section: PCI Express M.2">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/M.2" title="M.2">M.2</a></div> M.2 replaces the mSATA standard and Mini PCIe.<a href="#cite_note-oL68r-48">[46]</a> Computer bus interfaces provided through the M.2 connector are PCI Express 3.0 (up to four lanes), Serial ATA 3.0, and USB 3.0 (a single logical port for each of the latter two). It is up to the manufacturer of the M.2 host or device to choose which interfaces to support, depending on the desired level of host support and device type. <div class="mw-heading mw-heading3"><h3 id="PCI_Express_External_Cabling">PCI Express External Cabling</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=18" title="Edit section: PCI Express External Cabling">edit</a>]</div> PCI Express External Cabling (also known as External PCI Express, Cabled PCI Express, or ePCIe) specifications were released by the <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a> in February 2007.<a href="#cite_note-pcie_cabling1.0-49">[47]</a><a href="#cite_note-ZTXPi-50">[48]</a> Standard cables and connectors have been defined for x1, x4, x8, and x16 link widths, with a transfer rate of 250 MB/s per lane. The PCI-SIG also expects the norm to evolve to reach 500 MB/s, as in PCI Express 2.0. An example of the uses of Cabled PCI Express is a metal enclosure, containing a number of PCIe slots and PCIe-to-ePCIe adapter circuitry. This device would not be possible had it not been for the ePCIe specification. <div class="mw-heading mw-heading4"><h4 id="PCI_Express_OCuLink">PCI Express OCuLink</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=19" title="Edit section: PCI Express OCuLink">edit</a>]</div> OCuLink (standing for "optical-copper link", since Cu is the <a href="/wiki/Symbol_(chemistry)" class="mw-redirect" title="Symbol (chemistry)">chemical symbol</a> for <a href="/wiki/Copper" title="Copper">copper</a>) is an extension for the "cable version of PCI Express". Version 1.0 of OCuLink, released in Oct 2015, supports up to 4 PCIe 3.0 lanes (3.9 GB/s) over copper cabling; a <a href="/wiki/Fiber_optic" class="mw-redirect" title="Fiber optic">fiber optic</a> version may appear in the future. The most recent version of OCuLink, OCuLink-2, supports up to 16 GB/s (PCIe 4.0 x8)<a href="#cite_note-OCuLink2-51">[49]</a> while the maximum bandwidth of a <a href="/wiki/USB_4" class="mw-redirect" title="USB 4">USB 4</a> cable is 10GB/s. While initially intended for use in laptops for the connection of powerful external GPU boxes, OCuLink's popularity lies primarily in its use for PCIe interconnections in servers, a more prevalent application.<a href="#cite_note-6MiK5-52">[50]</a> <div class="mw-heading mw-heading3"><h3 id="Derivative_forms">Derivative forms</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=20" title="Edit section: Derivative forms">edit</a>]</div> Numerous other form factors use, or are able to use, PCIe. These include: <ul><li>Low-height card</li> <li><a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a>: Successor to the <a href="/wiki/PC_Card" title="PC Card">PC Card</a> form factor (with x1 PCIe and USB 2.0; hot-pluggable)</li> <li>PCI Express ExpressModule: A hot-pluggable modular form factor defined for servers and workstations</li> <li><a href="/wiki/XQD_card" title="XQD card">XQD card</a>: A PCI Express-based flash card standard by the <a href="/wiki/CompactFlash_Association" class="mw-redirect" title="CompactFlash Association">CompactFlash Association</a> with x2 PCIe</li> <li><a href="/wiki/CFexpress" title="CFexpress">CFexpress</a> card: A PCI Express-based flash card by the CompactFlash Association in three form factors supporting 1 to 4 PCIe lanes</li> <li>SD card: The <a href="/wiki/SD_card#SD_Express" title="SD card">SD Express</a> bus, introduced in version 7.0 of the SD specification uses a x1 PCIe link</li> <li><a href="/w/index.php?title=Switched_Mezzanine_Card&action=edit&redlink=1" class="new" title="Switched Mezzanine Card (page does not exist)">XMC</a>: Similar to the <a href="/w/index.php?title=Common_Mezzanine_Card&action=edit&redlink=1" class="new" title="Common Mezzanine Card (page does not exist)">CMC</a>/<a href="/wiki/PCI_Mezzanine_Card" title="PCI Mezzanine Card">PMC</a> form factor (VITA 42.3)</li> <li><a href="/wiki/Advanced_Telecommunications_Computing_Architecture" title="Advanced Telecommunications Computing Architecture">AdvancedTCA</a>: A complement to <a href="/wiki/CompactPCI" title="CompactPCI">CompactPCI</a> for larger applications; supports serial based backplane topologies</li> <li><a href="/wiki/Advanced_Mezzanine_Card" title="Advanced Mezzanine Card">AMC</a>: A complement to the <a href="/wiki/Advanced_Telecommunications_Computing_Architecture" title="Advanced Telecommunications Computing Architecture">AdvancedTCA</a> specification; supports processor and I/O modules on ATCA boards (x1, x2, x4 or x8 PCIe).</li> <li><a href="/wiki/FeaturePak" title="FeaturePak">FeaturePak</a>: A tiny expansion card format (43 mm × 65 mm) for embedded and small-form-factor applications, which implements two x1 PCIe links on a high-density connector along with USB, I2C, and up to 100 points of I/O</li> <li><a href="/w/index.php?title=Universal_IO&action=edit&redlink=1" class="new" title="Universal IO (page does not exist)">Universal IO</a>: A variant from <a href="/wiki/Supermicro" title="Supermicro">Super Micro Computer</a> Inc designed for use in low-profile rack-mounted chassis.<a href="#cite_note-tNP5L-53">[51]</a> It has the connector bracket reversed so it cannot fit in a normal PCI Express socket, but it is pin-compatible and may be inserted if the bracket is removed.</li> <li><a href="/wiki/M.2" title="M.2">M.2</a> (formerly known as NGFF)</li> <li><a href="/wiki/M-PCIe" class="mw-redirect" title="M-PCIe">M-PCIe</a> brings PCIe 3.0 to mobile devices (such as tablets and smartphones), over the <a href="/wiki/M-PHY" title="M-PHY">M-PHY</a> physical layer.<a href="#cite_note-osiit-54">[52]</a><a href="#cite_note-PoRghEr-55">[53]</a></li> <li><a href="/wiki/U.2" title="U.2">U.2</a> (formerly known as SFF-8639)</li> <li><a href="/wiki/SlimSAS" class="mw-redirect" title="SlimSAS">SlimSAS</a></li></ul> The PCIe slot connector can also carry protocols other than PCIe. Some <a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">9xx series Intel chipsets</a> support <a href="/wiki/Serial_Digital_Video_Out" title="Serial Digital Video Out">Serial Digital Video Out</a>, a proprietary technology that uses a slot to transmit video signals from the host CPU's <a href="/wiki/Intel_GMA" title="Intel GMA">integrated graphics</a> instead of PCIe, using a supported add-in. The PCIe transaction-layer protocol can also be used over some other interconnects, which are not electrically PCIe: <ul><li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a>: A royalty-free interconnect standard by Intel that combines <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a> and PCIe protocols in a form factor compatible with <a href="/wiki/Mini_DisplayPort" title="Mini DisplayPort">Mini DisplayPort</a>. Thunderbolt 3.0 also combines USB 3.1 and uses the <a href="/wiki/USB-C" title="USB-C">USB-C</a> form factor as opposed to Mini DisplayPort.</li> <li><a href="/wiki/USB4" title="USB4">USB4</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="History_and_revisions">History and revisions</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=21" title="Edit section: History and revisions">edit</a>]</div> While in early development, PCIe was initially referred to as HSI (for High Speed Interconnect), and underwent a name change to 3GIO (for 3rd Generation I/O) before finally settling on its <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a> name PCI Express. A technical working group named the Arapaho Work Group (AWG) drew up the standard. For initial drafts, the AWG consisted only of Intel engineers; subsequently, the AWG expanded to include industry partners. Since, PCIe has undergone several large and smaller revisions, improving on performance and other features. <div class="mw-heading mw-heading3"><h3 id="Comparison_table">Comparison table</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=22" title="Edit section: Comparison table">edit</a>]</div> <table class="wikitable" style="text-align:right"> <caption>PCI Express link performance<a href="#cite_note-faq4-56">[54]</a><a href="#cite_note-faq3-57">[55]</a> </caption> <tbody><tr style="line-height:120%"> <th scope="col" rowspan="2">Version </th> <th scope="col" rowspan="2">intro- duced </th> <th scope="col" rowspan="2" colspan="2">Line code </th> <th scope="col" rowspan="2">Transfer rate<a href="#cite_note-both-directions-58">[i]</a><a href="#cite_note-transfer-rate-59">[ii]</a> (per lane) </th> <th scope="col" colspan="5">Throughput<a href="#cite_note-both-directions-58">[i]</a><a href="#cite_note-throughput-60">[iii]</a> </th></tr> <tr> <th scope="col">x1 </th> <th scope="col">x2 </th> <th scope="col">x4 </th> <th scope="col">x8 </th> <th scope="col">x16 </th></tr> <tr> <th scope="row">1.0 </th> <td>2003 </td> <td rowspan="5"><a href="/wiki/Non-return-to-zero" title="Non-return-to-zero">NRZ</a> </td> <td rowspan="2"><a href="/wiki/8b/10b" class="mw-redirect" title="8b/10b">8b/10b</a> </td> <td>2.5 <a href="/wiki/GT/s" class="mw-redirect" title="GT/s">GT/s</a> </td> <td>0.250 <a href="/wiki/GB/s" class="mw-redirect" title="GB/s">GB/s</a> </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">0.500 GB/s </td> <td>1.000 GB/s </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">2.000 GB/s </td> <td>4.000 GB/s </td></tr> <tr> <th scope="row">2.0 </th> <td>2007 </td> <td>5.0 GT/s </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">0.500 GB/s </td> <td>1.000 GB/s </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">2.000 GB/s </td> <td>4.000 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">8.000 GB/s </td></tr> <tr> <th scope="row">3.0 </th> <td>2010 </td> <td rowspan="3"><a href="/wiki/128b/130b" class="mw-redirect" title="128b/130b">128b/130b</a> </td> <td>8.0 GT/s </td> <td>0.985 GB/s </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">1.969 GB/s </td> <td>3.938 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">07.877 GB/s </td> <td>15.754 GB/s </td></tr> <tr> <th scope="row">4.0 </th> <td>2017 </td> <td>16.0 GT/s </td> <td style="background-color: #FFF; color:black; text-align: right;" class="table-cast">1.969 GB/s </td> <td>3.938 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">07.877 GB/s </td> <td>15.754 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">031.508 GB/s </td></tr> <tr> <th scope="row">5.0 </th> <td>2019 </td> <td>32.0 GT/s </td> <td>3.938 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">07.877 GB/s </td> <td>15.754 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">31.508 GB/s </td> <td>63.015 GB/s </td></tr> <tr> <th scope="row">6.0 </th> <td>2022 </td> <td rowspan="2"><a href="/wiki/PAM-4" class="mw-redirect" title="PAM-4">PAM-4</a> <a href="/wiki/Forward_error_correction" class="mw-redirect" title="Forward error correction">FEC</a> </td> <td rowspan="2">1b/1b 242B/256B <a href="/wiki/Flit_(computer_networking)" title="Flit (computer networking)">FLIT</a> </td> <td>64.0 GT/s 32.0 G<a href="/wiki/Baud" title="Baud">Bd</a> </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">7.563 GB/s </td> <td>15.125 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">30.250 GB/s </td> <td>60.500 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">121.000 GB/s </td></tr> <tr> <th scope="row">7.0 </th> <td>2025 (planned) </td> <td>128.0 GT/s 64.0 GBd </td> <td>15.125 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">30.250 GB/s </td> <td>60.500 GB/s </td> <td style="background: #EEE; color:black; vertical-align: middle; text-align: right;" class="table-cast">121.000 GB/s </td> <td>242.000 GB/s </td></tr></tbody></table> <dl><dt>Notes</dt></dl> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-both-directions-58">^ <a href="#cite_ref-both-directions_58-0">a</a> <a href="#cite_ref-both-directions_58-1">b</a> In each direction (each lane is a dual simplex channel). </li> <li id="cite_note-transfer-rate-59"><a href="#cite_ref-transfer-rate_59-0">^</a> Transfer rate refers to the encoded serial bit rate; 2.5 GT/s means 2.5 Gbit/s serial data rate. </li> <li id="cite_note-throughput-60"><a href="#cite_ref-throughput_60-0">^</a> Throughput indicates the usable bandwidth (i.e. only including the payload, not the 8b/10b, 128b/130b, or 242B/256B encoding overhead). The PCIe 1.0 transfer rate of 2.5 GT/s per lane means a 2.5 Gbit/s serial bit rate; after applying a 8b/10b encoding, this corresponds to a useful throughput of 2.0 Gbit/s = 250 MB/s. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_1.0a">PCI Express 1.0a</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=23" title="Edit section: PCI Express 1.0a">edit</a>]</div> In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250 MB/s and a <a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">transfer rate</a> of 2.5 gigatransfers per second (GT/s). Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput;<a href="#cite_note-HroAC-61">[56]</a> PCIe 1.x uses an <a href="/wiki/8b/10b_encoding" title="8b/10b encoding">8b/10b encoding</a> scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth.<a href="#cite_note-tfQxK-62">[57]</a> So in the PCIe terminology, transfer rate refers to the encoded bit rate: 2.5 GT/s is 2.5 Gbit/s on the encoded serial link. This corresponds to 2.0 Gbit/s of pre-coded data or 250 MB/s, which is referred to as throughput in PCIe. <div class="mw-heading mw-heading4"><h4 id="PCI_Express_1.1">PCI Express 1.1</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=24" title="Edit section: PCI Express 1.1">edit</a>]</div> In 2005, PCI-SIG<a href="#cite_note-n9qGs-63">[58]</a> introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate. <div class="mw-heading mw-heading3"><h3 id="PCI_Express_2.0">PCI Express 2.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=25" title="Edit section: PCI Express 2.0">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Rosewill-USB3-PCI-Express-Card.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/19/Rosewill-USB3-PCI-Express-Card.jpg/220px-Rosewill-USB3-PCI-Express-Card.jpg" decoding="async" width="220" height="148" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/19/Rosewill-USB3-PCI-Express-Card.jpg/330px-Rosewill-USB3-PCI-Express-Card.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/19/Rosewill-USB3-PCI-Express-Card.jpg/440px-Rosewill-USB3-PCI-Express-Card.jpg 2x" data-file-width="2580" data-file-height="1740" /></a><figcaption>A PCI Express 2.0 x1 expansion card that provides USB 3.0 connectivity<a href="#cite_note-64">[b]</a></figcaption></figure> <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a> announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.<a href="#cite_note-PCIExpressPressRelease-65">[59]</a> The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. Consequently, a 16-lane PCIe connector (x16) can support an aggregate throughput of up to 8 GB/s. PCIe 2.0 motherboard slots are fully <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 work, with the other being v1.1 or v1.0a. The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.<a href="#cite_note-UaYlc-66">[60]</a> <a href="/wiki/Intel_Corporation" class="mw-redirect" title="Intel Corporation">Intel</a>'s first PCIe 2.0 capable chipset was the <a href="/wiki/G35_(chipset)" class="mw-redirect" title="G35 (chipset)">X38</a> and boards began to ship from various vendors (<a href="/wiki/Universal_abit" class="mw-redirect" title="Universal abit">Abit</a>, <a href="/wiki/Asus" title="Asus">Asus</a>, <a href="/wiki/Gigabyte_Technology" title="Gigabyte Technology">Gigabyte</a>) as of 21 October 2007.<a href="#cite_note-wHHTf-67">[61]</a> AMD started supporting PCIe 2.0 with its <a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">AMD 700 chipset series</a> and nVidia started with the <a href="/wiki/NForce_700" title="NForce 700">MCP72</a>.<a href="#cite_note-gL2GQ-68">[62]</a> All of Intel's prior chipsets, including the <a href="/wiki/Intel_P35" title="Intel P35">Intel P35</a> chipset, supported PCIe 1.1 or 1.0a.<a href="#cite_note-mUQKD-69">[63]</a> Like 1.x, PCIe 2.0 uses an <a href="/wiki/8b/10b_encoding" title="8b/10b encoding">8b/10b encoding</a> scheme, therefore delivering, per-lane, an effective 4 Gbit/s max. transfer rate from its 5 GT/s raw data rate. <div class="mw-heading mw-heading4"><h4 id="PCI_Express_2.1">PCI Express 2.1</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=26" title="Edit section: PCI Express 2.1">edit</a>]</div> PCI Express 2.1 (with its specification dated 4 March 2009) supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. The increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1. <div class="mw-heading mw-heading3"><h3 id="PCI_Express_3.0">PCI Express 3.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=27" title="Edit section: PCI Express 3.0">edit</a>]</div> PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 <a href="/wiki/Gigatransfer" class="mw-redirect" title="Gigatransfer">gigatransfers</a> per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010.<a href="#cite_note-cVjNG-70">[64]</a> New features for the PCI Express 3.0 specification included a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, <a href="/wiki/Phase-locked_loop" title="Phase-locked loop">PLL</a> improvements, clock data recovery, and channel enhancements of currently supported topologies.<a href="#cite_note-extrmetech-71">[65]</a> Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second could be manufactured in mainstream silicon process technology, and deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) with the PCI Express protocol stack. PCI Express 3.0 upgraded the <a href="/wiki/Encoding_scheme" class="mw-redirect" title="Encoding scheme">encoding scheme</a> to 128b/130b from the previous <a href="/wiki/8b/10b_encoding" title="8b/10b encoding">8b/10b encoding</a>, reducing the bandwidth overhead from 20% of PCI Express 2.0 to approximately 1.54% (= 2/130). PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.<a href="#cite_note-faq3-57">[55]</a> On 18 November 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.<a href="#cite_note-ajVA3-72">[66]</a> <div class="mw-heading mw-heading4"><h4 id="PCI_Express_3.1">PCI Express 3.1</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=28" title="Edit section: PCI Express 3.1">edit</a>]</div> In September 2013, PCI Express 3.1 specification was announced for release in late 2013 or early 2014, consolidating various improvements to the published PCI Express 3.0 specification in three areas: power management, performance and functionality.<a href="#cite_note-PoRghEr-55">[53]</a><a href="#cite_note-5lvIH-73">[67]</a> It was released in November 2014.<a href="#cite_note-9EIkz-74">[68]</a> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_4.0">PCI Express 4.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=29" title="Edit section: PCI Express 4.0">edit</a>]</div> On 29 November 2011, PCI-SIG preliminarily announced PCI Express 4.0,<a href="#cite_note-W466M-75">[69]</a> providing a 16 GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0 to 31.5 GB/s in each direction for a 16-lane configuration, while maintaining backward and <a href="/wiki/Forward_compatibility" title="Forward compatibility">forward compatibility</a> in both software support and used mechanical interface.<a href="#cite_note-QNZsy-76">[70]</a> PCI Express 4.0 specs also bring OCuLink-2, an alternative to <a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a>. OCuLink version 2 has up to 16 GT/s (16 GB/s total for x8 lanes),<a href="#cite_note-OCuLink2-51">[49]</a> while the maximum bandwidth of a Thunderbolt 3 link is 5 GB/s. In June 2016 Cadence, PLDA and Synopsys demonstrated PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG’s annual developer’s conference.<a href="#cite_note-EE_4+5-77">[71]</a> <a href="/wiki/Mellanox_Technologies" title="Mellanox Technologies">Mellanox Technologies</a> announced the first 100 Gbit/s network adapter with PCIe 4.0 on 15 June 2016,<a href="#cite_note-FZ4hQ-78">[72]</a> and the first 200 Gbit/s network adapter with PCIe 4.0 on 10 November 2016.<a href="#cite_note-zovf4-79">[73]</a> In August 2016, <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a> presented a test setup with FPGA clocking a lane to PCIe 4.0 speeds at the <a href="/wiki/Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a>. Their IP has been licensed to several firms planning to present their chips and products at the end of 2016.<a href="#cite_note-heise_idf_2016-80">[74]</a> On the IEEE Hot Chips Symposium in August 2016 <a href="/wiki/IBM" title="IBM">IBM</a> announced the first CPU with PCIe 4.0 support, <a href="/wiki/POWER9" title="POWER9">POWER9</a>.<a href="#cite_note-HC28-IBM-Power9-81">[75]</a><a href="#cite_note-IEEE-Power9-82">[76]</a> PCI-SIG officially announced the release of the final PCI Express 4.0 specification on 8 June 2017.<a href="#cite_note-TR_pcie4-83">[77]</a> The spec includes improvements in flexibility, scalability, and lower-power. On 5 December 2017 IBM announced the first system with PCIe 4.0 slots, Power AC922.<a href="#cite_note-2HOSh-84">[78]</a><a href="#cite_note-IBM-ZG17-0147-85">[79]</a> NETINT Technologies introduced the first <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> SSD based on PCIe 4.0 on 17 July 2018, ahead of Flash Memory Summit 2018<a href="#cite_note-ChNhD-86">[80]</a> <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> announced on 9 January 2019 its upcoming <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a>-based processors and X570 chipset would support PCIe 4.0.<a href="#cite_note-Akskd-87">[81]</a> AMD had hoped to enable partial support for older chipsets, but instability caused by motherboard traces not conforming to PCIe 4.0 specifications made that impossible.<a href="#cite_note-KDBMK-88">[82]</a><a href="#cite_note-CAY71-89">[83]</a> Intel released their first mobile CPUs with PCI Express 4.0 support in mid-2020, as a part of the <a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake</a> microarchitecture.<a href="#cite_note-C02lC-90">[84]</a> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_5.0">PCI Express 5.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=30" title="Edit section: PCI Express 5.0">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png/220px-Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png" decoding="async" width="220" height="252" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png/330px-Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png/440px-Detailaufnahme_des_ASRock_TRX50_WS_20240406_HOF1835-HDR_RAW-Export_000185.png 2x" data-file-width="6047" data-file-height="6914" /></a><figcaption>Three PCIe 5.0 x16 and two PCIe 4.0 x16 slots on a 2023 workstation mainboard</figcaption></figure> In June 2017, PCI-SIG announced the PCI Express 5.0 preliminary specification.<a href="#cite_note-TR_pcie4-83">[77]</a> Bandwidth was expected to increase to 32 GT/s, yielding 63 GB/s in each direction in a 16-lane configuration. The draft spec was expected to be standardized in 2019.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] Initially, 25.0 GT/s was also considered for technical feasibility. On 7 June 2017 at PCI-SIG DevCon, Synopsys recorded the first demonstration of PCI Express 5.0 at 32 GT/s.<a href="#cite_note-Syn50-91">[85]</a> On 31 May 2018, PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day.<a href="#cite_note-n6z9y-92">[86]</a><a href="#cite_note-9OVm8-93">[87]</a> On 10 December 2018, the PCI SIG released version 0.9 of the PCIe 5.0 specification to its members,<a href="#cite_note-PCIe5r09-94">[88]</a> and on 17 January 2019, PCI SIG announced the version 0.9 had been ratified, with version 1.0 targeted for release in the first quarter of 2019.<a href="#cite_note-ETVqe-95">[89]</a> On 29 May 2019, PCI-SIG officially announced the release of the final PCI Express 5.0 specification.<a href="#cite_note-MW69U-96">[90]</a> On 20 November 2019, <a href="/w/index.php?title=Jiangsu_Huacun&action=edit&redlink=1" class="new" title="Jiangsu Huacun (page does not exist)">Jiangsu Huacun</a> presented the first PCIe 5.0 Controller HC9001 in a 12 nm manufacturing process.<a href="#cite_note-yk5Nd-97">[91]</a> Production started in 2020. On 17 August 2020, IBM announced the <a href="/wiki/Power10" title="Power10">Power10</a> processor with PCIe 5.0 and up to 32 lanes per single-chip module (SCM) and up to 64 lanes per double-chip module (DCM).<a href="#cite_note-98">[92]</a> On 9 September 2021, IBM announced the Power E1080 Enterprise server with planned availability date 17 September.<a href="#cite_note-IBM-ENUSZG21-0059-99">[93]</a> It can have up to 16 Power10 SCMs with maximum of 32 slots per system which can act as PCIe 5.0 x8 or PCIe 4.0 x16.<a href="#cite_note-IBM-REDP-5649-00-100">[94]</a> Alternatively they can be used as PCIe 5.0 x16 slots for optional optical CXP converter adapters connecting to external PCIe expansion drawers. On 27 October 2021, Intel announced the 12th Gen Intel Core CPU family, the world's first consumer x86-64 processors with PCIe 5.0 (up to 16 lanes) connectivity.<a href="#cite_note-101">[95]</a> On 22 March 2022, Nvidia announced Nvidia Hopper GH100 GPU, the world's first PCIe 5.0 GPU.<a href="#cite_note-102">[96]</a> On 23 May 2022, AMD announced its Zen 4 architecture with support for up to 24 lanes of PCIe 5.0 connectivity on consumer platforms and 128 lanes on server platforms.<a href="#cite_note-103">[97]</a><a href="#cite_note-104">[98]</a> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_6.0">PCI Express 6.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=31" title="Edit section: PCI Express 6.0">edit</a>]</div> On 18 June 2019, PCI-SIG announced the development of PCI Express 6.0 specification. Bandwidth is expected to increase to 64 GT/s, yielding 128 GB/s in each direction in a 16-lane configuration, with a target release date of 2021.<a href="#cite_note-businesswire.com-105">[99]</a> The new standard uses 4-level <a href="/wiki/Pulse-amplitude_modulation" title="Pulse-amplitude modulation">pulse-amplitude modulation</a> (PAM-4) with a low-latency <a href="/wiki/Forward_error_correction" class="mw-redirect" title="Forward error correction">forward error correction</a> (FEC) in place of <a href="/wiki/Non-return-to-zero" title="Non-return-to-zero">non-return-to-zero</a> (NRZ) modulation.<a href="#cite_note-O5gOe-106">[100]</a> Unlike previous PCI Express versions, forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer. With 64 GT/s data transfer rate (raw bit rate), up to 121 GB/s in each direction is possible in x16 configuration.<a href="#cite_note-businesswire.com-105">[99]</a> On 24 February 2020, the PCI Express 6.0 revision 0.5 specification (a "first draft" with all architectural aspects and requirements defined) was released.<a href="#cite_note-puGmx-107">[101]</a> On 5 November 2020, the PCI Express 6.0 revision 0.7 specification (a "complete draft" with electrical specifications validated via test chips) was released.<a href="#cite_note-ltCSi-108">[102]</a> On 6 October 2021, the PCI Express 6.0 revision 0.9 specification (a "final draft") was released.<a href="#cite_note-60r9-109">[103]</a> On 11 January 2022, PCI-SIG officially announced the release of the final PCI Express 6.0 specification.<a href="#cite_note-110">[104]</a> On 18 March 2024, Nvidia announced Nvidia Blackwell GB100 GPU, the world's first PCIe 6.0 GPU.<a href="#cite_note-111">[105]</a> <a href="/wiki/PAM-4" class="mw-redirect" title="PAM-4">PAM-4</a> coding results in a vastly higher <a href="/wiki/Bit_error_rate" title="Bit error rate">bit error rate</a> (BER) of 10−6 (vs. 10−12 previously), so in place of 128b/130b encoding, a 3-way interlaced <a href="/wiki/Forward_error_correction" class="mw-redirect" title="Forward error correction">forward error correction</a> (FEC) is used in addition to <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">cyclic redundancy check</a> (CRC). A fixed 256 byte <a href="/wiki/Flit_(computer_networking)" title="Flit (computer networking)">Flow Control Unit</a> (FLIT) block carries 242 bytes of data, which includes variable-sized transaction level packets (TLP) and data link layer payload (DLLP); remaining 14 bytes are reserved for 8-byte CRC and 6-byte FEC.<a href="#cite_note-pcie6_evolution_blog-112">[106]</a><a href="#cite_note-PCIe6_fut-113">[107]</a> 3-way <a href="/wiki/Gray_code" title="Gray code">Gray code</a> is used in PAM-4/FLIT mode to reduce error rate; the interface does not switch to NRZ and 128/130b encoding even when retraining to lower data rates.<a href="#cite_note-cadence_pice6-114">[108]</a><a href="#cite_note-pcie6_webinar-115">[109]</a> <div class="mw-heading mw-heading3"><h3 id="PCI_Express_7.0">PCI Express 7.0</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=32" title="Edit section: PCI Express 7.0">edit</a>]</div> On 21 June 2022, PCI-SIG announced the development of PCI Express 7.0 specification.<a href="#cite_note-116">[110]</a> It will deliver 128 GT/s raw bit rate and up to 242 GB/s per direction in x16 configuration, using the same <a href="/wiki/Pulse-amplitude_modulation" title="Pulse-amplitude modulation">PAM4</a> signaling as version 6.0. Doubling of the data rate will be achieved by fine-tuning channel parameters to decrease signal losses and improve power efficiency, but signal integrity is expected to be a challenge. The specification is expected to be finalized in 2025. On 2 April 2024, PCI-SIG announced the release of PCIe 7.0 specification version 0.5; PCI Express 7.0 remains on track for release in 2025.<a href="#cite_note-PCIe70v05-117">[111]</a> <div class="mw-heading mw-heading2"><h2 id="Extensions_and_future_directions">Extensions and future directions</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=33" title="Edit section: Extensions and future directions">edit</a>]</div> Some vendors offer PCIe over fiber products,<a href="#cite_note-PCIeFiber-118">[112]</a><a href="#cite_note-adnacoPCIe-119">[113]</a><a href="#cite_note-g6np3-120">[114]</a> with active optical cables (AOC) for PCIe switching at increased distance in PCIe expansion drawers,<a href="#cite_note-IBM-REDP-5137-00-121">[115]</a><a href="#cite_note-IBM-REDP-5649-00-100">[94]</a> or in specific cases where transparent PCIe bridging is preferable to using a more mainstream standard (such as <a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a> or <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a>) that may require additional software to support it. <a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a> was co-developed by <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> as a general-purpose high speed interface combining a logical PCIe link with <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a> and was originally intended as an all-fiber interface, but due to early difficulties in creating a consumer-friendly fiber interconnect, nearly all implementations are copper systems. A notable exception, the <a href="/wiki/Sony_Vaio_Z_series" title="Sony Vaio Z series">Sony VAIO Z</a> VPC-Z2, uses a nonstandard USB port with an optical component to connect to an outboard PCIe display adapter. Apple has been the primary driver of Thunderbolt adoption through 2011, though several other vendors<a href="#cite_note-kZCuH-122">[116]</a> have announced new products and systems featuring Thunderbolt. Thunderbolt 3 forms the basis of the <a href="/wiki/USB4" title="USB4">USB4</a> standard. Mobile PCIe specification (abbreviated to M-PCIe) allows PCI Express architecture to operate over the <a href="/wiki/MIPI_Alliance" title="MIPI Alliance">MIPI Alliance</a>'s <a href="/wiki/M-PHY" title="M-PHY">M-PHY</a> physical layer technology. Building on top of already existing widespread adoption of M-PHY and its low-power design, Mobile PCIe lets mobile devices use PCI Express.<a href="#cite_note-RKmF2-123">[117]</a> <div class="mw-heading mw-heading3"><h3 id="Draft_process">Draft process</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=34" title="Edit section: Draft process">edit</a>]</div> There are 5 primary releases/checkpoints in a PCI-SIG specification:<a href="#cite_note-yT5P8-124">[118]</a> <ul><li>Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals.</li> <li>Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft.</li> <li>Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon.</li> <li>Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.</li> <li>1.0 (Final release): this is the final and definitive specification, and any changes or enhancements are through Errata documentation and Engineering Change Notices (ECNs) respectively.</li></ul> Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources. <div class="mw-heading mw-heading2"><h2 id="Hardware_protocol_summary">Hardware protocol summary</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=35" title="Edit section: Hardware protocol summary">edit</a>]</div> The PCIe link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connections known as lanes. This is in sharp contrast to the earlier PCI connection, which is a bus-based system where all the devices share the same bidirectional, 32-bit or 64-bit parallel bus. PCI Express is a <a href="/wiki/Layered_protocol" class="mw-redirect" title="Layered protocol">layered protocol</a>, consisting of a <a href="#Transaction_layer">transaction layer</a>, a <a href="#Data_link_layer">data link layer</a>, and a <a href="#Physical_layer">physical layer</a>. The Data Link Layer is subdivided to include a <a href="/wiki/Media_access_control" class="mw-redirect" title="Media access control">media access control</a> (MAC) sublayer. The Physical Layer is subdivided into logical and electrical sublayers. The Physical logical-sublayer contains a physical coding sublayer (PCS). The terms are borrowed from the <a href="/wiki/IEEE_802" title="IEEE 802">IEEE 802</a> networking protocol model. <div class="mw-heading mw-heading3"><h3 id="Physical_layer">Physical layer</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=36" title="Edit section: Physical layer">edit</a>]</div> <table class="wikitable floatright" style="margin-left: 1.5em; margin-right: 0; margin-top: 0;"> <caption>Connector pins and lengths </caption> <tbody><tr> <th rowspan="2">Lanes </th> <th colspan="2">Pins </th> <th colspan="2">Length </th></tr> <tr> <th>Total </th> <th>Variable </th> <th>Total </th> <th>Variable </th></tr> <tr> <td>0x1</td> <td>2×18 = 036<a href="#cite_note-9tQ3g-125">[119]</a></td> <td>2×07 = 014</td> <td>25 mm</td> <td>07.65 mm </td></tr> <tr> <td>0x4</td> <td>2×32 = 064</td> <td>2×21 = 042</td> <td>39 mm</td> <td>21.65 mm </td></tr> <tr> <td>0x8</td> <td>2×49 = 098</td> <td>2×38 = 076</td> <td>56 mm</td> <td>38.65 mm </td></tr> <tr> <td>0x16</td> <td>2×82 = 164</td> <td>2×71 = 142</td> <td>89 mm</td> <td>71.65 mm </td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a3/PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG/220px-PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG" decoding="async" width="220" height="205" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a3/PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG/330px-PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a3/PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG/440px-PCIe_J1900_SoC_ITX_Mainboard_IMG_1820.JPG 2x" data-file-width="639" data-file-height="594" /></a><figcaption>An open-end PCI Express x1 connector lets longer cards that use more lanes be plugged while operating at x1 speeds.</figcaption></figure> The PCIe Physical Layer (PHY, PCIEPHY, PCI Express PHY, or PCIe PHY) specification is divided into two sub-layers, corresponding to electrical and logical specifications. The logical sublayer is sometimes further divided into a MAC sublayer and a PCS, although this division is not formally part of the PCIe specification. A specification published by Intel, the PHY Interface for PCI Express (PIPE),<a href="#cite_note-pipe_spec-126">[120]</a> defines the MAC/PCS functional partitioning and the interface between these two sub-layers. The PIPE specification also identifies the physical media attachment (PMA) layer, which includes the <a href="/wiki/SerDes" title="SerDes">serializer/deserializer (SerDes)</a> and other analog circuitry; however, since SerDes implementations vary greatly among <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a> vendors, PIPE does not specify an interface between the PCS and PMA. At the electrical level, each lane consists of two unidirectional <a href="/wiki/Differential_signaling" class="mw-redirect" title="Differential signaling">differential pairs</a> operating at 2.5, 5, 8, 16 or 32 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">Gbit</a>/s, depending on the negotiated capabilities. Transmit and receive are separate differential pairs, for a total of four data wires per lane. A connection between any two PCIe devices is known as a link, and is built up from a collection of one or more lanes. All devices must minimally support single-lane (x1) link. Devices may optionally support wider links composed of up to 32 lanes.<a href="#cite_note-PCIe-System-Architecture-127">[121]</a><a href="#cite_note-Intel-PCIe-128">[122]</a> This allows for very good compatibility in two ways: <ul><li>A PCIe card physically fits (and works correctly) in any slot that is at least as large as it is (e.g., a x1 sized card works in any sized slot);</li> <li>A slot of a large physical size (e.g., x16) can be wired electrically with fewer lanes (e.g., x1, x4, x8, or x12) as long as it provides the ground connections required by the larger physical slot size.</li></ul> In both cases, PCIe negotiates the highest mutually supported number of lanes. Many graphics cards, motherboards and <a href="/wiki/BIOS" title="BIOS">BIOS</a> versions are verified to support x1, x4, x8 and x16 connectivity on the same connection. The width of a PCIe connector is 8.8 mm, while the height is 11.25 mm, and the length is variable. The fixed section of the connector is 11.65 mm in length and contains two rows of 11 pins each (22 pins total), while the length of the other section is variable depending on the number of lanes. The pins are spaced at 1 mm intervals, and the thickness of the card going into the connector is 1.6 mm.<a href="#cite_note-pcie_schematics1-129">[123]</a><a href="#cite_note-pcie_schematics2-130">[124]</a> <div class="mw-heading mw-heading4"><h4 id="Data_transmission">Data transmission</h4>[<a href="/w/index.php?title=PCI_Express&action=edit&section=37" title="Edit section: Data transmission">edit</a>]</div> PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines. When the problem of IRQ sharing of pin based interrupts is taken into account and the fact that message signaled interrupts (MSI) can bypass an I/O APIC and be delivered to the CPU directly, MSI performance ends up being substantially better.<a href="#cite_note-vV4Hv-131">[125]</a> Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as data striping. While requiring significant hardware complexity to synchronize (or <a href="/wiki/Clock_skew" title="Clock skew">deskew</a>) the incoming striped data, striping can significantly reduce the latency of the nth byte on a link. While the lanes are not tightly synchronized, there is a limit to the lane to lane skew of 20/8/6 ns for 2.5/5/8 GT/s so the hardware buffers can re-align the striped data.<a href="#cite_note-iPAaS-132">[126]</a> Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link. As with other high data rate serial transmission protocols, the clock is <a href="/wiki/Self-clocking_signal" title="Self-clocking signal">embedded</a> in the signal. At the physical level, PCI Express 2.0 utilizes the <a href="/wiki/8b/10b_encoding" title="8b/10b encoding">8b/10b encoding</a> scheme<a href="#cite_note-faq3-57">[55]</a> (line code) to ensure that strings of consecutive identical digits (zeros or ones) are limited in length. This coding was used to prevent the receiver from losing track of where the bit edges are. In this coding scheme every eight (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, causing a 20% overhead in the electrical bandwidth. To improve the available bandwidth, PCI Express version 3.0 instead uses <a href="/wiki/64b/66b_encoding" title="64b/66b encoding">128b/130b</a> encoding (1.54% overhead). <a href="/wiki/Line_encoding" class="mw-redirect" title="Line encoding">Line encoding</a> limits the run length of identical-digit strings in data streams and ensures the receiver stays synchronised to the transmitter via <a href="/wiki/Clock_recovery" title="Clock recovery">clock recovery</a>. A desirable balance (and therefore <a href="/wiki/Spectral_density" title="Spectral density">spectral density</a>) of 0 and 1 bits in the data stream is achieved by <a href="/wiki/XOR" class="mw-redirect" title="XOR">XORing</a> a known <a href="/wiki/Linear-feedback_shift_register" title="Linear-feedback shift register">binary polynomial</a> as a "<a href="/wiki/Scrambler" title="Scrambler">scrambler</a>" to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware. Dual simplex in PCIe means there are two simplex channels on every PCIe lane. Simplex means communication is only possible in one direction. By having two simplex channels, two-way communication is made possible. One differential pair is used for each channel.<a href="#cite_note-133">[127]</a><a href="#cite_note-134">[128]</a><a href="#cite_note-135">[129]</a> <div class="mw-heading mw-heading3"><h3 id="Data_link_layer">Data link layer</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=38" title="Edit section: Data link layer">edit</a>]</div> The data link layer performs three vital services for the PCIe link: <ol><li>sequence the transaction layer packets (TLPs) that are generated by the transaction layer,</li> <li>ensure reliable delivery of TLPs between two endpoints via an acknowledgement protocol (<a href="/wiki/Acknowledge_character" class="mw-redirect" title="Acknowledge character">ACK</a> and <a href="/wiki/Negative-acknowledge_character" class="mw-redirect" title="Negative-acknowledge character">NAK</a> signaling) that explicitly requires replay of unacknowledged/bad TLPs,</li> <li>initialize and manage flow control credits</li></ol> On the transmit side, the data link layer generates an incrementing sequence number for each outgoing TLP. It serves as a unique identification tag for each transmitted TLP, and is inserted into the header of the outgoing TLP. A 32-bit <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">cyclic redundancy check</a> code (known in this context as Link CRC or LCRC) is also appended to the end of each outgoing TLP. On the receive side, the received TLP's LCRC and sequence number are both validated in the link layer. If either the LCRC check fails (indicating a data error), or the sequence-number is out of range (non-consecutive from the last valid received TLP), then the bad TLP, as well as any TLPs received after the bad TLP, are considered invalid and discarded. The receiver sends a negative acknowledgement message (NAK) with the sequence-number of the invalid TLP, requesting re-transmission of all TLPs forward of that sequence-number. If the received TLP passes the LCRC check and has the correct sequence number, it is treated as valid. The link receiver increments the sequence-number (which tracks the last received good TLP), and forwards the valid TLP to the receiver's transaction layer. An ACK message is sent to remote transmitter, indicating the TLP was successfully received (and by extension, all TLPs with past sequence-numbers.) If the transmitter receives a NAK message, or no acknowledgement (NAK or ACK) is received until a timeout period expires, the transmitter must retransmit all TLPs that lack a positive acknowledgement (ACK). Barring a persistent malfunction of the device or transmission medium, the link-layer presents a reliable connection to the transaction layer, since the transmission protocol ensures delivery of TLPs over an unreliable medium. In addition to sending and receiving TLPs generated by the transaction layer, the data-link layer also generates and consumes data link layer packets (DLLPs). ACK and NAK signals are communicated via DLLPs, as are some power management messages and flow control credit information (on behalf of the transaction layer). In practice, the number of in-flight, unacknowledged TLPs on the link is limited by two factors: the size of the transmitter's replay buffer (which must store a copy of all transmitted TLPs until the remote receiver ACKs them), and the flow control credits issued by the receiver to a transmitter. PCI Express requires all receivers to issue a minimum number of credits, to guarantee a link allows sending PCIConfig TLPs and message TLPs. <div class="mw-heading mw-heading3"><h3 id="Transaction_layer">Transaction layer</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=39" title="Edit section: Transaction layer">edit</a>]</div> PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response. PCI Express uses credit-based flow control. In this scheme, a device advertises an initial amount of credit for each received buffer in its transaction layer. The device at the opposite end of the link, when sending transactions to this device, counts the number of credits each TLP consumes from its account. The sending device may only transmit a TLP when doing so does not make its consumed credit count exceed its credit limit. When the receiving device finishes processing the TLP from its buffer, it signals a return of credits to the sending device, which increases the credit limit by the restored amount. The credit counters are modular counters, and the comparison of consumed credits to credit limit requires <a href="/wiki/Modular_arithmetic" title="Modular arithmetic">modular arithmetic</a>. The advantage of this scheme (compared to other methods such as wait states or handshake-based transfer protocols) is that the latency of credit return does not affect performance, provided that the credit limit is not encountered. This assumption is generally met if each device is designed with adequate buffer sizes. PCIe 1.x is often quoted to support a data rate of 250 MB/s in each direction, per lane. This figure is a calculation from the physical signaling rate (2.5 <a href="/wiki/Gigabaud" class="mw-redirect" title="Gigabaud">gigabaud</a>) divided by the encoding overhead (10 bits per byte). This means a sixteen lane (x16) PCIe card would then be theoretically capable of 16x250 MB/s = 4 GB/s in each direction. While this is correct in terms of data bytes, more meaningful calculations are based on the usable data payload rate, which depends on the profile of the traffic, which is a function of the high-level (software) application and intermediate protocol levels. Like other high data rate serial interconnect systems, PCIe has a protocol and processing overhead due to the additional transfer robustness (CRC and acknowledgements). Long continuous unidirectional transfers (such as those typical in high-performance storage controllers) can approach >95% of PCIe's raw (lane) data rate. These transfers also benefit the most from increased number of lanes (x2, x4, etc.) But in more typical applications (such as a <a href="/wiki/Universal_Serial_Bus" class="mw-redirect" title="Universal Serial Bus">USB</a> or <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> controller), the traffic profile is characterized as short data packets with frequent enforced acknowledgements.<a href="#cite_note-traffic_profile-136">[130]</a> This type of traffic reduces the efficiency of the link, due to overhead from packet parsing and forced interrupts (either in the device's host interface or the PC's CPU). Being a protocol for devices connected to the same <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a>, it does not require the same tolerance for transmission errors as a protocol for communication over longer distances, and thus, this loss of efficiency is not particular to PCIe. <div class="mw-heading mw-heading3"><h3 id="Efficiency_of_the_link">Efficiency of the link</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=40" title="Edit section: Efficiency of the link">edit</a>]</div> As for any network-like communication links, some of the raw bandwidth is consumed by protocol overhead:<a href="#cite_note-Xilinx-137">[131]</a> A PCIe 1.x lane for example offers a data rate on top of the physical layer of 250 MB/s (simplex). This is not the payload bandwidth but the physical layer bandwidth – a PCIe lane has to carry additional information for full functionality.<a href="#cite_note-Xilinx-137">[131]</a> <table class="wikitable"> <caption>Gen 2 Transaction Layer Packet<a href="#cite_note-Xilinx-137">[131]</a>: 3  </caption> <tbody><tr> <th scope="col" style="width: 80px;">Layer </th> <th scope="col" style="width: 20px;">PHY </th> <th scope="col" style="width: 120px;">Data Link Layer </th> <th scope="col" style="width: 400px;" colspan="3">Transaction </th> <th scope="col" style="width: 120px;">Data Link Layer </th> <th scope="col" style="width: 20px;">PHY </th></tr> <tr> <th scope="row">Data </th> <td>Start </td> <td>Sequence </td> <td scope="col" style="width: 75px;">Header </td> <td scope="col" style="text-align:center; width: 250px;">Payload </td> <td scope="col" style="width: 75px;">ECRC </td> <td>LCRC </td> <td>End </td></tr> <tr> <th scope="row">Size (Bytes) </th> <td>1 </td> <td>2 </td> <td>12 or 16 </td> <td scope="col" style="text-align:center;">0 to 4096 </td> <td>4 (optional) </td> <td>4 </td> <td>1 </td></tr></tbody></table> The Gen2 overhead is then 20, 24, or 28 bytes per transaction.[<a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify">clarification needed</a>][<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] <table class="wikitable"> <caption>Gen 3 Transaction Layer Packet<a href="#cite_note-Xilinx-137">[131]</a>: 3  </caption> <tbody><tr> <th scope="col" style="width: 80px;">Layer </th> <th scope="col" style="width: 40px;">PHY </th> <th scope="col" style="width: 120px;">Data Link Layer </th> <th scope="col" colspan="3" style="width: 400px;">Transaction Layer </th> <th scope="col" style="width: 120px;">Data Link Layer </th></tr> <tr> <th scope="row">Data </th> <td>Start </td> <td>Sequence </td> <td scope="col" style="width: 75px;">Header </td> <td scope="col" style="width: 250px;text-align:center;">Payload </td> <td scope="col" style="width: 75px;">ECRC </td> <td>LCRC </td></tr> <tr> <th scope="row">Size (Bytes) </th> <td>4 </td> <td>2 </td> <td>12 or 16 </td> <td scope="col" style="text-align:center;">0 to 4096 </td> <td>4 (optional) </td> <td>4 </td></tr></tbody></table> The Gen3 overhead is then 22, 26 or 30 bytes per transaction.[<a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify">clarification needed</a>][<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] The <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\text{Packet Efficiency}}={\frac {\text{Payload}}{{\text{Payload}}+{\text{Overhead}}}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mtext>Packet Efficiency</mtext> </mrow> <mo>=</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mtext>Payload</mtext> <mrow> <mrow class="MJX-TeXAtom-ORD"> <mtext>Payload</mtext> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mtext>Overhead</mtext> </mrow> </mrow> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\text{Packet Efficiency}}={\frac {\text{Payload}}{{\text{Payload}}+{\text{Overhead}}}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/ac295a94a3db99ad0ca03d4e1eabf4d9b15b2b9e" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.338ex; width:42.212ex; height:5.843ex;" alt="{\displaystyle {\text{Packet Efficiency}}={\frac {\text{Payload}}{{\text{Payload}}+{\text{Overhead}}}}}"> for a 128 byte payload is 86%, and 98% for a 1024 byte payload. For small accesses like register settings (4 bytes), the efficiency drops as low as 16%.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="Formula is in text, but it didn't state this anywhere or anything about register settings being 4 bytes or the like... and most of the PCIe config registers aren't on the devices and don't need a bus access, they're just sitting around in a DMA region mapped to the CPU's control registers (September 2021)">citation needed</a>] The maximum payload size (MPS) is set on all devices based on smallest maximum on any device in the chain. If one device has an MPS of 128 bytes, all devices of the tree must set their MPS to 128 bytes. In this case the bus will have a peak efficiency of 86% for writes.<a href="#cite_note-Xilinx-137">[131]</a>: 3  <div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=41" title="Edit section: Applications">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b7/ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg/220px-ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b7/ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg/330px-ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b7/ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg/440px-ASUS_GTX-650_Ti_TOP_Cu-II_PCI_Express_3.0_x16_graphics_card.jpg 2x" data-file-width="1280" data-file-height="960" /></a><figcaption><a href="/wiki/Asus" title="Asus">Asus</a> Nvidia GeForce GTX 650 Ti, a PCI Express 3.0 x16 graphics card</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:NVIDIA-GTX-1070-FoundersEdition-FL.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/220px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg" decoding="async" width="220" height="164" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/330px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/440px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg 2x" data-file-width="4700" data-file-height="3500" /></a><figcaption>The <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> GeForce GTX 1070, a PCI Express 3.0 x16 Graphics card</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:An_Intel_82574L_Gigabit_Ethernet_NIC,_PCI_Express_x1_card.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/24/An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg/220px-An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/24/An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg/330px-An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/24/An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg/440px-An_Intel_82574L_Gigabit_Ethernet_NIC%2C_PCI_Express_x1_card.jpg 2x" data-file-width="1280" data-file-height="960" /></a><figcaption><a href="/wiki/Intel" title="Intel">Intel</a> 82574L Gigabit Ethernet <a href="/wiki/Network_interface_controller" title="Network interface controller">NIC</a>, a PCI Express x1 card</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SATA_6_Gbit-s_controller,_in_form_of_a_PCI_Express_card.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg/220px-SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg/330px-SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3d/SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg/440px-SATA_6_Gbit-s_controller%2C_in_form_of_a_PCI_Express_card.jpg 2x" data-file-width="1280" data-file-height="960" /></a><figcaption>A <a href="/wiki/Marvell_Technology" title="Marvell Technology">Marvell</a>-based <a href="/wiki/SATA_3.0" class="mw-redirect" title="SATA 3.0">SATA 3.0</a> controller, as a PCI Express x1 card</figcaption></figure> PCI Express operates in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals), a passive backplane interconnect and as an <a href="/wiki/Expansion_card" title="Expansion card">expansion card</a> interface for add-in boards. In virtually all modern (as of 2012<a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&action=edit">[update]</a>) PCs, from consumer laptops and desktops to enterprise data servers, the PCIe bus serves as the primary motherboard-level interconnect, connecting the host system-processor with both integrated peripherals (surface-mounted ICs) and add-on peripherals (expansion cards). In most of these systems, the PCIe bus co-exists with one or more legacy PCI buses, for backward compatibility with the large body of legacy PCI peripherals. As of 2013<a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&action=edit">[update]</a>, PCI Express has replaced <a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> as the default interface for graphics cards on new systems. Almost all models of <a href="/wiki/Graphics_card" title="Graphics card">graphics cards</a> released since 2010 by <a href="/wiki/AMD_Graphics" class="mw-redirect" title="AMD Graphics">AMD</a> (ATI) and <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> use PCI Express. Nvidia used the high-bandwidth data transfer of PCIe for its <a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">Scalable Link Interface</a> (SLI) technology, which allowed multiple graphics cards of the same chipset and model number to run in tandem, allowing increased performance.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] This interface has, since, been discontinued. AMD has also developed a multi-GPU system based on PCIe called <a href="/wiki/ATI_CrossFire" class="mw-redirect" title="ATI CrossFire">CrossFire</a>.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] AMD, Nvidia, and Intel have released motherboard chipsets that support as many as four PCIe x16 slots, allowing tri-GPU and quad-GPU card configurations. <div class="mw-heading mw-heading3"><h3 id="External_GPUs">External GPUs</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=42" title="Edit section: External GPUs">edit</a>]</div> Theoretically, external PCIe could give a notebook the graphics power of a desktop, by connecting a notebook with any PCIe desktop video card (enclosed in its own external housing, with a power supply and cooling); this is possible with an ExpressCard or <a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a> interface. An ExpressCard interface provides <a href="/wiki/Bit_rate" title="Bit rate">bit rates</a> of 5 Gbit/s (0.5 GB/s throughput), whereas a Thunderbolt interface provides bit rates of up to 40 Gbit/s (5 GB/s throughput). In 2006, <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> developed the <a href="/wiki/Nvidia_Quadro_Plex" title="Nvidia Quadro Plex">Quadro Plex</a> external PCIe family of <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPUs</a> that can be used for advanced graphic applications for the professional market.<a href="#cite_note-gxHZT-138">[132]</a> These video cards require a PCI Express x8 or x16 slot for the host-side card, which connects to the Plex via a <a href="/wiki/VHDCI" class="mw-redirect" title="VHDCI">VHDCI</a> carrying eight PCIe lanes.<a href="#cite_note-zJYg8-139">[133]</a> In 2008, AMD announced the <a href="/wiki/ATI_XGP" class="mw-redirect" title="ATI XGP">ATI XGP</a> technology, based on a proprietary cabling system that is compatible with PCIe x8 signal transmissions.<a href="#cite_note-HgxXj-140">[134]</a> This connector is available on the Fujitsu Amilo and the Acer Ferrari One notebooks. Fujitsu launched their AMILO GraphicBooster enclosure for XGP soon thereafter.<a href="#cite_note-WHU07-141">[135]</a> Around 2010 Acer launched the Dynavivid graphics dock for XGP.<a href="#cite_note-mvR09-142">[136]</a> In 2010, external card hubs were introduced that can connect to a laptop or desktop through a PCI ExpressCard slot. These hubs can accept full-sized graphics cards. Examples include MSI GUS,<a href="#cite_note-ZAJ0y-143">[137]</a> Village Instrument's ViDock,<a href="#cite_note-J5UtH-144">[138]</a> the Asus <a href="/wiki/XG_Station" title="XG Station">XG Station</a>, Bplus PE4H V3.2 adapter,<a href="#cite_note-jWWJt-145">[139]</a> as well as more improvised DIY devices.<a href="#cite_note-ERk1e-146">[140]</a> However such solutions are limited by the size (often only x1) and version of the available PCIe slot on a laptop. The Intel Thunderbolt interface has provided a new option to connect with a PCIe card externally. Magma has released the ExpressBox 3T, which can hold up to three PCIe cards (two at x8 and one at x4).<a href="#cite_note-CvJwZ-147">[141]</a> MSI also released the Thunderbolt GUS II, a PCIe chassis dedicated for video cards.<a href="#cite_note-OLzu7-148">[142]</a> Other products such as the Sonnet's Echo Express<a href="#cite_note-5LOrR-149">[143]</a> and mLogic's mLink are Thunderbolt PCIe chassis in a smaller form factor.<a href="#cite_note-apXPa-150">[144]</a> In 2017, more fully featured external card hubs were introduced, such as the Razer Core, which has a full-length PCIe x16 interface.<a href="#cite_note-PXbHS-151">[145]</a> <div class="mw-heading mw-heading3"><h3 id="Storage_devices">Storage devices</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=43" title="Edit section: Storage devices">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCIe_card_full_height.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/ae/PCIe_card_full_height.jpg/220px-PCIe_card_full_height.jpg" decoding="async" width="220" height="155" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/ae/PCIe_card_full_height.jpg/330px-PCIe_card_full_height.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/ae/PCIe_card_full_height.jpg/440px-PCIe_card_full_height.jpg 2x" data-file-width="2569" data-file-height="1811" /></a><figcaption>An <a href="/wiki/OCZ" title="OCZ">OCZ</a> RevoDrive <a href="/wiki/Solid-state_drive" title="Solid-state drive">SSD</a>, a full-height x4 PCI Express card</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/SATA_Express" title="SATA Express">SATA Express</a> and <a href="/wiki/NVMe" class="mw-redirect" title="NVMe">NVMe</a></div> The PCI Express protocol can be used as data interface to <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a> devices, such as <a href="/wiki/Memory_card" title="Memory card">memory cards</a> and <a href="/wiki/Solid-state_drive" title="Solid-state drive">solid-state drives</a> (SSDs). The <a href="/wiki/XQD_card" title="XQD card">XQD card</a> is a memory card format utilizing PCI Express, developed by the CompactFlash Association, with transfer rates of up to 1 GB/s.<a href="#cite_note-49Gx4-152">[146]</a> Many high-performance, enterprise-class SSDs are designed as PCI Express <a href="/wiki/RAID_controller" class="mw-redirect" title="RAID controller">RAID controller</a> cards.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] Before NVMe was standardized, many of these cards utilized proprietary interfaces and custom drivers to communicate with the operating system; they had much higher transfer rates (over 1 GB/s) and IOPS (over one million I/O operations per second) when compared to Serial ATA or <a href="/wiki/Serial_attached_SCSI" class="mw-redirect" title="Serial attached SCSI">SAS</a> drives.[<a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers" title="Wikipedia:Manual of Style/Dates and numbers">quantify</a>]<a href="#cite_note-P3Feb-153">[147]</a><a href="#cite_note-NeWKh-154">[148]</a> For example, in 2011 OCZ and Marvell co-developed a native PCI Express solid-state drive controller for a PCI Express 3.0 x16 slot with maximum capacity of 12 TB and a performance of to 7.2 GB/s sequential transfers and up to 2.52 million IOPS in random transfers.<a href="#cite_note-VLf63-155">[149]</a>[<a href="/wiki/Wikipedia:Writing_better_articles#Stay_on_topic" title="Wikipedia:Writing better articles"><span title="The material near this tag may contain information that is not relevant to the article's main topic. Can't find any info on whether this product was even sold, and I can't imagine it was when the other thing OCZ was in the news for at the time were their PCIe based SSDs being constantly failing nightmares that were impossible to recover because of the proprietary interface and required drivers... Enterprise would have rightfully scoffed at those numbers, thrown a couple thousand more regular SSDs in their giant storage arrays if they needed more than the billions of IOPS they were already achieving, maybe updated from 40 Gbps to 100 Gbps runs between the storage servers, and called it a day. (September 2021)">relevant?</a>] <a href="/wiki/SATA_Express" title="SATA Express">SATA Express</a> was an interface for connecting SSDs through SATA-compatible ports, optionally providing multiple PCI Express lanes as a pure PCI Express connection to the attached storage device.<a href="#cite_note-ymSig-156">[150]</a> <a href="/wiki/M.2" title="M.2">M.2</a> is a specification for internally mounted computer <a href="/wiki/Expansion_card" title="Expansion card">expansion cards</a> and associated connectors, which also uses multiple PCI Express lanes.<a href="#cite_note-SNLQe-157">[151]</a> PCI Express storage devices can implement both <a href="/wiki/AHCI" class="mw-redirect" title="AHCI">AHCI</a> logical interface for backward compatibility, and <a href="/wiki/NVM_Express" title="NVM Express">NVM Express</a> logical interface for much faster I/O operations provided by utilizing internal parallelism offered by such devices. Enterprise-class SSDs can also implement <a href="/wiki/SCSI_over_PCI_Express" class="mw-redirect" title="SCSI over PCI Express">SCSI over PCI Express</a>.<a href="#cite_note-FJvMX-158">[152]</a> <div class="mw-heading mw-heading3"><h3 id="Cluster_interconnect">Cluster interconnect</h3>[<a href="/w/index.php?title=PCI_Express&action=edit&section=44" title="Edit section: Cluster interconnect">edit</a>]</div> Certain <a href="/wiki/Data-center" class="mw-redirect" title="Data-center">data-center</a> applications (such as large <a href="/wiki/Computer_cluster" title="Computer cluster">computer clusters</a>) require the use of fiber-optic interconnects due to the distance limitations inherent in copper cabling. Typically, a network-oriented standard such as Ethernet or <a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a> suffices for these applications, but in some cases the overhead introduced by <a href="/wiki/Routing" title="Routing">routable</a> protocols is undesirable and a lower-level interconnect, such as <a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a>, <a href="/wiki/RapidIO" title="RapidIO">RapidIO</a>, or <a href="/wiki/NUMAlink" title="NUMAlink">NUMAlink</a> is needed. Local-bus standards such as PCIe and <a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a> can in principle be used for this purpose,<a href="#cite_note-YUum6-159">[153]</a> but as of 2015<a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&action=edit">[update]</a>, solutions are only available from niche vendors such as <a href="/wiki/Dolphin_Interconnect_Solutions" title="Dolphin Interconnect Solutions">Dolphin ICS</a>, and TTTech Auto. <div class="mw-heading mw-heading2"><h2 id="Competing_protocols">Competing protocols</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=45" title="Edit section: Competing protocols">edit</a>]</div> Other communications standards based on high bandwidth serial architectures include <a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a>, <a href="/wiki/RapidIO" title="RapidIO">RapidIO</a>, <a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a>, <a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a>, the <a href="/wiki/Mobile_Industry_Processor_Interface" class="mw-redirect" title="Mobile Industry Processor Interface">Mobile Industry Processor Interface</a> (MIPI), and <a href="/wiki/NVLink" title="NVLink">NVLink</a>. Differences are based on the trade-offs between flexibility and extensibility vs latency and overhead. For example, making the system hot-pluggable, as with Infiniband but not PCI Express, requires that software track network topology changes.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] Another example is making the packets shorter to decrease latency (as is required if a bus must operate as a memory interface). Smaller packets mean packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] PCI Express falls somewhere in the middle,[<a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="In the middle of *what*? What are the endpoints? Nothing above talks about device interconnects or routed network protocols; some discussion of routing was removed in a February 2019 edit, leaving this paragraph missing some context. (September 2024)">clarification needed</a>] targeted by design as a system interconnect (<a href="/wiki/Local_bus" title="Local bus">local bus</a>) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] Delays in PCIe 4.0 implementations led to the <a href="/wiki/Gen-Z_(consortium)" title="Gen-Z (consortium)">Gen-Z</a> consortium, the CCIX effort and an open <a href="/wiki/Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface</a> (CAPI) all being announced by the end of 2016.<a href="#cite_note-1Jwlv-160">[154]</a> On 11 March 2019, Intel presented <a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a>, a new interconnect bus, based on the PCI Express 5.0 physical layer infrastructure. The initial promoters of the CXL specification included: <a href="/wiki/Alibaba_Group" title="Alibaba Group">Alibaba</a>, <a href="/wiki/Cisco" title="Cisco">Cisco</a>, <a href="/wiki/Dell_EMC" title="Dell EMC">Dell EMC</a>, <a href="/wiki/Facebook" title="Facebook">Facebook</a>, <a href="/wiki/Google" title="Google">Google</a>, <a href="/wiki/Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">HPE</a>, <a href="/wiki/Huawei" title="Huawei">Huawei</a>, <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/Microsoft" title="Microsoft">Microsoft</a>.<a href="#cite_note-aJ00L-161">[155]</a> <div class="mw-heading mw-heading2"><h2 id="Integrators_list">Integrators list</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=46" title="Edit section: Integrators list">edit</a>]</div> The PCI-SIG Integrators List lists products made by PCI-SIG member companies that have passed compliance testing. The list include switches, bridges, NICs, SSDs, etc.<a href="#cite_note-9ps7Q-162">[156]</a> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=47" title="Edit section: See also">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><a href="/wiki/File:Nuvola_apps_ksim.png" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/28px-Nuvola_apps_ksim.png" decoding="async" width="28" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/42px-Nuvola_apps_ksim.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/56px-Nuvola_apps_ksim.png 2x" data-file-width="128" data-file-height="128" /></a><a href="/wiki/Portal:Electronics" title="Portal:Electronics">Electronics portal</a></li></ul> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 22em;"> <ul><li><a href="/wiki/Active_State_Power_Management" title="Active State Power Management">Active State Power Management</a> (ASPM)</li> <li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">Peripheral Component Interconnect</a> (PCI)</li> <li><a href="/wiki/PCI_configuration_space" title="PCI configuration space">PCI configuration space</a></li> <li><a href="/wiki/PCI-X" title="PCI-X">PCI-X</a> (PCI Extended)</li> <li><a href="/wiki/PCI/104-Express" title="PCI/104-Express">PCI/104-Express</a></li> <li><a href="/wiki/PCIe/104" class="mw-redirect" title="PCIe/104">PCIe/104</a></li> <li><a href="/wiki/Root_complex" title="Root complex">Root complex</a></li> <li><a href="/wiki/Serial_Digital_Video_Out" title="Serial Digital Video Out">Serial Digital Video Out</a> (SDVO)</li> <li><a href="/wiki/List_of_device_bit_rates#Main_buses" class="mw-redirect" title="List of device bit rates">List of device bit rates § Main buses</a></li> <li><a href="/wiki/UCIe" title="UCIe">UCIe</a></li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link</a> (CXL)</li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=48" title="Edit section: Notes">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-2"><a href="#cite_ref-2">^</a> Switches can create multiple endpoints out of one to allow sharing it with multiple devices. </li> <li id="cite_note-64"><a href="#cite_ref-64">^</a> The card's <a href="/wiki/Serial_ATA#Standard_connector" class="mw-redirect" title="Serial ATA">Serial ATA power connector</a> is present because the USB 3.0 ports require more power than the PCI Express bus can supply. More often, a <a href="/wiki/Molex_connector#Disk_drive" title="Molex connector">4-pin Molex power connector</a> is used. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=49" title="Edit section: References">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=ZjyrAgAAQBAJ&dq=pcie+dual+simplex&pg=PA69">IBM Power 770 and 780 Technical Overview and Introduction</a>. IBM Redbooks. 6 June 2013. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7384-5121-3" title="Special:BookSources/978-0-7384-5121-3"><bdi>978-0-7384-5121-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+Power+770+and+780+Technical+Overview+and+Introduction&rft.pub=IBM+Redbooks&rft.date=2013-06-06&rft.isbn=978-0-7384-5121-3&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DZjyrAgAAQBAJ%26dq%3Dpcie%2Bdual%2Bsimplex%26pg%3DPA69&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-s5NDG-3"><a href="#cite_ref-s5NDG_3-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMayhewKrishnan2003" class="citation book cs1">Mayhew, D.; Krishnan, V. (August 2003). "PCI express and advanced switching: Evolutionary path to building next generation interconnects". 11th Symposium on High Performance Interconnects, 2003. Proceedings. pp. 21–29. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FCONECT.2003.1231473">10.1109/CONECT.2003.1231473</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7695-2012-X" title="Special:BookSources/0-7695-2012-X"><bdi>0-7695-2012-X</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:7456382">7456382</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=PCI+express+and+advanced+switching%3A+Evolutionary+path+to+building+next+generation+interconnects&rft.btitle=11th+Symposium+on+High+Performance+Interconnects%2C+2003.+Proceedings.&rft.pages=21-29&rft.date=2003-08&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A7456382%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FCONECT.2003.1231473&rft.isbn=0-7695-2012-X&rft.aulast=Mayhew&rft.aufirst=D.&rft.au=Krishnan%2C+V.&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-DQmzv-4"><a href="#cite_ref-DQmzv_4-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pcmag.com/encyclopedia/term/48998/pci-express">"Definition of PCI Express"</a>. PCMag.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=PCMag&rft.atitle=Definition+of+PCI+Express&rft_id=https%3A%2F%2Fwww.pcmag.com%2Fencyclopedia%2Fterm%2F48998%2Fpci-express&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-gf9Lm-5"><a href="#cite_ref-gf9Lm_5-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZhangNguyen2007" class="citation web cs1">Zhang, Yanmin; Nguyen, T Long (June 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160310074031/https://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf">"Enable PCI Express Advanced Error Reporting in the Kernel"</a> (PDF). Proceedings of the Linux Symposium. Fedora project. Archived from <a rel="nofollow" class="external text" href="https://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf">the original</a> (PDF) on 10 March 2016. Retrieved 8 May 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Proceedings+of+the+Linux+Symposium&rft.atitle=Enable+PCI+Express+Advanced+Error+Reporting+in+the+Kernel&rft.date=2007-06&rft.aulast=Zhang&rft.aufirst=Yanmin&rft.au=Nguyen%2C+T+Long&rft_id=http%3A%2F%2Fols.fedoraproject.org%2FOLS%2FReprints-2007%2Fzhang-Reprint.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-sxOen-6"><a href="#cite_ref-sxOen_6-0">^</a> <a rel="nofollow" class="external free" href="https://www.hyperstone.com">https://www.hyperstone.com</a> Flash Memory Form Factors – The Fundamentals of Reliable Flash Storage, Retrieved 19 April 2018 </li> <li id="cite_note-pcie-basics-7">^ <a href="#cite_ref-pcie-basics_7-0">a</a> <a href="#cite_ref-pcie-basics_7-1">b</a> <a href="#cite_ref-pcie-basics_7-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRavi_Budruk2007" class="citation web cs1">Ravi Budruk (21 August 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140715120034/http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67">"PCI Express Basics"</a>. <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a>. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67">the original</a> (PDF) on 15 July 2014. Retrieved 15 July 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+Basics&rft.pub=PCI-SIG&rft.date=2007-08-21&rft.au=Ravi+Budruk&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fdevelopers%2Fmain%2Ftraining_materials%2Fget_document%3Fdoc_id%3D4e00a39acaa5c5a8ee44ebb07baba982e5972c67&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-8"><a href="#cite_ref-8">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://pcguide101.com/motherboard/what-are-pcie-slots/">"What are PCIe Slots and Their Uses"</a>. PC Guide 101. 18 May 2021. Retrieved 21 June 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=What+are+PCIe+Slots+and+Their+Uses&rft.pub=PC+Guide+101&rft.date=2021-05-18&rft_id=https%3A%2F%2Fpcguide101.com%2Fmotherboard%2Fwhat-are-pcie-slots%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-howstuffworks1-9"><a href="#cite_ref-howstuffworks1_9-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://computer.howstuffworks.com/pci-express.htm">"How PCI Express Works"</a>. How Stuff Works. 17 August 2005. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20091203053924/http://computer.howstuffworks.com/pci-express.htm">Archived</a> from the original on 3 December 2009. Retrieved 7 December 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=How+Stuff+Works&rft.atitle=How+PCI+Express+Works&rft.date=2005-08-17&rft_id=http%3A%2F%2Fcomputer.howstuffworks.com%2Fpci-express.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-4TrCr-10"><a href="#cite_ref-4TrCr_10-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2">"4.2.4.9. Link Width and Lane Sequence Negotiation", PCI Express Base Specification, Revision 2.1., 4 March 2009</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=4.2.4.9.+Link+Width+and+Lane+Sequence+Negotiation&rft.btitle=PCI+Express+Base+Specification%2C+Revision+2.1.&rft.date=2009-03-04&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-faq1-11">^ <a href="#cite_ref-faq1_11-0">a</a> <a href="#cite_ref-faq1_11-1">b</a> <a href="#cite_ref-faq1_11-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20081113163608/http://www.pcisig.com/news_room/faqs/faq_express/">"PCI Express Architecture Frequently Asked Questions"</a>. PCI-SIG. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/faqs/faq_express/">the original</a> on 13 November 2008. Retrieved 23 November 2008.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+Architecture+Frequently+Asked+Questions&rft.pub=PCI-SIG&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Ffaqs%2Ffaq_express%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-2Nt8T-12"><a href="#cite_ref-2Nt8T_12-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20071208162241/http://www.interfacebus.com/Design_Connector_PCI_Express.html">"PCI Express Bus"</a>. Interface bus. Archived from <a rel="nofollow" class="external text" href="http://www.interfacebus.com/Design_Connector_PCI_Express.html">the original</a> on 8 December 2007. Retrieved 12 June 2010.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Interface+bus&rft.atitle=PCI+Express+Bus&rft_id=http%3A%2F%2Fwww.interfacebus.com%2FDesign_Connector_PCI_Express.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-Gchhw-13"><a href="#cite_ref-Gchhw_13-0">^</a> 32 lanes are defined by the PCIe Base Specification up to PCIe 5.0 but there's no card standard in the PCIe Card Electromechanical Specification and that lane number was never implemented. </li> <li id="cite_note-odC7t-14"><a href="#cite_ref-odC7t_14-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100105163040/http://zone.ni.com/devzone/cda/tut/p/id/3767">"PCI Express – An Overview of the PCI Express Standard"</a>. Developer Zone. National Instruments. 13 August 2009. Archived from <a rel="nofollow" class="external text" href="http://zone.ni.com/devzone/cda/tut/p/id/3767">the original</a> on 5 January 2010. Retrieved 7 December 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Developer+Zone&rft.atitle=PCI+Express+%E2%80%93+An+Overview+of+the+PCI+Express+Standard&rft.date=2009-08-13&rft_id=http%3A%2F%2Fzone.ni.com%2Fdevzone%2Fcda%2Ftut%2Fp%2Fid%2F3767&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-P7MD8-15"><a href="#cite_ref-P7MD8_15-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFQazi" class="citation web cs1">Qazi, Atif. <a rel="nofollow" class="external text" href="https://pcgearlab.com/motherboard/what-are-pcie-slots/">"What are PCIe Slots?"</a>. PC Gear Lab. Retrieved 8 April 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=PC+Gear+Lab&rft.atitle=What+are+PCIe+Slots%3F&rft.aulast=Qazi&rft.aufirst=Atif&rft_id=https%3A%2F%2Fpcgearlab.com%2Fmotherboard%2Fwhat-are-pcie-slots%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-8AKZj-16"><a href="#cite_ref-8AKZj_16-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.nvmexpress.org/blog/new-pcie-form-factor-enables-greater-pcie-ssd-adoption/">"New PCIe Form Factor Enables Greater PCIe SSD Adoption"</a>. NVM Express. 12 June 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150906180730/http://www.nvmexpress.org/blog/new-pcie-form-factor-enables-greater-pcie-ssd-adoption/">Archived</a> from the original on 6 September 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=NVM+Express&rft.atitle=New+PCIe+Form+Factor+Enables+Greater+PCIe+SSD+Adoption&rft.date=2012-06-12&rft_id=http%3A%2F%2Fwww.nvmexpress.org%2Fblog%2Fnew-pcie-form-factor-enables-greater-pcie-ssd-adoption%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-c1yve-17"><a href="#cite_ref-c1yve_17-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.storagereview.com/memblaze_pblaze4_aic_nvme_ssd_review">"Memblaze PBlaze4 AIC NVMe SSD Review"</a>. StorageReview. 21 December 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=StorageReview&rft.atitle=Memblaze+PBlaze4+AIC+NVMe+SSD+Review&rft.date=2015-12-21&rft_id=http%3A%2F%2Fwww.storagereview.com%2Fmemblaze_pblaze4_aic_nvme_ssd_review&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-j6TTS-18"><a href="#cite_ref-j6TTS_18-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJuly_20152015" class="citation web cs1">July 2015, Kane Fulton 20 (20 July 2015). <a rel="nofollow" class="external text" href="https://www.techradar.com/news/gaming/19-graphics-cards-that-shaped-the-future-of-gaming-1289666">"19 graphics cards that shaped the future of gaming"</a>. TechRadar.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechRadar&rft.atitle=19+graphics+cards+that+shaped+the+future+of+gaming&rft.date=2015-07-20&rft.aulast=July+2015&rft.aufirst=Kane+Fulton+20&rft_id=https%3A%2F%2Fwww.techradar.com%2Fnews%2Fgaming%2F19-graphics-cards-that-shaped-the-future-of-gaming-1289666&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: numeric names: authors list (<a href="/wiki/Category:CS1_maint:_numeric_names:_authors_list" title="Category:CS1 maint: numeric names: authors list">link</a>) </li> <li id="cite_note-RAreG-19"><a href="#cite_ref-RAreG_19-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLeadbetter2020" class="citation web cs1">Leadbetter, Richard (16 September 2020). <a rel="nofollow" class="external text" href="https://www.eurogamer.net/articles/digitalfoundry-2020-nvidia-geforce-rtx-3080-review">"Nvidia GeForce RTX 3080 review: welcome to the next level"</a>. <a href="/wiki/Eurogamer" title="Eurogamer">Eurogamer</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Eurogamer&rft.atitle=Nvidia+GeForce+RTX+3080+review%3A+welcome+to+the+next+level&rft.date=2020-09-16&rft.aulast=Leadbetter&rft.aufirst=Richard&rft_id=https%3A%2F%2Fwww.eurogamer.net%2Farticles%2Fdigitalfoundry-2020-nvidia-geforce-rtx-3080-review&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-20"><a href="#cite_ref-20">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDiscuss2023" class="citation web cs1">Discuss, btarunr (6 January 2023). <a rel="nofollow" class="external text" href="https://www.techpowerup.com/303148/asus-x-noctua-rtx-4080-graphics-card-is-5-slots-thick-we-go-hands-on">"ASUS x Noctua RTX 4080 Graphics Card is 5 Slots Thick, We Go Hands-on"</a>. TechPowerUp. Retrieved 19 September 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=ASUS+x+Noctua+RTX+4080+Graphics+Card+is+5+Slots+Thick%2C+We+Go+Hands-on&rft.date=2023-01-06&rft.aulast=Discuss&rft.aufirst=btarunr&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F303148%2Fasus-x-noctua-rtx-4080-graphics-card-is-5-slots-thick-we-go-hands-on&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-E0Tsg-21"><a href="#cite_ref-E0Tsg_21-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://bit-tech.net/reviews/tech/graphics/sapphire-radeon-rx-5700-xt-pulse-review/1/">"Sapphire Radeon RX 5700 XT Pulse Review | bit-tech.net"</a>. bit-tech.net. Retrieved 26 August 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=bit-tech.net&rft.atitle=Sapphire+Radeon+RX+5700+XT+Pulse+Review+%7C+bit-tech.net&rft_id=https%3A%2F%2Fbit-tech.net%2Freviews%2Ftech%2Fgraphics%2Fsapphire-radeon-rx-5700-xt-pulse-review%2F1%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-mAt96-22"><a href="#cite_ref-mAt96_22-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20190901193735/http://xfxforce.com/en-gb/Products/product-category/amd-radeon-rx-5700xt-8gb-thicc-ii-rx-57xt8dfd6">"AMD Radeon™ RX 5700 XT 8GB GDDR6 THICC II – RX-57XT8DFD6"</a>. xfxforce.com. Archived from <a rel="nofollow" class="external text" href="http://xfxforce.com/en-gb/Products/product-category/amd-radeon-rx-5700xt-8gb-thicc-ii-rx-57xt8dfd6">the original</a> on 1 September 2019. Retrieved 25 August 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=xfxforce.com&rft.atitle=AMD+Radeon%E2%84%A2+RX+5700+XT+8GB+GDDR6+THICC+II+%E2%80%93+RX-57XT8DFD6&rft_id=http%3A%2F%2Fxfxforce.com%2Fen-gb%2FProducts%2Fproduct-category%2Famd-radeon-rx-5700xt-8gb-thicc-ii-rx-57xt8dfd6&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-kk3xz-23"><a href="#cite_ref-kk3xz_23-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://rog.asus.com/graphics-cards/graphics-cards/rog-strix/rog-strix-rtx3080-o10g-gaming-model/spec">"ROG Strix GeForce RTX 3080 OC Edition 10GB GDDR6X | Graphics Cards"</a>. rog.asus.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=rog.asus.com&rft.atitle=ROG+Strix+GeForce+RTX+3080+OC+Edition+10GB+GDDR6X+%26%23124%3B+Graphics+Cards&rft_id=https%3A%2F%2Frog.asus.com%2Fgraphics-cards%2Fgraphics-cards%2Frog-strix%2Frog-strix-rtx3080-o10g-gaming-model%2Fspec&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-IM1RH-24"><a href="#cite_ref-IM1RH_24-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20111102042843/http://www.adexelec.com/faq.htm#pcikeys">"What is the A side, B side configuration of PCI cards"</a>. Frequently Asked Questions. Adex Electronics. 1998. Archived from <a rel="nofollow" class="external text" href="http://www.adexelec.com/faq.htm#pcikeys">the original</a> on 2 November 2011. Retrieved 24 October 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Frequently+Asked+Questions&rft.atitle=What+is+the+A+side%2C+B+side+configuration+of+PCI+cards&rft.date=1998&rft_id=http%3A%2F%2Fwww.adexelec.com%2Ffaq.htm%23pcikeys&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIe_card_2-25">^ <a href="#cite_ref-PCIe_card_2_25-0">a</a> <a href="#cite_ref-PCIe_card_2_25-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2">PCI Express Card Electromechanical Specification Revision 2.0</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=PCI+Express+Card+Electromechanical+Specification+Revision+2.0&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ajnim-26"><a href="#cite_ref-ajnim_26-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://members.pcisig.com/wg/PCI-SIG/document/13446">"PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Clean)"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+Card+Electromechanical+Specification+Revision+4.0%2C+Version+1.0+%28Clean%29&rft_id=https%3A%2F%2Fmembers.pcisig.com%2Fwg%2FPCI-SIG%2Fdocument%2F13446&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-vj2hg-27"><a href="#cite_ref-vj2hg_27-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20181204125124/http://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf">"L1 PM Substates with CLKREQ, Revision 1.0a"</a> (PDF). PCI-SIG. Archived from <a rel="nofollow" class="external text" href="https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf">the original</a> (PDF) on 4 December 2018. Retrieved 8 November 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=L1+PM+Substates+with+CLKREQ%2C+Revision+1.0a&rft.pub=PCI-SIG&rft_id=https%3A%2F%2Fpcisig.com%2Fsites%2Fdefault%2Ffiles%2Fspecification_documents%2FECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-YpQVq-28"><a href="#cite_ref-YpQVq_28-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20181109193739/https://pcisig.com/sites/default/files/specification_documents/Emergency%20Power%20Reduction%20Mechanism%20with%20PWRBRK%20Signal%20ECN.pdf">"Emergency Power Reduction Mechanism with PWRBRK Signal ECN"</a> (PDF). PCI-SIG. Archived from <a rel="nofollow" class="external text" href="https://pcisig.com/sites/default/files/specification_documents/Emergency%20Power%20Reduction%20Mechanism%20with%20PWRBRK%20Signal%20ECN.pdf">the original</a> (PDF) on 9 November 2018. Retrieved 8 November 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Emergency+Power+Reduction+Mechanism+with+PWRBRK+Signal+ECN&rft.pub=PCI-SIG&rft_id=https%3A%2F%2Fpcisig.com%2Fsites%2Fdefault%2Ffiles%2Fspecification_documents%2FEmergency%2520Power%2520Reduction%2520Mechanism%2520with%2520PWRBRK%2520Signal%2520ECN.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-29"><a href="#cite_ref-29">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://greatpcreview.com/guides/where-does-pcie-cables-go/">"Where Does PCIe Cable Go?"</a>. 16 January 2022. Retrieved 10 June 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Where+Does+PCIe+Cable+Go%3F&rft.date=2022-01-16&rft_id=https%3A%2F%2Fgreatpcreview.com%2Fguides%2Fwhere-does-pcie-cables-go%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-CEM1.1-30"><a href="#cite_ref-CEM1.1_30-0">^</a> PCI Express Card Electromechanical Specification Revision 1.1 </li> <li id="cite_note-jArAO-31"><a href="#cite_ref-jArAO_31-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSchoenborn2004" class="citation cs2">Schoenborn, Zale (2004), <a rel="nofollow" class="external text" href="http://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/639/7851.PCIe_5F00_designGuides.pdf#page=19">Board Design Guidelines for PCI Express Architecture</a> (PDF), PCI-SIG, pp. 19–21, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160327185412/http://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/639/7851.PCIe_5F00_designGuides.pdf#page=19">archived</a> (PDF) from the original on 27 March 2016</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Board+Design+Guidelines+for+PCI+Express+Architecture&rft.pages=19-21&rft.pub=PCI-SIG&rft.date=2004&rft.aulast=Schoenborn&rft.aufirst=Zale&rft_id=http%3A%2F%2Fe2e.ti.com%2Fcfs-file%2F__key%2Fcommunityserver-discussions-components-files%2F639%2F7851.PCIe_5F00_designGuides.pdf%23page%3D19&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-32"><a href="#cite_ref-32">^</a> PCI Express Base Specification, Revision 1.1 Page 332 </li> <li id="cite_note-JuErgh-33">^ <a href="#cite_ref-JuErgh_33-0">a</a> <a href="#cite_ref-JuErgh_33-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.molex.com/pdm_docs/ps/PS-45558-001-001.pdf">"Mini-Fit® PCI Express®* Wire to Board Connector System"</a> (PDF). Retrieved 4 December 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Mini-Fit%C2%AE+PCI+Express%C2%AE%2A+Wire+to+Board+Connector+System&rft_id=https%3A%2F%2Fwww.molex.com%2Fpdm_docs%2Fps%2FPS-45558-001-001.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-o2GFI-34"><a href="#cite_ref-o2GFI_34-0">^</a> PCI Express x16 Graphics 150W-ATX Specification Revision 1.0 </li> <li id="cite_note-uLc7Q-35"><a href="#cite_ref-uLc7Q_35-0">^</a> PCI Express 225 W/300 W High Power Card Electromechanical Specification Revision 1.0 </li> <li id="cite_note-CEM3.0-36"><a href="#cite_ref-CEM3.0_36-0">^</a> PCI Express Card Electromechanical Specification Revision 3.0 </li> <li id="cite_note-mcd6L-37"><a href="#cite_ref-mcd6L_37-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYun_Ling2008" class="citation web cs1">Yun Ling (16 May 2008). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20151105083550/http://kavi.pcisig.com/developers/main/training_materials/get_document?doc_id=fa4ec3357012d69821baa0856011c665ac770768">"PCIe Electromechanical Updates"</a>. Archived from <a rel="nofollow" class="external text" href="http://kavi.pcisig.com/developers/main/training_materials/get_document?doc_id=fa4ec3357012d69821baa0856011c665ac770768">the original</a> on 5 November 2015. Retrieved 7 November 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCIe+Electromechanical+Updates&rft.date=2008-05-16&rft.au=Yun+Ling&rft_id=http%3A%2F%2Fkavi.pcisig.com%2Fdevelopers%2Fmain%2Ftraining_materials%2Fget_document%3Fdoc_id%3Dfa4ec3357012d69821baa0856011c665ac770768&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-39"><a href="#cite_ref-39">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://members.pcisig.com/wg/PCI-SIG/document/17134">"12VHPWR Sideband Allocation and Requirements - PCIe 5.x ECN"</a>. PCI SIG. 12 May 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=12VHPWR+Sideband+Allocation+and+Requirements+-+PCIe+5.x+ECN&rft.pub=PCI+SIG&rft.date=2022-05-12&rft_id=https%3A%2F%2Fmembers.pcisig.com%2Fwg%2FPCI-SIG%2Fdocument%2F17134&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-40"><a href="#cite_ref-40">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://members.pcisig.com/wg/PCI-SIG/document/19972">"12V-2x6 Connector Updates to PCIe Base 6.0 - PCIe 6.x ECN"</a>. PCI SIG. 31 August 2023. <q>This ECN defines Connector Type encodings for the new 12V-2x6 connector. This connector, defined in CEM 5.1, replaces the 12VHPWR connector.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=12V-2x6+Connector+Updates+to+PCIe+Base+6.0+-+PCIe+6.x+ECN&rft.pub=PCI+SIG&rft.date=2023-08-31&rft_id=https%3A%2F%2Fmembers.pcisig.com%2Fwg%2FPCI-SIG%2Fdocument%2F19972&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-41"><a href="#cite_ref-41">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2015/02/understanding-m-2-the-interface-that-will-speed-up-your-next-ssd/">"Understanding M.2, the interface that will speed up your next SSD"</a>. 8 February 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Understanding+M.2%2C+the+interface+that+will+speed+up+your+next+SSD&rft.date=2015-02-08&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2015%2F02%2Funderstanding-m-2-the-interface-that-will-speed-up-your-next-ssd%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-DmwJz-42"><a href="#cite_ref-DmwJz_42-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.hwtools.net/Adapter/MP1.html">"MP1: Mini PCI Express / PCI Express Adapter"</a>. hwtools.net. 18 July 2014. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20141003233055/http://www.hwtools.net/Adapter/MP1.html">Archived</a> from the original on 3 October 2014. Retrieved 28 September 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=hwtools.net&rft.atitle=MP1%3A+Mini+PCI+Express+%2F+PCI+Express+Adapter&rft.date=2014-07-18&rft_id=http%3A%2F%2Fwww.hwtools.net%2FAdapter%2FMP1.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-43"><a href="#cite_ref-43">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=otfPEAAAQBAJ&dq=pci+express+micro&pg=PT628">IT Essentials Companion Guide v8</a>. Cisco Press. 9 July 2023. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-13-816625-0" title="Special:BookSources/978-0-13-816625-0"><bdi>978-0-13-816625-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IT+Essentials+Companion+Guide+v8&rft.pub=Cisco+Press&rft.date=2023-07-09&rft.isbn=978-0-13-816625-0&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DotfPEAAAQBAJ%26dq%3Dpci%2Bexpress%2Bmicro%26pg%3DPT628&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-44"><a href="#cite_ref-44">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://google.com.pa/books/edition/Mobile_Computing_Deployment_and_Manageme/rP5gBgAAQBAJ?hl=en&gbpv=1&dq=mini+pcie+full+size+half+size&pg=PA491&printsec=frontcover">Mobile Computing Deployment and Management: Real World Skills for CompTIA Mobility+ Certification and Beyond</a>. John Wiley & Sons. 24 February 2015. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-118-82461-0" title="Special:BookSources/978-1-118-82461-0"><bdi>978-1-118-82461-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Mobile+Computing+Deployment+and+Management%3A+Real+World+Skills+for+CompTIA+Mobility%2B+Certification+and+Beyond&rft.pub=John+Wiley+%26+Sons&rft.date=2015-02-24&rft.isbn=978-1-118-82461-0&rft_id=https%3A%2F%2Fgoogle.com.pa%2Fbooks%2Fedition%2FMobile_Computing_Deployment_and_Manageme%2FrP5gBgAAQBAJ%3Fhl%3Den%26gbpv%3D1%26dq%3Dmini%2Bpcie%2Bfull%2Bsize%2Bhalf%2Bsize%26pg%3DPA491%26printsec%3Dfrontcover&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-5xxpo-45"><a href="#cite_ref-5xxpo_45-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://forum.notebookreview.com/lenovo-ibm/574993-msata-faq-basic-primer.html">"mSATA FAQ: A Basic Primer"</a>. Notebook review. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120212164949/http://forum.notebookreview.com/lenovo-ibm/574993-msata-faq-basic-primer.html">Archived</a> from the original on 12 February 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=mSATA+FAQ%3A+A+Basic+Primer&rft_id=http%3A%2F%2Fforum.notebookreview.com%2Flenovo-ibm%2F574993-msata-faq-basic-primer.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-EeePC-46"><a href="#cite_ref-EeePC_46-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://beta.ivancover.com/wiki/index.php/Eee_PC_Research">"Eee PC Research"</a>. ivc (wiki). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100330035948/http://beta.ivancover.com/wiki/index.php/Eee_PC_Research">Archived</a> from the original on 30 March 2010. Retrieved 26 October 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ivc&rft.atitle=Eee+PC+Research&rft_id=http%3A%2F%2Fbeta.ivancover.com%2Fwiki%2Findex.php%2FEee_PC_Research&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-xpI66-47"><a href="#cite_ref-xpI66_47-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/support/motherboards/desktop/sb/CS-032415.htm?wapkw=032415">"Desktop Board Solid-state drive (SSD) compatibility"</a>. <a href="/wiki/Intel" title="Intel">Intel</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160102233130/http://www.intel.com/support/motherboards/desktop/sb/CS-032415.htm?wapkw=032415">Archived</a> from the original on 2 January 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Desktop+Board+Solid-state+drive+%28SSD%29+compatibility&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fmotherboards%2Fdesktop%2Fsb%2FCS-032415.htm%3Fwapkw%3D032415&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-oL68r-48"><a href="#cite_ref-oL68r_48-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.dell.com/support/article/en-us/sln301626/how-to-distinguish-the-differences-between-m-2-cards?lang=en">"How to distinguish the differences between M.2 cards | Dell US"</a>. www.dell.com. Retrieved 24 March 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.dell.com&rft.atitle=How+to+distinguish+the+differences+between+M.2+cards+%7C+Dell+US&rft_id=https%3A%2F%2Fwww.dell.com%2Fsupport%2Farticle%2Fen-us%2Fsln301626%2Fhow-to-distinguish-the-differences-between-m-2-cards%3Flang%3Den&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-pcie_cabling1.0-49"><a href="#cite_ref-pcie_cabling1.0_49-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/">"PCI Express External Cabling 1.0 Specification"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070210055546/http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/">Archived</a> from the original on 10 February 2007. Retrieved 9 February 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+External+Cabling+1.0+Specification&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fspecifications%2Fpciexpress%2Fpcie_cabling1.0%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ZTXPi-50"><a href="#cite_ref-ZTXPi_50-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131126064157/http://www.pcisig.com/news_room/news/press_release/02_07_07">"PCI Express External Cabling Specification Completed by PCI-SIG"</a>. PCI SIG. 7 February 2007. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/news/press_release/02_07_07">the original</a> on 26 November 2013. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+External+Cabling+Specification+Completed+by+PCI-SIG&rft.pub=PCI+SIG&rft.date=2007-02-07&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Fnews%2Fpress_release%2F02_07_07&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-OCuLink2-51">^ <a href="#cite_ref-OCuLink2_51-0">a</a> <a href="#cite_ref-OCuLink2_51-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170313215047/http://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/">"OCuLink connectors and cables support new PCIe standard"</a>. www.connectortips.com. Archived from <a rel="nofollow" class="external text" href="https://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/">the original</a> on 13 March 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.connectortips.com&rft.atitle=OCuLink+connectors+and+cables+support+new+PCIe+standard&rft_id=https%3A%2F%2Fwww.connectortips.com%2Foculink-connectors-cables-support-new-pcie-standard%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-6MiK5-52"><a href="#cite_ref-6MiK5_52-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMokosiy2020" class="citation web cs1">Mokosiy, Vitaliy (9 October 2020). <a rel="nofollow" class="external text" href="https://mokosiy.medium.com/untangling-terms-m-2-nvme-usb-c-sas-pcie-6599c044f38e">"Untangling terms: M.2, NVMe, USB-C, SAS, PCIe, U.2, OCuLink"</a>. Medium. Retrieved 26 March 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Medium&rft.atitle=Untangling+terms%3A+M.2%2C+NVMe%2C+USB-C%2C+SAS%2C+PCIe%2C+U.2%2C+OCuLink&rft.date=2020-10-09&rft.aulast=Mokosiy&rft.aufirst=Vitaliy&rft_id=https%3A%2F%2Fmokosiy.medium.com%2Funtangling-terms-m-2-nvme-usb-c-sas-pcie-6599c044f38e&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-tNP5L-53"><a href="#cite_ref-tNP5L_53-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.supermicro.com/products/nfo/uio.cfm">"Supermicro Universal I/O (UIO) Solutions"</a>. Supermicro.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140324184437/http://www.supermicro.com/products/nfo/uio.cfm">Archived</a> from the original on 24 March 2014. Retrieved 24 March 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Supermicro+Universal+I%2FO+%28UIO%29+Solutions&rft.pub=Supermicro.com&rft_id=http%3A%2F%2Fwww.supermicro.com%2Fproducts%2Fnfo%2Fuio.cfm&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-osiit-54"><a href="#cite_ref-osiit_54-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.edn.com/design/pc-board/4423319/Get-ready-for-M-PCIe-testing">"Get ready for M-PCIe testing"</a>, PC board design, EDN</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Get+ready+for+M-PCIe+testing&rft.btitle=PC+board+design&rft.pub=EDN&rft_id=http%3A%2F%2Fwww.edn.com%2Fdesign%2Fpc-board%2F4423319%2FGet-ready-for-M-PCIe-testing&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PoRghEr-55">^ <a href="#cite_ref-PoRghEr_55-0">a</a> <a href="#cite_ref-PoRghEr_55-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/">"PCI SIG discusses M-PCIe oculink & 4th gen PCIe"</a>, The Register, <a href="/wiki/United_Kingdom" title="United Kingdom">UK</a>, 13 September 2013, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170629201006/http://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/">archived</a> from the original on 29 June 2017</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Register&rft.atitle=PCI+SIG+discusses+M-PCIe+oculink+%26+4th+gen+PCIe&rft.date=2013-09-13&rft_id=https%3A%2F%2Fwww.theregister.co.uk%2FPrint%2F2013%2F09%2F13%2Fpci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-faq4-56"><a href="#cite_ref-faq4_56-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140518224913/http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3">"PCI Express 4.0 Frequently Asked Questions"</a>. pcisig.com. PCI-SIG. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3">the original</a> on 18 May 2014. Retrieved 18 May 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=PCI+Express+4.0+Frequently+Asked+Questions&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Ffaqs%2FFAQ_PCI_Express_4.0%2F%23EQ3&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-faq3-57">^ <a href="#cite_ref-faq3_57-0">a</a> <a href="#cite_ref-faq3_57-1">b</a> <a href="#cite_ref-faq3_57-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140201172536/http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2">"PCI Express 3.0 Frequently Asked Questions"</a>. pcisig.com. PCI-SIG. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2">the original</a> on 1 February 2014. Retrieved 1 May 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=PCI+Express+3.0+Frequently+Asked+Questions&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Ffaqs%2Fpcie3.0_faq%2F%23EQ2&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-HroAC-61"><a href="#cite_ref-HroAC_61-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.tmworld.com/electronics-news/4380071/What-does-GT-s-mean-anyway-">"What does GT/s mean, anyway?"</a>. TM World. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120814002641/http://www.tmworld.com/electronics-news/4380071/What-does-GT-s-mean-anyway-">Archived</a> from the original on 14 August 2012. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TM+World&rft.atitle=What+does+GT%2Fs+mean%2C+anyway%3F&rft_id=http%3A%2F%2Fwww.tmworld.com%2Felectronics-news%2F4380071%2FWhat-does-GT-s-mean-anyway-&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-tfQxK-62"><a href="#cite_ref-tfQxK_62-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100817201815/http://www.eiscat.se/groups/EISCAT_3D_info/DeliverableWP12.2/preview_popup">"Deliverable 12.2"</a>. <a href="/wiki/Sweden" title="Sweden">SE</a>: Eiscat. Archived from <a rel="nofollow" class="external text" href="http://www.eiscat.se/groups/EISCAT_3D_info/DeliverableWP12.2/preview_popup">the original</a> on 17 August 2010. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Deliverable+12.2&rft.place=SE&rft.pub=Eiscat&rft_id=http%3A%2F%2Fwww.eiscat.se%2Fgroups%2FEISCAT_3D_info%2FDeliverableWP12.2%2Fpreview_popup&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-n9qGs-63"><a href="#cite_ref-n9qGs_63-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.pcisig.com/">PCI SIG</a>, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080706134414/http://pcisig.com/">archived</a> from the original on 6 July 2008</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=PCI+SIG&rft_id=http%3A%2F%2Fwww.pcisig.com%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIExpressPressRelease-65"><a href="#cite_ref-PCIExpressPressRelease_65-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070304101327/http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf">"PCI Express Base 2.0 specification announced"</a> (PDF) (Press release). <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI-SIG</a>. 15 January 2007. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf">the original</a> (PDF) on 4 March 2007. Retrieved 9 February 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+Base+2.0+specification+announced&rft.pub=PCI-SIG&rft.date=2007-01-15&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2FPCIe2_0_Spec_Release_FINAL2.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> — note that in this press release the term aggregate bandwidth refers to the sum of incoming and outgoing bandwidth; using this terminology the aggregate bandwidth of full duplex 100BASE-TX is 200 Mbit/s. </li> <li id="cite_note-UaYlc-66"><a href="#cite_ref-UaYlc_66-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith2006" class="citation web cs1">Smith, Tony (11 October 2006). <a rel="nofollow" class="external text" href="http://www.reghardware.co.uk/2006/10/11/pic-sig_posts_pcie_2_final_draft/">"PCI Express 2.0 final draft spec published"</a>. The Register. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070129121731/http://www.reghardware.co.uk/2006/10/11/pic-sig_posts_pcie_2_final_draft/">Archived</a> from the original on 29 January 2007. Retrieved 9 February 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Register&rft.atitle=PCI+Express+2.0+final+draft+spec+published&rft.date=2006-10-11&rft.aulast=Smith&rft.aufirst=Tony&rft_id=http%3A%2F%2Fwww.reghardware.co.uk%2F2006%2F10%2F11%2Fpic-sig_posts_pcie_2_final_draft%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-wHHTf-67"><a href="#cite_ref-wHHTf_67-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKeyFink2007" class="citation news cs1">Key, Gary; Fink, Wesley (21 May 2007). <a rel="nofollow" class="external text" href="http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2993">"Intel P35: Intel's Mainstream Chipset Grows Up"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070523055011/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2993">Archived</a> from the original on 23 May 2007. Retrieved 21 May 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Intel+P35%3A+Intel%27s+Mainstream+Chipset+Grows+Up&rft.date=2007-05-21&rft.aulast=Key&rft.aufirst=Gary&rft.au=Fink%2C+Wesley&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fcpuchipsets%2Fshowdoc.aspx%3Fi%3D2993&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-gL2GQ-68"><a href="#cite_ref-gL2GQ_68-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHuynh2007" class="citation news cs1">Huynh, Anh (8 February 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070210200616/http://www.dailytech.com/article.aspx?newsid=6021">"NVIDIA "MCP72" Details Unveiled"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. Archived from <a rel="nofollow" class="external text" href="http://www.dailytech.com/article.aspx?newsid=6021">the original</a> on 10 February 2007. Retrieved 9 February 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=NVIDIA+%22MCP72%22+Details+Unveiled&rft.date=2007-02-08&rft.aulast=Huynh&rft.aufirst=Anh&rft_id=http%3A%2F%2Fwww.dailytech.com%2Farticle.aspx%3Fnewsid%3D6021&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-mUQKD-69"><a href="#cite_ref-mUQKD_69-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://download.intel.com/products/chipsets/P35/317304.pdf">"Intel P35 Express Chipset Product Brief"</a> (PDF). Intel. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070926150158/http://download.intel.com/products/chipsets/P35/317304.pdf">Archived</a> (PDF) from the original on 26 September 2007. Retrieved 5 September 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+P35+Express+Chipset+Product+Brief&rft.pub=Intel&rft_id=http%3A%2F%2Fdownload.intel.com%2Fproducts%2Fchipsets%2FP35%2F317304.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-cVjNG-70"><a href="#cite_ref-cVjNG_70-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHachman2009" class="citation web cs1">Hachman, Mark (5 August 2009). <a rel="nofollow" class="external text" href="https://www.pcmag.com/article2/0,2817,2351266,00.asp">"PCI Express 3.0 Spec Pushed Out to 2010"</a>. PC Mag. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140107192535/http://www.pcmag.com/article2/0,2817,2351266,00.asp">Archived</a> from the original on 7 January 2014. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+3.0+Spec+Pushed+Out+to+2010&rft.pub=PC+Mag&rft.date=2009-08-05&rft.aulast=Hachman&rft.aufirst=Mark&rft_id=https%3A%2F%2Fwww.pcmag.com%2Farticle2%2F0%2C2817%2C2351266%2C00.asp&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-extrmetech-71"><a href="#cite_ref-extrmetech_71-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://www.extremetech.com/article2/0,1697,2169018,00.asp">"PCI Express 3.0 Bandwidth: 8.0 Gigatransfers/s"</a>. ExtremeTech. 9 August 2007. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20071024140702/http://www.extremetech.com/article2/0,1697,2169018,00.asp">Archived</a> from the original on 24 October 2007. Retrieved 5 September 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=PCI+Express+3.0+Bandwidth%3A+8.0+Gigatransfers%2Fs&rft.date=2007-08-09&rft_id=http%3A%2F%2Fwww.extremetech.com%2Farticle2%2F0%2C1697%2C2169018%2C00.asp&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ajVA3-72"><a href="#cite_ref-ajVA3_72-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20101121001048/http://www.xbitlabs.com/news/other/display/20101118151837_PCI_Special_Interest_Group_Publishes_PCI_Express_3_0_Standard.html">"PCI Special Interest Group Publishes PCI Express 3.0 Standard"</a>. X bit labs. 18 November 2010. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/other/display/20101118151837_PCI_Special_Interest_Group_Publishes_PCI_Express_3_0_Standard.html">the original</a> on 21 November 2010. Retrieved 18 November 2010.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=PCI+Special+Interest+Group+Publishes+PCI+Express+3.0+Standard&rft.date=2010-11-18&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fother%2Fdisplay%2F20101118151837_PCI_Special_Interest_Group_Publishes_PCI_Express_3_0_Standard.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-5lvIH-73"><a href="#cite_ref-5lvIH_73-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.eteknix.com/pcie-3-1-and-4-0-specifications-revealed/">"PCIe 3.1 and 4.0 Specifications Revealed"</a>. eteknix.com. July 2013. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160201102133/http://www.eteknix.com/pcie-3-1-and-4-0-specifications-revealed/">Archived</a> from the original on 1 February 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=eteknix.com&rft.atitle=PCIe+3.1+and+4.0+Specifications+Revealed&rft.date=2013-07&rft_id=http%3A%2F%2Fwww.eteknix.com%2Fpcie-3-1-and-4-0-specifications-revealed%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-9EIkz-74"><a href="#cite_ref-9EIkz_74-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://blogs.synopsys.com/expressyourself/2014/11/12/trick-or-treat-pci-express-3-1-released/">"Trick or Treat… PCI Express 3.1 Released!"</a>. synopsys.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150323193106/https://blogs.synopsys.com/expressyourself/2014/11/12/trick-or-treat-pci-express-3-1-released/">Archived</a> from the original on 23 March 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=synopsys.com&rft.atitle=Trick+or+Treat%E2%80%A6+PCI+Express+3.1+Released%21&rft_id=http%3A%2F%2Fblogs.synopsys.com%2Fexpressyourself%2F2014%2F11%2F12%2Ftrick-or-treat-pci-express-3-1-released%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-W466M-75"><a href="#cite_ref-W466M_75-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20121223043627/http://www.pcisig.com/news_room/Press_Releases/November_29_2011_Press_Release_/">"PCI Express 4.0 evolution to 16 GT/s, twice the throughput of PCI Express 3.0 technology"</a> (press release). PCI-SIG. 29 November 2011. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/Press_Releases/November_29_2011_Press_Release_/">the original</a> on 23 December 2012. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+4.0+evolution+to+16+GT%2Fs%2C+twice+the+throughput+of+PCI+Express+3.0+technology&rft.pub=PCI-SIG&rft.date=2011-11-29&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2FPress_Releases%2FNovember_29_2011_Press_Release_%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-QNZsy-76"><a href="#cite_ref-QNZsy_76-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20161020040106/https://pcisig.com/faq?field_category_value%5B%5D=pci_express_4.0">"Frequently Asked Questions | PCI-SIG"</a>. pcisig.com. Archived from <a rel="nofollow" class="external text" href="https://pcisig.com/faq?field_category_value%5B%5D=pci_express_4.0#4415">the original</a> on 20 October 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=Frequently+Asked+Questions+%26%23124%3B+PCI-SIG&rft_id=https%3A%2F%2Fpcisig.com%2Ffaq%3Ffield_category_value%255B%255D%3Dpci_express_4.0%234415&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-EE_4+5-77"><a href="#cite_ref-EE_4+5_77-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation magazine cs1"><a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1330006">"PCIe 4.0 Heads to Fab, 5.0 to Lab"</a>. EE Times. 26 June 2016. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160828221858/http://www.eetimes.com/document.asp?doc_id=1330006">Archived</a> from the original on 28 August 2016. Retrieved 27 August 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EE+Times&rft.atitle=PCIe+4.0+Heads+to+Fab%2C+5.0+to+Lab&rft.date=2016-06-26&rft_id=http%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1330006&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-FZ4hQ-78"><a href="#cite_ref-FZ4hQ_78-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.mellanox.com/news/press_release/mellanox-announces-connectx-5-next-generation-100g-infiniband-and-ethernet-smart-interconnect">"Mellanox Announces ConnectX-5, the Next Generation of 100G InfiniBand and Ethernet Smart Interconnect Adapter | NVIDIA"</a>. www.mellanox.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.mellanox.com&rft.atitle=Mellanox+Announces+ConnectX-5%2C+the+Next+Generation+of+100G+InfiniBand+and+Ethernet+Smart+Interconnect+Adapter+%26%23124%3B+NVIDIA&rft_id=https%3A%2F%2Fwww.mellanox.com%2Fnews%2Fpress_release%2Fmellanox-announces-connectx-5-next-generation-100g-infiniband-and-ethernet-smart-interconnect&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-zovf4-79"><a href="#cite_ref-zovf4_79-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.mellanox.com/news/press_release/mellanox-announces-200gbs-hdr-infiniband-solutions-enabling-record-levels-performance-and">"Mellanox Announces 200Gb/s HDR InfiniBand Solutions Enabling Record Levels of Performance and Scalability | NVIDIA"</a>. www.mellanox.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.mellanox.com&rft.atitle=Mellanox+Announces+200Gb%2Fs+HDR+InfiniBand+Solutions+Enabling+Record+Levels+of+Performance+and+Scalability+%26%23124%3B+NVIDIA&rft_id=https%3A%2F%2Fwww.mellanox.com%2Fnews%2Fpress_release%2Fmellanox-announces-200gbs-hdr-infiniband-solutions-enabling-record-levels-performance-and&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-heise_idf_2016-80"><a href="#cite_ref-heise_idf_2016_80-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html">"IDF: PCIe 4.0 läuft, PCIe 5.0 in Arbeit"</a>. <a href="/wiki/Heise_Online" class="mw-redirect" title="Heise Online">Heise Online</a> (in German). 18 August 2016. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160819153631/http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html">Archived</a> from the original on 19 August 2016. Retrieved 18 August 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Heise+Online&rft.atitle=IDF%3A+PCIe+4.0+l%C3%A4uft%2C+PCIe+5.0+in+Arbeit&rft.date=2016-08-18&rft_id=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2FIDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-HC28-IBM-Power9-81"><a href="#cite_ref-HC28-IBM-Power9_81-0">^</a> <a rel="nofollow" class="external text" href="https://old.hotchips.org/wp-content/uploads/hc_archives/hc28/HC28.23-Tuesday-Epub/HC28.23.90-High-Perform-Epub/HC28.23.921-.POWER9-Thompto-IBM-final.pdf">Brian Thompto, POWER9 Processor for the Cognitive Era</a> </li> <li id="cite_note-IEEE-Power9-82"><a href="#cite_ref-IEEE-Power9_82-0">^</a> <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/xpl/conhome/7932734/proceeding">2016 IEEE Hot Chips 28 Symposium (HCS), 21–23 Aug. 2016</a> </li> <li id="cite_note-TR_pcie4-83">^ <a href="#cite_ref-TR_pcie4_83-0">a</a> <a href="#cite_ref-TR_pcie4_83-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBorn2017" class="citation news cs1">Born, Eric (8 June 2017). <a rel="nofollow" class="external text" href="https://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap">"PCIe 4.0 specification finally out with 16 GT/s on tap"</a>. Tech Report. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170608155216/http://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap">Archived</a> from the original on 8 June 2017. Retrieved 8 June 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=PCIe+4.0+specification+finally+out+with+16+GT%2Fs+on+tap&rft.date=2017-06-08&rft.aulast=Born&rft.aufirst=Eric&rft_id=https%3A%2F%2Ftechreport.com%2Fnews%2F32064%2Fpcie-4-0-specification-finally-out-with-16-gt-s-on-tap&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-2HOSh-84"><a href="#cite_ref-2HOSh_84-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20171208002632/http://www-03.ibm.com/press/us/en/pressrelease/53452.wss">"IBM Unveils Most Advanced Server for AI"</a>. www-03.ibm.com. 5 December 2017. Archived from <a rel="nofollow" class="external text" href="https://www-03.ibm.com/press/us/en/pressrelease/53452.wss">the original</a> on 8 December 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www-03.ibm.com&rft.atitle=IBM+Unveils+Most+Advanced+Server+for+AI&rft.date=2017-12-05&rft_id=https%3A%2F%2Fwww-03.ibm.com%2Fpress%2Fus%2Fen%2Fpressrelease%2F53452.wss&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-IBM-ZG17-0147-85"><a href="#cite_ref-IBM-ZG17-0147_85-0">^</a> <a rel="nofollow" class="external text" href="https://www.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/7/877/ENUSZG17-0147/index.html">IBM Power System AC922 (8335-GTG) server helps you to harness breakthrough accelerated AI, HPDA, and HPC performance for faster time to insight, IBM Europe Hardware Announcement ZG17-0147</a> </li> <li id="cite_note-ChNhD-86"><a href="#cite_ref-ChNhD_86-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20180929041113/https://www.netint.ca/blog/netint-introduces-codensity-with-support-for-pcie-4-0/">"NETINT Introduces Codensity with Support for PCIe 4.0 – NETINT Technologies"</a>. NETINT Technologies. 17 July 2018. Archived from <a rel="nofollow" class="external text" href="https://www.netint.ca/blog/netint-introduces-codensity-with-support-for-pcie-4-0/">the original</a> on 29 September 2018. Retrieved 28 September 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=NETINT+Technologies&rft.atitle=NETINT+Introduces+Codensity+with+Support+for+PCIe+4.0+%E2%80%93+NETINT+Technologies&rft.date=2018-07-17&rft_id=https%3A%2F%2Fwww.netint.ca%2Fblog%2Fnetint-introduces-codensity-with-support-for-pcie-4-0%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-Akskd-87"><a href="#cite_ref-Akskd_87-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMujtaba2019" class="citation web cs1">Mujtaba, Hassan (9 January 2019). <a rel="nofollow" class="external text" href="https://wccftech.com/amd-ryzen-3000-zen-2-desktop-am4-processors-launching-mid-2019/">"AMD Ryzen 3000 Series CPUs Based on Zen 2 Launching in Mid of 2019"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+3000+Series+CPUs+Based+on+Zen+2+Launching+in+Mid+of+2019&rft.date=2019-01-09&rft.aulast=Mujtaba&rft.aufirst=Hassan&rft_id=https%3A%2F%2Fwccftech.com%2Famd-ryzen-3000-zen-2-desktop-am4-processors-launching-mid-2019%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-KDBMK-88"><a href="#cite_ref-KDBMK_88-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2019" class="citation web cs1">Alcorn, Paul (3 June 2019). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/amd-pcie-4.0-socket-am4-motherboard,39559.html">"AMD Nixes PCIe 4.0 Support on Older Socket AM4 Motherboards, Here's Why"</a>. Tom's Hardware. <a rel="nofollow" class="external text" href="https://archive.today/20190610025155/https://www.tomshardware.com/news/amd-pcie-4.0-socket-am4-motherboard,39559.html">Archived</a> from the original on 10 June 2019. Retrieved 10 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=AMD+Nixes+PCIe+4.0+Support+on+Older+Socket+AM4+Motherboards%2C+Here%27s+Why&rft.date=2019-06-03&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Famd-pcie-4.0-socket-am4-motherboard%2C39559.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-CAY71-89"><a href="#cite_ref-CAY71_89-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2019" class="citation web cs1">Alcorn, Paul (10 January 2019). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/amd-ryzen-pcie-4.0-motherboard,38401.html">"PCIe 4.0 May Come to all AMD Socket AM4 Motherboards (Updated)"</a>. Tom's Hardware. <a rel="nofollow" class="external text" href="https://archive.today/20190610025353/https://www.tomshardware.com/news/amd-ryzen-pcie-4.0-motherboard,38401.html">Archived</a> from the original on 10 June 2019. Retrieved 10 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=PCIe+4.0+May+Come+to+all+AMD+Socket+AM4+Motherboards+%28Updated%29&rft.date=2019-01-10&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Famd-ryzen-pcie-4.0-motherboard%2C38401.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-C02lC-90"><a href="#cite_ref-C02lC_90-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2020" class="citation web cs1">Cutress, Dr. Ian (13 August 2020). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/15971/intels-11th-gen-core-tiger-lake-soc-detailed-superfin-willow-cove-and-xelp/5">"Tiger Lake IO and Power"</a>. Anandtech.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Anandtech&rft.atitle=Tiger+Lake+IO+and+Power&rft.date=2020-08-13&rft.aulast=Cutress&rft.aufirst=Dr.+Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F15971%2Fintels-11th-gen-core-tiger-lake-soc-detailed-superfin-willow-cove-and-xelp%2F5&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-Syn50-91"><a href="#cite_ref-Syn50_91-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://blogs.synopsys.com/expressyourself/2017/08/15/1-2-3-4-5-its-official-pcie-5-0-is-announced">"1,2,3,4,5... It's Official, PCIe 5.0 is Announced | synopsys.com"</a>. www.synopsys.com. Retrieved 7 June 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.synopsys.com&rft.atitle=1%2C2%2C3%2C4%2C5...+It%27s+Official%2C+PCIe+5.0+is+Announced+%7C+synopsys.com&rft_id=https%3A%2F%2Fblogs.synopsys.com%2Fexpressyourself%2F2017%2F08%2F15%2F1-2-3-4-5-its-official-pcie-5-0-is-announced&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-n6z9y-92"><a href="#cite_ref-n6z9y_92-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.plda.com/plda-announces-availability-xpressrich5tm-pcie-50-controller-ip">"PLDA Announces Availability of XpressRICH5™ PCIe 5.0 Controller IP | PLDA.com"</a>. www.plda.com. Retrieved 28 June 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.plda.com&rft.atitle=PLDA+Announces+Availability+of+XpressRICH5%E2%84%A2+PCIe+5.0+Controller+IP+%7C+PLDA.com&rft_id=https%3A%2F%2Fwww.plda.com%2Fplda-announces-availability-xpressrich5tm-pcie-50-controller-ip&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-9OVm8-93"><a href="#cite_ref-9OVm8_93-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.plda.com/products/pcie-solutions-asicsoc/pcie-controller-ip/pcie-soft-ip/pcie-40-soft-ip/xpressrich5-asic">"XpressRICH5 for ASIC | PLDA.com"</a>. www.plda.com. Retrieved 28 June 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.plda.com&rft.atitle=XpressRICH5+for+ASIC+%7C+PLDA.com&rft_id=https%3A%2F%2Fwww.plda.com%2Fproducts%2Fpcie-solutions-asicsoc%2Fpcie-controller-ip%2Fpcie-soft-ip%2Fpcie-40-soft-ip%2Fxpressrich5-asic&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIe5r09-94"><a href="#cite_ref-PCIe5r09_94-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://pcisig.com/doubling-bandwidth-under-two-years-pci-express®-base-specification-revision-50-version-09-now">"Doubling Bandwidth in Under Two Years: PCI Express® Base Specification Revision 5.0, Version 0.9 is Now Available to Members"</a>. pcisig.com. Retrieved 12 December 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=Doubling+Bandwidth+in+Under+Two+Years%3A+PCI+Express%C2%AE+Base+Specification+Revision+5.0%2C+Version+0.9+is+Now+Available+to+Members&rft_id=http%3A%2F%2Fpcisig.com%2Fdoubling-bandwidth-under-two-years-pci-express%C2%AE-base-specification-revision-50-version-09-now&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ETVqe-95"><a href="#cite_ref-ETVqe_95-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/pcie-4.0-5.0-pci-sig-specification,38460.html">"PCIe 5.0 Is Ready For Prime Time"</a>. tomshardware.com. 17 January 2019. Retrieved 18 January 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=tomshardware.com&rft.atitle=PCIe+5.0+Is+Ready+For+Prime+Time&rft.date=2019-01-17&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fpcie-4.0-5.0-pci-sig-specification%2C38460.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-MW69U-96"><a href="#cite_ref-MW69U_96-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.businesswire.com/news/home/20190529005766/en/PCI-SIG%C2%AE-Achieves-32GTs-with-New-PCI-Express%C2%AE-5.0-Specification">"PCI-SIG® Achieves 32GT/s with New PCI Express® 5.0 Specification"</a>. www.businesswire.com. 29 May 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.businesswire.com&rft.atitle=PCI-SIG%C2%AE+Achieves+32GT%2Fs+with+New+PCI+Express%C2%AE+5.0+Specification&rft.date=2019-05-29&rft_id=https%3A%2F%2Fwww.businesswire.com%2Fnews%2Fhome%2F20190529005766%2Fen%2FPCI-SIG%25C2%25AE-Achieves-32GTs-with-New-PCI-Express%25C2%25AE-5.0-Specification&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-yk5Nd-97"><a href="#cite_ref-yk5Nd_97-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pcgameshardware.de/Mainboard-Hardware-154107/News/PCI-Express50-China-stellt-ersten-Controller-vor-1337072/">"PCI-Express 5.0: China stellt ersten Controller vor"</a>. PC Games Hardware. 18 November 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=PC+Games+Hardware&rft.atitle=PCI-Express+5.0%3A+China+stellt+ersten+Controller+vor&rft.date=2019-11-18&rft_id=https%3A%2F%2Fwww.pcgameshardware.de%2FMainboard-Hardware-154107%2FNews%2FPCI-Express50-China-stellt-ersten-Controller-vor-1337072%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-98"><a href="#cite_ref-98">^</a> <a rel="nofollow" class="external text" href="https://hc32.hotchips.org/assets/program/conference/day1/HotChips2020_Server_Processors_IBM_Starke_POWER10_v33.pdf">IBM’s POWER10 Processor, Hot Chips 32, August 16–18, 2020</a> </li> <li id="cite_note-IBM-ENUSZG21-0059-99"><a href="#cite_ref-IBM-ENUSZG21-0059_99-0">^</a> <a rel="nofollow" class="external text" href="https://www.ibm.com/common/ssi/rep_ca/9/877/ENUSZG21-0059/index.html">Power E1080 Enterprise server delivers a uniquely architected platform to help securely and efficiently scale core operational and AI applications in a hybrid cloud, IBM Europe Hardware Announcement ZG21-0059</a> </li> <li id="cite_note-IBM-REDP-5649-00-100">^ <a href="#cite_ref-IBM-REDP-5649-00_100-0">a</a> <a href="#cite_ref-IBM-REDP-5649-00_100-1">b</a> <a rel="nofollow" class="external text" href="http://www.redbooks.ibm.com/redpapers/pdfs/redp5649.pdf">IBM Power E1080 Technical Overview and Introduction</a> </li> <li id="cite_note-101"><a href="#cite_ref-101">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/12th-gen-core-processors.html">"Intel Unveils 12th Gen Intel Core, Launches World's Best Gaming"</a>. Intel.com. Retrieved 16 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Unveils+12th+Gen+Intel+Core%2C+Launches+World%27s+Best+Gaming&rft.pub=Intel.com&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fnews%2F12th-gen-core-processors.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-102"><a href="#cite_ref-102">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://nvidianews.nvidia.com/news/nvidia-announces-hopper-architecture-the-next-generation-of-accelerated-computing">"NVIDIA Announces Hopper Architecture, the Next Generation of Accelerated Computing"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=NVIDIA+Announces+Hopper+Architecture%2C+the+Next+Generation+of+Accelerated+Computing&rft_id=https%3A%2F%2Fnvidianews.nvidia.com%2Fnews%2Fnvidia-announces-hopper-architecture-the-next-generation-of-accelerated-computing&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-103"><a href="#cite_ref-103">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/press-releases/2022-05-23-amd-showcases-growth-gaming-commercial-and-mainstream-mobile-and-industry">"AMD Showcases Industry-Leading Gaming, Commercial, and Mainstream PC Technologies at COMPUTEX 2022"</a>. AMD.com. Retrieved 23 May 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Showcases+Industry-Leading+Gaming%2C+Commercial%2C+and+Mainstream+PC+Technologies+at+COMPUTEX+2022&rft.pub=AMD.com&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fpress-releases%2F2022-05-23-amd-showcases-growth-gaming-commercial-and-mainstream-mobile-and-industry&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-104"><a href="#cite_ref-104">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/campaigns/epyc-9004-architecture">"4th Gen AMD EPYC™ Processor Architecture"</a>. AMD.com. Retrieved 12 November 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=4th+Gen+AMD+EPYC%E2%84%A2+Processor+Architecture&rft.pub=AMD.com&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fcampaigns%2Fepyc-9004-architecture&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-businesswire.com-105">^ <a href="#cite_ref-businesswire.com_105-0">a</a> <a href="#cite_ref-businesswire.com_105-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.businesswire.com/news/home/20190618005945/en/PCI-SIG%C2%AE-Announces-Upcoming-PCI-Express%C2%AE-6.0-Specification-to-Reach-64-GTs">"PCI-SIG® Announces Upcoming PCI Express® 6.0 Specification to Reach 64 GT/s"</a>. www.businesswire.com. 18 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.businesswire.com&rft.atitle=PCI-SIG%C2%AE+Announces+Upcoming+PCI+Express%C2%AE+6.0+Specification+to+Reach+64+GT%2Fs&rft.date=2019-06-18&rft_id=https%3A%2F%2Fwww.businesswire.com%2Fnews%2Fhome%2F20190618005945%2Fen%2FPCI-SIG%25C2%25AE-Announces-Upcoming-PCI-Express%25C2%25AE-6.0-Specification-to-Reach-64-GTs&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-O5gOe-106"><a href="#cite_ref-O5gOe_106-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith" class="citation web cs1">Smith, Ryan. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14559/pci-express-bandwidth-to-be-doubled-again-pcie-60-announced-spec-to-land-in-2021">"PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021"</a>. www.anandtech.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=PCI+Express+Bandwidth+to+Be+Doubled+Again%3A+PCIe+6.0+Announced%2C+Spec+to+Land+in+2021&rft.aulast=Smith&rft.aufirst=Ryan&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14559%2Fpci-express-bandwidth-to-be-doubled-again-pcie-60-announced-spec-to-land-in-2021&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-puGmx-107"><a href="#cite_ref-puGmx_107-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.phoronix.com/scan.php?page=news_item&px=PCI-Express-6.0-v0.5">"PCI Express 6.0 Reaches Version 0.5 Ahead Of Finalization Next Year – Phoronix"</a>. www.phoronix.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.phoronix.com&rft.atitle=PCI+Express+6.0+Reaches+Version+0.5+Ahead+Of+Finalization+Next+Year+%E2%80%93+Phoronix&rft_id=https%3A%2F%2Fwww.phoronix.com%2Fscan.php%3Fpage%3Dnews_item%26px%3DPCI-Express-6.0-v0.5&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ltCSi-108"><a href="#cite_ref-ltCSi_108-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShilov2020" class="citation web cs1">Shilov, Anton (4 November 2020). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/pcie-6-specification-hits-milestone-complete-draft-is-ready">"PCIe 6.0 Specification Hits Milestone: Complete Draft Is Ready"</a>. Tom's Hardware.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=PCIe+6.0+Specification+Hits+Milestone%3A+Complete+Draft+Is+Ready&rft.date=2020-11-04&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fpcie-6-specification-hits-milestone-complete-draft-is-ready&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-60r9-109"><a href="#cite_ref-60r9_109-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYanes" class="citation web cs1">Yanes, Al. <a rel="nofollow" class="external text" href="https://pcisig.com/blog/pcie®-60-specification-version-09-one-step-closer-final-release">"PCIe® 6.0 Specification, Version 0.9: One Step Closer to Final Release | PCI-SIG"</a>. pcisig.com. Retrieved 6 October 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=PCIe%C2%AE+6.0+Specification%2C+Version+0.9%3A+One+Step+Closer+to+Final+Release+%7C+PCI-SIG&rft.aulast=Yanes&rft.aufirst=Al&rft_id=https%3A%2F%2Fpcisig.com%2Fblog%2Fpcie%C2%AE-60-specification-version-09-one-step-closer-final-release&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-110"><a href="#cite_ref-110">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.businesswire.com/news/home/20220111005011/en/PCI-SIG%C2%AE-Releases-PCIe%C2%AE-6.0-Specification-Delivering-Record-Performance-to-Power-Big-Data-Applications">"PCI-SIG® Releases PCIe® 6.0 Specification Delivering Record Performance to Power Big Data Applications"</a>. Business Wire. 11 January 2022. Retrieved 16 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI-SIG%C2%AE+Releases+PCIe%C2%AE+6.0+Specification+Delivering+Record+Performance+to+Power+Big+Data+Applications&rft.pub=Business+Wire&rft.date=2022-01-11&rft_id=https%3A%2F%2Fwww.businesswire.com%2Fnews%2Fhome%2F20220111005011%2Fen%2FPCI-SIG%25C2%25AE-Releases-PCIe%25C2%25AE-6.0-Specification-Delivering-Record-Performance-to-Power-Big-Data-Applications&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-111"><a href="#cite_ref-111">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing">"NVIDIA Blackwell Platform Arrives to Power a New Era of Computing"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=NVIDIA+Blackwell+Platform+Arrives+to+Power+a+New+Era+of+Computing&rft_id=https%3A%2F%2Fnvidianews.nvidia.com%2Fnews%2Fnvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-pcie6_evolution_blog-112"><a href="#cite_ref-pcie6_evolution_blog_112-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://pcisig.com/blog/evolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong">"The Evolution of the PCI Express Specification: On its Sixth Generation, Third Decade and Still Going Strong"</a>. Pci-Sig. 11 January 2022. Retrieved 16 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+Evolution+of+the+PCI+Express+Specification%3A+On+its+Sixth+Generation%2C+Third+Decade+and+Still+Going+Strong&rft.pub=Pci-Sig&rft.date=2022-01-11&rft_id=https%3A%2F%2Fpcisig.com%2Fblog%2Fevolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIe6_fut-113"><a href="#cite_ref-PCIe6_fut_113-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDebendra_Das_Sharma2020" class="citation web cs1">Debendra Das Sharma (8 June 2020). <a rel="nofollow" class="external text" href="https://ghostarchive.org/varchive/youtube/20211030/jhehXwnu0Ss">"PCIe 6.0 Specification: The Interconnect for I/O Needs of the Future"</a>. PCI-SIG. p. 8. Archived from <a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=jhehXwnu0Ss">the original</a> on 30 October 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCIe+6.0+Specification%3A+The+Interconnect+for+I%2FO+Needs+of+the+Future&rft.pages=8&rft.pub=PCI-SIG&rft.date=2020-06-08&rft.au=Debendra+Das+Sharma&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3DjhehXwnu0Ss&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-cadence_pice6-114"><a href="#cite_ref-cadence_pice6_114-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/design-ip/pushing-the-envelope-with-pcie-6-wp.pdf">"Pushing the Envelope with PCIe 6.0: Bringing PAM4 to PCIe"</a> (PDF). Retrieved 16 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Pushing+the+Envelope+with+PCIe+6.0%3A+Bringing+PAM4+to+PCIe&rft_id=https%3A%2F%2Fwww.cadence.com%2Fcontent%2Fdam%2Fcadence-www%2Fglobal%2Fen_US%2Fdocuments%2Ftools%2Fip%2Fdesign-ip%2Fpushing-the-envelope-with-pcie-6-wp.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-pcie6_webinar-115"><a href="#cite_ref-pcie6_webinar_115-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf">"PowerPoint Presentation"</a> (PDF). Retrieved 16 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PowerPoint+Presentation&rft_id=https%3A%2F%2Fpcisig.com%2Fsites%2Fdefault%2Ffiles%2Ffiles%2FPCIe%25206.0%2520Webinar_Final_.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-116"><a href="#cite_ref-116">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.businesswire.com/news/home/20220621005137/en">"PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s"</a>. Business Wire. 21 June 2022. Retrieved 25 June 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI-SIG%C2%AE+Announces+PCI+Express%C2%AE+7.0+Specification+to+Reach+128+GT%2Fs&rft.pub=Business+Wire&rft.date=2022-06-21&rft_id=https%3A%2F%2Fwww.businesswire.com%2Fnews%2Fhome%2F20220621005137%2Fen&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIe70v05-117"><a href="#cite_ref-PCIe70v05_117-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://pcisig.com/blog/pcie%C2%AE-70-specification-version-05-now-available-full-draft-available-members">"PCIe® 7.0 Specification, Version 0.5 Now Available: Full Draft Available to Members"</a>. pcisig.com. Retrieved 3 April 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=PCIe%C2%AE+7.0+Specification%2C+Version+0.5+Now+Available%3A+Full+Draft+Available+to+Members&rft_id=https%3A%2F%2Fpcisig.com%2Fblog%2Fpcie%25C2%25AE-70-specification-version-05-now-available-full-draft-available-members&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIeFiber-118"><a href="#cite_ref-PCIeFiber_118-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cablinginstall.com/index/display/article-display/8876181966/articles/cabling-installation-maintenance/news/data-center/2011/6/plx-demo_shows_pcie.html">"PLX demo shows PCIe over fiber as data center clustering interconnect"</a>. Cabling install. Penn Well. Retrieved 29 August 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Cabling+install&rft.atitle=PLX+demo+shows+PCIe+over+fiber+as+data+center+clustering+interconnect&rft_id=http%3A%2F%2Fwww.cablinginstall.com%2Findex%2Fdisplay%2Farticle-display%2F8876181966%2Farticles%2Fcabling-installation-maintenance%2Fnews%2Fdata-center%2F2011%2F6%2Fplx-demo_shows_pcie.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-adnacoPCIe-119"><a href="#cite_ref-adnacoPCIe_119-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.adnaco.com/2011/09/03/new1">"Introduced second generation PCI Express Gen 2 over fiber optic systems"</a>. Adnaco. 22 April 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121004094357/http://www.adnaco.com/2011/09/03/new1/">Archived</a> from the original on 4 October 2012. Retrieved 29 August 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Introduced+second+generation+PCI+Express+Gen+2+over+fiber+optic+systems&rft.pub=Adnaco&rft.date=2011-04-22&rft_id=http%3A%2F%2Fwww.adnaco.com%2F2011%2F09%2F03%2Fnew1&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-g6np3-120"><a href="#cite_ref-g6np3_120-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.samtec.com/cable-systems/active-optics/active-optical-cable/pcie.aspx">"PCIe Active Optical Cable System"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20141230122105/http://www.samtec.com/cable-systems/active-optics/active-optical-cable/pcie.aspx">Archived</a> from the original on 30 December 2014. Retrieved 23 October 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCIe+Active+Optical+Cable+System&rft_id=http%3A%2F%2Fwww.samtec.com%2Fcable-systems%2Factive-optics%2Factive-optical-cable%2Fpcie.aspx&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-IBM-REDP-5137-00-121"><a href="#cite_ref-IBM-REDP-5137-00_121-0">^</a> <a rel="nofollow" class="external text" href="http://www.redbooks.ibm.com/redpapers/pdfs/redp5137.pdf">IBM Power Systems E870 and E880 Technical Overview and Introduction</a> </li> <li id="cite_note-kZCuH-122"><a href="#cite_ref-kZCuH_122-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation magazine cs1"><a rel="nofollow" class="external text" href="https://www.pcworld.com/article/240013/acer_asus_to_bring_intels_thunderbolt_speed_technology_to_windows_pcs.html">"Acer, Asus to Bring Intel's Thunderbolt Speed Technology to Windows PCs"</a>. PC World. 14 September 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120118190546/http://www.pcworld.com/article/240013/acer_asus_to_bring_intels_thunderbolt_speed_technology_to_windows_pcs.html">Archived</a> from the original on 18 January 2012. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=PC+World&rft.atitle=Acer%2C+Asus+to+Bring+Intel%27s+Thunderbolt+Speed+Technology+to+Windows+PCs&rft.date=2011-09-14&rft_id=https%3A%2F%2Fwww.pcworld.com%2Farticle%2F240013%2Facer_asus_to_bring_intels_thunderbolt_speed_technology_to_windows_pcs.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-RKmF2-123"><a href="#cite_ref-RKmF2_123-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKevin_Parrish2013" class="citation web cs1">Kevin Parrish (28 June 2013). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/M-PCIe-M.2-PCIe-3.1-PCIe-4.0-OCuLink,23259.html">"PCIe for Mobile Launched; PCIe 3.1, 4.0 Specs Revealed"</a>. Tom's Hardware. Retrieved 10 July 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=PCIe+for+Mobile+Launched%3B+PCIe+3.1%2C+4.0+Specs+Revealed&rft.date=2013-06-28&rft.au=Kevin+Parrish&rft_id=http%3A%2F%2Fwww.tomshardware.com%2Fnews%2FM-PCIe-M.2-PCIe-3.1-PCIe-4.0-OCuLink%2C23259.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-yT5P8-124"><a href="#cite_ref-yT5P8_124-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.chipestimate.com/PCI-Express-40-Draft-07-and-PIPE-44-Specifications-What-Do-They-Mean-to-Designers/Synopsys/Technical-Article/2017/02/21">"PCI Express 4.0 Draft 0.7 & PIPE 4.4 Specifications – What Do They Mean to Designers? — Synopsys Technical Article | ChipEstimate.com"</a>. www.chipestimate.com. Retrieved 28 June 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.chipestimate.com&rft.atitle=PCI+Express+4.0+Draft+0.7+%26+PIPE+4.4+Specifications+%E2%80%93+What+Do+They+Mean+to+Designers%3F+%E2%80%94+Synopsys+Technical+Article+%7C+ChipEstimate.com&rft_id=https%3A%2F%2Fwww.chipestimate.com%2FPCI-Express-40-Draft-07-and-PIPE-44-Specifications-What-Do-They-Mean-to-Designers%2FSynopsys%2FTechnical-Article%2F2017%2F02%2F21&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-9tQ3g-125"><a href="#cite_ref-9tQ3g_125-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://pinouts.ru/Slots/pci_express_pinout.shtml">"PCI Express 1x, 4x, 8x, 16x bus pinout and wiring @"</a>. <a href="/wiki/Russia" title="Russia">RU</a>: Pinouts. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20091125025800/http://pinouts.ru/Slots/pci_express_pinout.shtml">Archived</a> from the original on 25 November 2009. Retrieved 7 December 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI+Express+1x%2C+4x%2C+8x%2C+16x+bus+pinout+and+wiring+%40&rft.place=RU&rft.pub=Pinouts&rft_id=http%3A%2F%2Fpinouts.ru%2FSlots%2Fpci_express_pinout.shtml&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-pipe_spec-126"><a href="#cite_ref-pipe_spec_126-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080317171752/http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf">"PHY Interface for the PCI Express Architecture"</a> (PDF) (version 2.00 ed.). Intel. Archived from <a rel="nofollow" class="external text" href="http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf">the original</a> (PDF) on 17 March 2008. Retrieved 21 May 2008.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PHY+Interface+for+the+PCI+Express+Architecture&rft.edition=version+2.00&rft.pub=Intel&rft_id=http%3A%2F%2Fdownload.intel.com%2Ftechnology%2Fpciexpress%2Fdevnet%2Fdocs%2Fpipe2_00.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PCIe-System-Architecture-127"><a href="#cite_ref-PCIe-System-Architecture_127-0">^</a> <a rel="nofollow" class="external text" href="https://www.mindshare.com/files/ebooks/PCI%20Express%20System%20Architecture.pdf">PCI Express System Architecture</a> </li> <li id="cite_note-Intel-PCIe-128"><a href="#cite_ref-Intel-PCIe_128-0">^</a> <a rel="nofollow" class="external text" href="https://www.intel.ru/content/www/ru/ru/io/pci-express/pci-express-architecture-general.html">PCI Express Architecture, intel.com</a> </li> <li id="cite_note-pcie_schematics1-129"><a href="#cite_ref-pcie_schematics1_129-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.interfacebus.com/PCI-Express-Bus-PCIe-Description.html#d">"Mechanical Drawing for PCI Express Connector"</a>. Interface bus. Retrieved 7 December 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Mechanical+Drawing+for+PCI+Express+Connector&rft.pub=Interface+bus&rft_id=http%3A%2F%2Fwww.interfacebus.com%2FPCI-Express-Bus-PCIe-Description.html%23d&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-pcie_schematics2-130"><a href="#cite_ref-pcie_schematics2_130-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://portal.fciconnect.com/Comergent/fci/drawing/10018783.pdf">"FCi schematic for PCIe connectors"</a> (PDF). FCI connect. Retrieved 7 December 2007.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=FCi+schematic+for+PCIe+connectors&rft.pub=FCI+connect&rft_id=http%3A%2F%2Fportal.fciconnect.com%2FComergent%2Ffci%2Fdrawing%2F10018783.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-vV4Hv-131"><a href="#cite_ref-vV4Hv_131-0">^</a> <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf">Reducing Interrupt Latency Through the Use of Message Signaled Interrupts</a> </li> <li id="cite_note-iPAaS-132"><a href="#cite_ref-iPAaS_132-0">^</a> PCI Express Base Specification, Revision 3.0 Table 4-24 </li> <li id="cite_note-133"><a href="#cite_ref-133">^</a> <a rel="nofollow" class="external free" href="https://ww1.microchip.com/downloads/aemDocuments/documents/TCG/ProductDocuments/Brochures/00003818.pdf">https://ww1.microchip.com/downloads/aemDocuments/documents/TCG/ProductDocuments/Brochures/00003818.pdf</a> </li> <li id="cite_note-134"><a href="#cite_ref-134">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=ZjyrAgAAQBAJ&dq=pcie+dual+simplex&pg=PA69">IBM Power 770 and 780 Technical Overview and Introduction</a>. IBM Redbooks. 6 June 2013. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7384-5121-3" title="Special:BookSources/978-0-7384-5121-3"><bdi>978-0-7384-5121-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+Power+770+and+780+Technical+Overview+and+Introduction&rft.pub=IBM+Redbooks&rft.date=2013-06-06&rft.isbn=978-0-7384-5121-3&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DZjyrAgAAQBAJ%26dq%3Dpcie%2Bdual%2Bsimplex%26pg%3DPA69&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-135"><a href="#cite_ref-135">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=k_HJCgAAQBAJ&dq=pcie+differential+pair&pg=PT128">CompTIA A+ Exam Cram (Exams 220-602, 220-603, 220-604)</a>. Pearson Education. 19 July 2007. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7686-9003-3" title="Special:BookSources/978-0-7686-9003-3"><bdi>978-0-7686-9003-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=CompTIA+A%2B+Exam+Cram+%28Exams+220-602%2C+220-603%2C+220-604%29&rft.pub=Pearson+Education&rft.date=2007-07-19&rft.isbn=978-0-7686-9003-3&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dk_HJCgAAQBAJ%26dq%3Dpcie%2Bdifferential%2Bpair%26pg%3DPT128&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-traffic_profile-136"><a href="#cite_ref-traffic_profile_136-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=Xp7-NKsJ8_sC&dq=frequent+enforced+acknowledgements/&pg=PA35">Computer Peripherals And Interfaces</a>. Technical Publications Pune. 2008. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9788184313086" title="Special:BookSources/9788184313086"><bdi>9788184313086</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140225203956/http://www.google.com/books?id=Xp7-NKsJ8_sC&pg=PA35&dq=frequent+enforced+acknowledgements%2F">Archived</a> from the original on 25 February 2014. Retrieved 23 July 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Peripherals+And+Interfaces&rft.pub=Technical+Publications+Pune&rft.date=2008&rft.isbn=9788184313086&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DXp7-NKsJ8_sC%26dq%3Dfrequent%2Benforced%2Backnowledgements%2F%26pg%3DPA35&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-Xilinx-137">^ <a href="#cite_ref-Xilinx_137-0">a</a> <a href="#cite_ref-Xilinx_137-1">b</a> <a href="#cite_ref-Xilinx_137-2">c</a> <a href="#cite_ref-Xilinx_137-3">d</a> <a href="#cite_ref-Xilinx_137-4">e</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLawley2014" class="citation web cs1">Lawley, Jason (28 October 2014). <a rel="nofollow" class="external text" href="https://www.xilinx.com/support/documentation/white_papers/wp350.pdf">"Understanding Performance of PCI Express Systems"</a> (PDF). 1.2. Xilinx.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Understanding+Performance+of+PCI+Express+Systems&rft.series=1.2&rft.pub=Xilinx&rft.date=2014-10-28&rft.aulast=Lawley&rft.aufirst=Jason&rft_id=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fwhite_papers%2Fwp350.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-gxHZT-138"><a href="#cite_ref-gxHZT_138-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.nvidia.com/object/IO_34527.html">"NVIDIA Introduces NVIDIA Quadro® Plex – A Quantum Leap in Visual Computing"</a>. Nvidia. 1 August 2006. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060824225752/http://www.nvidia.com/object/IO_34527.html">Archived</a> from the original on 24 August 2006. Retrieved 14 July 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Nvidia&rft.atitle=NVIDIA+Introduces+NVIDIA+Quadro%C2%AE+Plex+%E2%80%93+A+Quantum+Leap+in+Visual+Computing&rft.date=2006-08-01&rft_id=http%3A%2F%2Fwww.nvidia.com%2Fobject%2FIO_34527.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-zJYg8-139"><a href="#cite_ref-zJYg8_139-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.nvidia.com/page/quadroplex.html">"Quadro Plex VCS – Advanced visualization and remote graphics"</a>. nVidia. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110428042937/http://www.nvidia.com/page/quadroplex.html">Archived</a> from the original on 28 April 2011. Retrieved 11 September 2010.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Quadro+Plex+VCS+%E2%80%93+Advanced+visualization+and+remote+graphics&rft.pub=nVidia&rft_id=http%3A%2F%2Fwww.nvidia.com%2Fpage%2Fquadroplex.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-HgxXj-140"><a href="#cite_ref-HgxXj_140-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100129170434/http://ati.amd.com/technology/xgp/">"XGP"</a>. ATI. AMD. Archived from <a rel="nofollow" class="external text" href="http://ati.amd.com/technology/xgp/">the original</a> on 29 January 2010. Retrieved 11 September 2010.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ATI&rft.atitle=XGP&rft_id=http%3A%2F%2Fati.amd.com%2Ftechnology%2Fxgp%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-WHU07-141"><a href="#cite_ref-WHU07_141-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.ubergizmo.com/2008/12/fujitsu-siemens-amilo-graphicbooster-external-laptop-gpu-released/">Fujitsu-Siemens Amilo GraphicBooster External Laptop GPU Released</a>, 3 December 2008, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20151016192734/http://www.ubergizmo.com/2008/12/fujitsu-siemens-amilo-graphicbooster-external-laptop-gpu-released/">archived</a> from the original on 16 October 2015, retrieved 9 August 2015</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Fujitsu-Siemens+Amilo+GraphicBooster+External+Laptop+GPU+Released&rft.date=2008-12-03&rft_id=http%3A%2F%2Fwww.ubergizmo.com%2F2008%2F12%2Ffujitsu-siemens-amilo-graphicbooster-external-laptop-gpu-released%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-mvR09-142"><a href="#cite_ref-mvR09_142-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.ubergizmo.com/2010/08/dynavivid-graphics-dock-from-acer-arrives-in-france-what-about-the-us/">DynaVivid Graphics Dock from Acer arrives in France, what about the US?</a>, 11 August 2010, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20151016192734/http://www.ubergizmo.com/2010/08/dynavivid-graphics-dock-from-acer-arrives-in-france-what-about-the-us/">archived</a> from the original on 16 October 2015, retrieved 9 August 2015</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=DynaVivid+Graphics+Dock+from+Acer+arrives+in+France%2C+what+about+the+US%3F&rft.date=2010-08-11&rft_id=http%3A%2F%2Fwww.ubergizmo.com%2F2010%2F08%2Fdynavivid-graphics-dock-from-acer-arrives-in-france-what-about-the-us%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ZAJ0y-143"><a href="#cite_ref-ZAJ0y_143-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDougherty2010" class="citation cs2">Dougherty, Steve (22 May 2010), <a rel="nofollow" class="external text" href="https://www.tweaktown.com/news/15382/msi_to_showcase_gus_external_graphics_solution_for_laptops_at_computex/">"MSI to showcase 'GUS' external graphics solution for laptops at Computex"</a>, TweakTown</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=TweakTown&rft.atitle=MSI+to+showcase+%27GUS%27+external+graphics+solution+for+laptops+at+Computex&rft.date=2010-05-22&rft.aulast=Dougherty&rft.aufirst=Steve&rft_id=http%3A%2F%2Fwww.tweaktown.com%2Fnews%2F15382%2Fmsi_to_showcase_gus_external_graphics_solution_for_laptops_at_computex%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-J5UtH-144"><a href="#cite_ref-J5UtH_144-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHellstrom2011" class="citation cs2">Hellstrom, Jerry (9 August 2011), <a rel="nofollow" class="external text" href="http://www.pcper.com/news/Editorial/ExpressCard-trying-pull-not-so-fast-one">"ExpressCard trying to pull a (not so) fast one?"</a>, PC Perspective (editorial), <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160201160254/http://www.pcper.com/news/Editorial/ExpressCard-trying-pull-not-so-fast-one">archived</a> from the original on 1 February 2016</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=PC+Perspective&rft.atitle=ExpressCard+trying+to+pull+a+%28not+so%29+fast+one%3F&rft.date=2011-08-09&rft.aulast=Hellstrom&rft.aufirst=Jerry&rft_id=http%3A%2F%2Fwww.pcper.com%2Fnews%2FEditorial%2FExpressCard-trying-pull-not-so-fast-one&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-jWWJt-145"><a href="#cite_ref-jWWJt_145-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.hwtools.net/Adapter/PE4H%20V3.2.html">"PE4H V3.2 (PCIe x16 Adapter)"</a>. Hwtools.net. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140214012341/http://www.hwtools.net/Adapter/PE4H%20V3.2.html">Archived</a> from the original on 14 February 2014. Retrieved 5 February 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PE4H+V3.2+%28PCIe+x16+Adapter%29&rft.pub=Hwtools.net&rft_id=http%3A%2F%2Fwww.hwtools.net%2FAdapter%2FPE4H%2520V3.2.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ERk1e-146"><a href="#cite_ref-ERk1e_146-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFO'Brien2010" class="citation cs2">O'Brien, Kevin (8 September 2010), <a rel="nofollow" class="external text" href="http://www.notebookreview.com/default.asp?newsID=5846&review=how+to+upgrade+laptop+graphics+notebook">"How to Upgrade Your Notebook Graphics Card Using DIY ViDOCK"</a>, Notebook review, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131213054647/http://www.notebookreview.com/default.asp?newsID=5846&review=how+to+upgrade+laptop+graphics+notebook">archived</a> from the original on 13 December 2013</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Notebook+review&rft.atitle=How+to+Upgrade+Your+Notebook+Graphics+Card+Using+DIY+ViDOCK&rft.date=2010-09-08&rft.aulast=O%27Brien&rft.aufirst=Kevin&rft_id=http%3A%2F%2Fwww.notebookreview.com%2Fdefault.asp%3FnewsID%3D5846%26review%3Dhow%2Bto%2Bupgrade%2Blaptop%2Bgraphics%2Bnotebook&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-CvJwZ-147"><a href="#cite_ref-CvJwZ_147-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLal_Shimpi2011" class="citation cs2">Lal Shimpi, Anand (7 September 2011), <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4743/the-thunderbolt-devices-trickle-in-magmas-expressbox-3t">"The Thunderbolt Devices Trickle In: Magma's ExpressBox 3T"</a>, AnandTech, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304201352/http://www.anandtech.com/show/4743/the-thunderbolt-devices-trickle-in-magmas-expressbox-3t">archived</a> from the original on 4 March 2016</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=AnandTech&rft.atitle=The+Thunderbolt+Devices+Trickle+In%3A+Magma%27s+ExpressBox+3T&rft.date=2011-09-07&rft.aulast=Lal+Shimpi&rft.aufirst=Anand&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fshow%2F4743%2Fthe-thunderbolt-devices-trickle-in-magmas-expressbox-3t&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-OLzu7-148"><a href="#cite_ref-OLzu7_148-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.theverge.com/2012/1/10/2698168/msi-GUS-II-external-thunderbolt-gpu-enclosure">"MSI GUS II external GPU enclosure with Thunderbolt"</a>. The Verge (hands-on). 10 January 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120213123659/http://www.theverge.com/2012/1/10/2698168/msi-GUS-II-external-thunderbolt-gpu-enclosure">Archived</a> from the original on 13 February 2012. Retrieved 12 February 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Verge&rft.atitle=MSI+GUS+II+external+GPU+enclosure+with+Thunderbolt&rft.date=2012-01-10&rft_id=https%3A%2F%2Fwww.theverge.com%2F2012%2F1%2F10%2F2698168%2Fmsi-GUS-II-external-thunderbolt-gpu-enclosure&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-5LOrR-149"><a href="#cite_ref-5LOrR_149-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/pci-express-graphics-thunderbolt,3263-2.html">"PCI express graphics, Thunderbolt"</a>, Tom’s hardware, 17 September 2012</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%E2%80%99s+hardware&rft.atitle=PCI+express+graphics%2C+Thunderbolt&rft.date=2012-09-17&rft_id=http%3A%2F%2Fwww.tomshardware.com%2Freviews%2Fpci-express-graphics-thunderbolt%2C3263-2.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-apXPa-150"><a href="#cite_ref-apXPa_150-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.engadget.com/2012/12/13/mlogics-mlink-thunderbolt-chassis-now-shipping-399/">"M logics M link Thunderbold chassis no shipping"</a>, Engadget, 13 December 2012, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170625182008/https://www.engadget.com/2012/12/13/mlogics-mlink-thunderbolt-chassis-now-shipping-399/">archived</a> from the original on 25 June 2017</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Engadget&rft.atitle=M+logics+M+link+Thunderbold+chassis+no+shipping&rft.date=2012-12-13&rft_id=https%3A%2F%2Fwww.engadget.com%2F2012%2F12%2F13%2Fmlogics-mlink-thunderbolt-chassis-now-shipping-399%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-PXbHS-151"><a href="#cite_ref-PXbHS_151-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBurns2017" class="citation cs2">Burns, Chris (17 October 2017), <a rel="nofollow" class="external text" href="https://www.slashgear.com/2017-razer-blade-stealth-and-core-v2-detailed-17504328/">"2017 Razer Blade Stealth and Core V2 detailed"</a>, SlashGear, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171017211631/https://www.slashgear.com/2017-razer-blade-stealth-and-core-v2-detailed-17504328/">archived</a> from the original on 17 October 2017</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=SlashGear&rft.atitle=2017+Razer+Blade+Stealth+and+Core+V2+detailed&rft.date=2017-10-17&rft.aulast=Burns&rft.aufirst=Chris&rft_id=https%3A%2F%2Fwww.slashgear.com%2F2017-razer-blade-stealth-and-core-v2-detailed-17504328%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-49Gx4-152"><a href="#cite_ref-49Gx4_152-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.engadget.com/2011/12/08/compactflash-association-readies-next-gen-xqd-format-promises-w/">"CompactFlash Association readies next-gen XQD format, promises write speeds of 125 MB/s and up"</a>. Engadget. 8 December 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140519002107/http://www.engadget.com/2011/12/08/compactflash-association-readies-next-gen-xqd-format-promises-w/">Archived</a> from the original on 19 May 2014. Retrieved 18 May 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CompactFlash+Association+readies+next-gen+XQD+format%2C+promises+write+speeds+of+125+MB%2Fs+and+up&rft.pub=Engadget&rft.date=2011-12-08&rft_id=https%3A%2F%2Fwww.engadget.com%2F2011%2F12%2F08%2Fcompactflash-association-readies-next-gen-xqd-format-promises-w%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-P3Feb-153"><a href="#cite_ref-P3Feb_153-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZsolt_Kerekes2011" class="citation web cs1">Zsolt Kerekes (December 2011). <a rel="nofollow" class="external text" href="http://www.storagesearch.com/ssd-29.html">"What's so very different about the design of Fusion-io's ioDrives / PCIe SSDs?"</a>. storagesearch.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130923065816/http://www.storagesearch.com/ssd-29.html">Archived</a> from the original on 23 September 2013. Retrieved 2 October 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=What%27s+so+very+different+about+the+design+of+Fusion-io%27s+ioDrives+%2F+PCIe+SSDs%3F&rft.pub=storagesearch.com&rft.date=2011-12&rft.au=Zsolt+Kerekes&rft_id=http%3A%2F%2Fwww.storagesearch.com%2Fssd-29.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-NeWKh-154"><a href="#cite_ref-NeWKh_154-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131004230049/http://www.storagereview.com/fusionio_iodrive_duo_enterprise_pcie_review">"Fusion-io ioDrive Duo Enterprise PCIe Review"</a>. storagereview.com. 16 July 2012. Archived from <a rel="nofollow" class="external text" href="http://www.storagereview.com/fusionio_iodrive_duo_enterprise_pcie_review">the original</a> on 4 October 2013. Retrieved 2 October 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Fusion-io+ioDrive+Duo+Enterprise+PCIe+Review&rft.pub=storagereview.com&rft.date=2012-07-16&rft_id=http%3A%2F%2Fwww.storagereview.com%2Ffusionio_iodrive_duo_enterprise_pcie_review&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-VLf63-155"><a href="#cite_ref-VLf63_155-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130325121004/http://www.xbitlabs.com/news/storage/display/20120110180208_OCZ_Demos_4TB_16TB_Solid_State_Drives_for_Enterprise.html">"OCZ Demos 4 TiB, 16 TiB Solid-State Drives for Enterprise"</a>. X-bit labs. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/storage/display/20120110180208_OCZ_Demos_4TB_16TB_Solid_State_Drives_for_Enterprise.html">the original</a> on 25 March 2013. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=OCZ+Demos+4+TiB%2C+16+TiB+Solid-State+Drives+for+Enterprise&rft.pub=X-bit+labs&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fstorage%2Fdisplay%2F20120110180208_OCZ_Demos_4TB_16TB_Solid_State_Drives_for_Enterprise.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-ymSig-156"><a href="#cite_ref-ymSig_156-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.sata-io.org/technology/sataexpress.asp">"Enabling Higher Speed Storage Applications with SATA Express"</a>. SATA-IO. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121127010238/http://www.sata-io.org/technology/sataexpress.asp">Archived</a> from the original on 27 November 2012. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Enabling+Higher+Speed+Storage+Applications+with+SATA+Express&rft.pub=SATA-IO&rft_id=http%3A%2F%2Fwww.sata-io.org%2Ftechnology%2Fsataexpress.asp&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-SNLQe-157"><a href="#cite_ref-SNLQe_157-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.sata-io.org/sata-m2-card">"SATA M.2 Card"</a>. SATA-IO. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131003103042/https://www.sata-io.org/sata-m2-card">Archived</a> from the original on 3 October 2013. Retrieved 14 September 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=SATA+M.2+Card&rft.pub=SATA-IO&rft_id=https%3A%2F%2Fwww.sata-io.org%2Fsata-m2-card&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-FJvMX-158"><a href="#cite_ref-FJvMX_158-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130127094133/http://www.scsita.org/library/scsi-express/">"SCSI Express"</a>. SCSI Trade Association. Archived from <a rel="nofollow" class="external text" href="http://www.scsita.org/library/scsi-express/">the original</a> on 27 January 2013. Retrieved 27 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=SCSI+Express&rft.pub=SCSI+Trade+Association&rft_id=http%3A%2F%2Fwww.scsita.org%2Flibrary%2Fscsi-express%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-YUum6-159"><a href="#cite_ref-YUum6_159-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMeduri2011" class="citation web cs1">Meduri, Vijay (24 January 2011). <a rel="nofollow" class="external text" href="http://www.hpcwire.com/hpcwire/2011-01-24/a_case_for_pci_express_as_a_high-performance_cluster_interconnect.html">"A Case for PCI Express as a High-Performance Cluster Interconnect"</a>. HPCwire. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130114041356/http://www.hpcwire.com/hpcwire/2011-01-24/a_case_for_pci_express_as_a_high-performance_cluster_interconnect.html">Archived</a> from the original on 14 January 2013. Retrieved 7 December 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=A+Case+for+PCI+Express+as+a+High-Performance+Cluster+Interconnect&rft.pub=HPCwire&rft.date=2011-01-24&rft.aulast=Meduri&rft.aufirst=Vijay&rft_id=http%3A%2F%2Fwww.hpcwire.com%2Fhpcwire%2F2011-01-24%2Fa_case_for_pci_express_as_a_high-performance_cluster_interconnect.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-1Jwlv-160"><a href="#cite_ref-1Jwlv_160-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEvan_Koblentz2017" class="citation news cs1">Evan Koblentz (3 February 2017). <a rel="nofollow" class="external text" href="https://www.techrepublic.com/article/new-pci-express-4-0-delay-may-empower-next-gen-alternatives/">"New PCI Express 4.0 delay may empower next-gen alternatives"</a>. Tech Republic. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170401143837/http://www.techrepublic.com/article/new-pci-express-4-0-delay-may-empower-next-gen-alternatives/">Archived</a> from the original on 1 April 2017. Retrieved 31 March 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tech+Republic&rft.atitle=New+PCI+Express+4.0+delay+may+empower+next-gen+alternatives&rft.date=2017-02-03&rft.au=Evan+Koblentz&rft_id=http%3A%2F%2Fwww.techrepublic.com%2Farticle%2Fnew-pci-express-4-0-delay-may-empower-next-gen-alternatives%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-aJ00L-161"><a href="#cite_ref-aJ00L_161-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation web cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14068/cxl-specification-1-released-new-industry-high-speed-interconnect-from-intel">"CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel"</a>. www.anandtech.com. Retrieved 9 August 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=CXL+Specification+1.0+Released%3A+New+Industry+High-Speed+Interconnect+From+Intel&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14068%2Fcxl-specification-1-released-new-industry-high-speed-interconnect-from-intel&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> <li id="cite_note-9ps7Q-162"><a href="#cite_ref-9ps7Q_162-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://pcisig.com/developers/integrators-list">"Integrators List | PCI-SIG"</a>. pcisig.com. Retrieved 27 March 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=pcisig.com&rft.atitle=Integrators+List+%7C+PCI-SIG&rft_id=http%3A%2F%2Fpcisig.com%2Fdevelopers%2Fintegrators-list&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988"> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=50" title="Edit section: Further reading">edit</a>]</div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBudrukAndersonShanley2003" class="citation cs2">Budruk, Ravi; Anderson, Don; Shanley, Tom (2003), Winkles, Joseph ‘Joe’ (ed.), PCI Express System Architecture, Mind share PC system architecture, Addison-Wesley, <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-321-15630-3" title="Special:BookSources/978-0-321-15630-3"><bdi>978-0-321-15630-3</bdi></a></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=PCI+Express+System+Architecture&rft.series=Mind+share+PC+system+architecture&rft.pub=Addison-Wesley&rft.date=2003&rft.isbn=978-0-321-15630-3&rft.aulast=Budruk&rft.aufirst=Ravi&rft.au=Anderson%2C+Don&rft.au=Shanley%2C+Tom&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988">, 1120 pp.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSolariCongdon2003" class="citation cs2">Solari, Edward; Congdon, Brad (2003), Complete PCI Express Reference: Design Implications for Hardware and Software Developers, Intel, <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-9717861-9-6" title="Special:BookSources/978-0-9717861-9-6"><bdi>978-0-9717861-9-6</bdi></a></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Complete+PCI+Express+Reference%3A+Design+Implications+for+Hardware+and+Software+Developers&rft.pub=Intel&rft.date=2003&rft.isbn=978-0-9717861-9-6&rft.aulast=Solari&rft.aufirst=Edward&rft.au=Congdon%2C+Brad&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988">, 1056 pp.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWilenSchadeThornburg2003" class="citation cs2">Wilen, Adam; Schade, Justin P; Thornburg, Ron (April 2003), Introduction to PCI Express: A Hardware and Software Developer's Guide, Intel, <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-9702846-9-3" title="Special:BookSources/978-0-9702846-9-3"><bdi>978-0-9702846-9-3</bdi></a></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Introduction+to+PCI+Express%3A+A+Hardware+and+Software+Developer%27s+Guide&rft.pub=Intel&rft.date=2003-04&rft.isbn=978-0-9702846-9-3&rft.aulast=Wilen&rft.aufirst=Adam&rft.au=Schade%2C+Justin+P&rft.au=Thornburg%2C+Ron&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI+Express" class="Z3988">, 325 pp.</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=PCI_Express&action=edit&section=51" title="Edit section: External links">edit</a>]</div> <ul><li><a href="/wiki/File:Commons-logo.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/24px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a> Media related to <a href="https://commons.wikimedia.org/wiki/Category:PCIe" class="extiw" title="commons:Category:PCIe">PCIe</a> at Wikimedia Commons</li> <li><a rel="nofollow" class="external text" href="https://pcisig.com/specifications">PCI-SIG Specifications</a></li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output 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class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini 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this template">e</abbr></a></li></ul></div><div id="Technical_and_de_facto_standards_for_wired_computer_buses" style="font-size:114%;margin:0 4em"><a href="/wiki/Technical_standard" title="Technical standard">Technical</a> and <a href="/wiki/De_facto_standard" title="De facto standard">de facto standards</a> for <a href="/wiki/Wired_communication" title="Wired communication">wired</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">computer buses</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_bus" title="System bus">System bus</a></li> <li><a href="/wiki/Front-side_bus" title="Front-side bus">Front-side bus</a></li> <li><a href="/wiki/Back-side_bus" title="Back-side bus">Back-side bus</a></li> <li><a href="/wiki/Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></li> <li><a href="/wiki/Control_bus" title="Control bus">Control bus</a></li> <li><a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">Address bus</a></li> <li><a href="/wiki/Bus_contention" title="Bus contention">Bus contention</a></li> <li><a href="/wiki/Bus_mastering" title="Bus mastering">Bus mastering</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li> <li><a href="/wiki/Plug_and_play" title="Plug and play">Plug and play</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Computer_buses" title="List of interface bit rates">List of bus bandwidths</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Standards</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SS-50_bus" title="SS-50 bus">SS-50 bus</a></li> <li><a href="/wiki/S-100_bus" title="S-100 bus">S-100 bus</a></li> <li><a href="/wiki/Multibus" title="Multibus">Multibus</a></li> <li><a href="/wiki/Unibus" title="Unibus">Unibus</a></li> <li><a href="/wiki/VAXBI_bus" title="VAXBI bus">VAXBI</a></li> <li><a href="/wiki/MBus_(SPARC)" title="MBus (SPARC)">MBus</a></li> <li><a href="/wiki/STD_Bus" title="STD Bus">STD Bus</a></li> <li><a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a></li> <li><a href="/wiki/Q-Bus" title="Q-Bus">Q-Bus</a></li> <li><a href="/wiki/Europe_Card_Bus" title="Europe Card Bus">Europe Card Bus</a></li> <li><a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a></li> <li><a href="/wiki/STEbus" title="STEbus">STEbus</a></li> <li><a href="/wiki/Amiga_Zorro_II" title="Amiga Zorro II">Zorro II</a></li> <li><a href="/wiki/Amiga_Zorro_III" title="Amiga Zorro III">Zorro III</a></li> <li><a href="/wiki/Computer_Automated_Measurement_and_Control" title="Computer Automated Measurement and Control">CAMAC</a></li> <li><a href="/wiki/FASTBUS" title="FASTBUS">FASTBUS</a></li> <li><a href="/wiki/Low_Pin_Count" title="Low Pin Count">LPC</a></li> <li><a href="/wiki/HP_Precision_Bus" title="HP Precision Bus">HP Precision Bus</a></li> <li><a href="/wiki/Extended_Industry_Standard_Architecture" title="Extended Industry Standard Architecture">EISA</a></li> <li><a href="/wiki/VMEbus" title="VMEbus">VME</a></li> <li><a href="/wiki/VME_eXtensions_for_Instrumentation" title="VME eXtensions for Instrumentation">VXI</a></li> <li><a href="/wiki/VXS" title="VXS">VXS</a></li> <li><a href="/wiki/VPX" title="VPX">VPX</a></li> <li><a href="/wiki/NuBus" title="NuBus">NuBus</a></li> <li><a href="/wiki/TURBOchannel" title="TURBOchannel">TURBOchannel</a></li> <li><a href="/wiki/Micro_Channel_architecture" title="Micro Channel architecture">MCA</a></li> <li><a href="/wiki/SBus" title="SBus">SBus</a></li> <li><a href="/wiki/VESA_Local_Bus" title="VESA Local Bus">VLB</a></li> <li><a href="/wiki/GSC_bus" title="GSC bus">HP GSC bus</a></li> <li><a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a></li> <li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/Ultra_Port_Architecture" title="Ultra Port Architecture">UPA</a></li> <li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a></li> <li><a href="/wiki/PCI-X" title="PCI-X">PCI Extended (PCI-X)</a></li> <li><a href="/wiki/PCI_eXtensions_for_Instrumentation" title="PCI eXtensions for Instrumentation">PXI</a></li> <li><a class="mw-selflink selflink">PCI Express (PCIe)</a></li> <li><a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a></li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface (DMI)</a></li> <li><a href="/wiki/RapidIO" title="RapidIO">RapidIO</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a></li> <li><a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a> <ul><li><a href="/wiki/Infinity_Fabric" class="mw-redirect" title="Infinity Fabric">Infinity Fabric</a></li></ul></li> <li><a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Intel Ultra Path Interconnect</a></li> <li><a href="/wiki/Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface (CAPI)</a></li> <li><a href="/wiki/SpaceWire" title="SpaceWire">SpaceWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Storage</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ST-506/ST-412" title="ST-506/ST-412">ST-506</a></li> <li><a href="/wiki/Enhanced_Small_Disk_Interface" title="Enhanced Small Disk Interface">ESDI</a></li> <li><a href="/wiki/Intelligent_Peripheral_Interface" title="Intelligent Peripheral Interface">IPI</a></li> <li><a href="/wiki/Storage_Module_Device" title="Storage Module Device">SMD</a></li> <li><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA (PATA)</a></li> <li><a href="/wiki/Bus_and_Tag" title="Bus and Tag">Bus and Tag</a></li> <li><a href="/wiki/Digital_Storage_Systems_Interconnect" title="Digital Storage Systems Interconnect">DSSI</a></li> <li><a href="/wiki/HIPPI" title="HIPPI">HIPPI</a></li> <li><a href="/wiki/SATA" title="SATA">Serial ATA (SATA)</a></li> <li><a href="/wiki/SCSI" title="SCSI">SCSI</a> <ul><li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel</a></li> <li><a href="/wiki/Serial_Attached_SCSI" title="Serial Attached SCSI">SAS</a></li></ul></li> <li><a href="/wiki/ESCON" title="ESCON">ESCON</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li> <li><a href="/wiki/Serial_Storage_Architecture" title="Serial Storage Architecture">SSA</a></li> <li><a href="/wiki/SATA_Express" title="SATA Express">SATAe</a></li> <li>PCI Express (via <a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">AHCI</a> or <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> logical device interface)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Peripheral</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Apple_Desktop_Bus" title="Apple Desktop Bus">Apple Desktop Bus</a></li> <li><a href="/wiki/Atari_SIO" title="Atari SIO">Atari SIO</a></li> <li><a href="/wiki/Digital_Control_Bus" title="Digital Control Bus">DCB</a></li> <li><a href="/wiki/Commodore_bus" title="Commodore bus">Commodore bus</a></li> <li><a href="/wiki/HP-IL" title="HP-IL">HP-IL</a></li> <li><a href="/wiki/HIL_bus" title="HIL bus">HIL</a></li> <li><a href="/wiki/MIDI" title="MIDI">MIDI</a></li> <li><a href="/wiki/RS-232" title="RS-232">RS-232</a></li> <li><a href="/wiki/RS-422" title="RS-422">RS-422</a></li> <li><a href="/wiki/RS-423" title="RS-423">RS-423</a></li> <li><a href="/wiki/RS-485" title="RS-485">RS-485</a></li> <li><a href="/wiki/Lightning_(connector)" title="Lightning (connector)">Lightning</a></li> <li><a href="/wiki/DMX512#DMX512-A" title="DMX512">DMX512-A</a></li> <li><a href="/wiki/IEEE-488" class="mw-redirect" title="IEEE-488">IEEE-488 (GPIB)</a></li> <li><a href="/wiki/IEEE_1284" title="IEEE 1284">IEEE-1284 (parallel port)</a></li> <li><a href="/wiki/IEEE_1394" title="IEEE 1394">IEEE-1394 (FireWire)</a></li> <li><a href="/wiki/UNI/O" title="UNI/O">UNI/O</a></li> <li><a href="/wiki/1-Wire" title="1-Wire">1-Wire</a></li> <li><a href="/wiki/I%C2%B2C" title="I²C">I²C</a> (<a href="/wiki/ACCESS.bus" title="ACCESS.bus">ACCESS.bus</a>, <a href="/wiki/Power_Management_Bus" title="Power Management Bus">PMBus</a>, <a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a>)</li> <li><a href="/wiki/I3C_(bus)" title="I3C (bus)">I3C</a></li> <li><a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a></li> <li><a href="/wiki/IEC_61030" title="IEC 61030">D²B</a></li> <li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel SCSI</a></li> <li><a href="/wiki/Profibus" title="Profibus">Profibus</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Camera_Link" title="Camera Link">Camera Link</a></li> <li><a class="mw-selflink-fragment" href="#PCI_Express_External_Cabling">External PCIe</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Audio</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ADAT_Lightpipe" title="ADAT Lightpipe">ADAT Lightpipe</a></li> <li><a href="/wiki/AES3" title="AES3">AES3</a></li> <li><a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">Intel HD Audio</a></li> <li><a href="/wiki/I%C2%B2S" title="I²S">I²S</a></li> <li><a href="/wiki/MADI" title="MADI">MADI</a></li> <li><a href="/wiki/McASP" title="McASP">McASP</a></li> <li><a href="/wiki/S/PDIF" title="S/PDIF">S/PDIF</a></li> <li><a href="/wiki/TOSLINK" title="TOSLINK">TOSLINK</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Portable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Embedded</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multidrop_bus" title="Multidrop bus">Multidrop bus</a></li> <li><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a></li> <li><a href="/wiki/Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a> (<a href="/wiki/Advanced_eXtensible_Interface" title="Advanced eXtensible Interface">AXI</a>)</li> <li><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a></li> <li><a href="/wiki/SLIMbus" title="SLIMbus">SLIMbus</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. <img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" data-file-height="185" /> <a href="/wiki/Category:Computer_buses" title="Category:Computer buses">Category</a></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Basic_computer_components" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Basic_computer_components" title="Template:Basic computer components"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Basic_computer_components" title="Template talk:Basic computer components"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Basic_computer_components" title="Special:EditPage/Template:Basic computer components"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Basic_computer_components" style="font-size:114%;margin:0 4em">Basic <a href="/wiki/Computer" title="Computer">computer</a> <a href="/wiki/Computer_hardware" title="Computer hardware">components</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Input_device" title="Input device">Input devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Pointing_device" title="Pointing device">Pointing devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Graphics_tablet" title="Graphics tablet">Graphics tablet</a></li> <li><a href="/wiki/Game_controller" title="Game controller">Game controller</a></li> <li><a href="/wiki/Light_pen" title="Light pen">Light pen</a></li> <li><a href="/wiki/Computer_mouse" title="Computer mouse">Mouse</a> <ul><li><a href="/wiki/Optical_mouse" title="Optical mouse">Optical</a></li></ul></li> <li><a href="/wiki/Optical_trackpad" title="Optical trackpad">Optical trackpad</a></li> <li><a href="/wiki/Pointing_stick" title="Pointing stick">Pointing stick</a></li> <li><a href="/wiki/Touchpad" title="Touchpad">Touchpad</a></li> <li><a href="/wiki/Touchscreen" title="Touchscreen">Touchscreen</a></li> <li><a href="/wiki/Trackball" title="Trackball">Trackball</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_keyboard" title="Computer keyboard">Keyboard</a></li> <li><a href="/wiki/Image_scanner" title="Image scanner">Image scanner</a></li> <li><a href="/wiki/Graphics_card" title="Graphics card">Graphics card</a> <ul><li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></li></ul></li> <li><a href="/wiki/Microphone" title="Microphone">Microphone</a></li> <li><a href="/wiki/Refreshable_braille_display" title="Refreshable braille display">Refreshable braille display</a></li> <li><a href="/wiki/Sound_card" title="Sound card">Sound card</a> <ul><li><a href="/wiki/Sound_chip" title="Sound chip">Sound chip</a></li></ul></li> <li><a href="/wiki/Webcam" title="Webcam">Webcam</a> <ul><li><a href="/wiki/Softcam" title="Softcam">Softcam</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Output_device" title="Output device">Output devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_monitor" title="Computer monitor">Monitor</a> <ul><li><a href="/wiki/Electronic_visual_display" title="Electronic visual display">Screen</a></li></ul></li> <li><a href="/wiki/Refreshable_braille_display" title="Refreshable braille display">Refreshable braille display</a></li> <li><a href="/wiki/Printer_(computing)" title="Printer (computing)">Printer</a> <ul><li><a href="/wiki/Plotter" title="Plotter">Plotter</a></li></ul></li> <li><a href="/wiki/Computer_speakers" title="Computer speakers">Speakers</a></li> <li><a href="/wiki/Sound_card" title="Sound card">Sound card</a></li> <li><a href="/wiki/Graphics_card" title="Graphics card">Graphics card</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Removable_media" title="Removable media">Removable data storage</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a></li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a></li> <li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a> <ul><li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li></ul></li> <li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> <ul><li><a href="/wiki/Memory_card" title="Memory card">Memory card</a></li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_case" title="Computer case">Computer case</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> <ul><li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li></ul></li> <li><a href="/wiki/Motherboard" title="Motherboard">Motherboard</a></li> <li><a href="/wiki/Computer_memory" title="Computer memory">Memory</a> <ul><li><a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a></li> <li><a href="/wiki/Nonvolatile_BIOS_memory" title="Nonvolatile BIOS memory">BIOS</a></li></ul></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Data storage</a> <ul><li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">HDD</a></li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">SSD</a> (<a href="/wiki/SATA" title="SATA">SATA</a> / <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a>)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">SSHD</a></li></ul></li> <li><a href="/wiki/Power_supply_unit_(computer)" title="Power supply unit (computer)">Power supply</a> <ul><li><a href="/wiki/Switched-mode_power_supply" title="Switched-mode power supply">SMPS</a></li></ul></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> <ul><li><a href="/wiki/Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li> <li><a href="/wiki/Voltage_regulator_module" title="Voltage regulator module">VRM</a></li></ul></li> <li><a href="/wiki/Network_interface_controller" title="Network interface controller">Network interface controller</a></li> <li><a href="/wiki/Fax_modem" title="Fax modem">Fax modem</a></li> <li><a href="/wiki/Expansion_card" title="Expansion card">Expansion card</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_port_(hardware)" title="Computer port (hardware)">Ports</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li> <li><a href="/wiki/Phone_connector_(audio)" title="Phone connector (audio)">Analog audio jack</a></li> <li><a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a></li> <li><a href="/wiki/HDMI" title="HDMI">HDMI</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IEEE_1394" title="IEEE 1394">FireWire</a> (IEEE 1394)</li> <li><a href="/wiki/Parallel_port" title="Parallel port">Parallel port</a></li> <li><a href="/wiki/Serial_port" title="Serial port">Serial port</a></li> <li><a href="/wiki/Game_port" title="Game port">Game port</a></li> <li><a href="/wiki/PS/2_port" title="PS/2 port">PS/2 port</a></li> <li><a href="/wiki/Serial_ATA#eSATA" class="mw-redirect" title="Serial ATA">eSATA</a></li> <li><a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a></li> <li><a href="/wiki/VGA_connector" title="VGA connector">VGA</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_computing_hardware" title="History of computing hardware">History of computing hardware</a></li> <li><a href="/wiki/History_of_computing_hardware_(1960s%E2%80%93present)" title="History of computing hardware (1960s–present)">History of computing hardware (1960s–present)</a></li> <li><a href="/wiki/List_of_pioneers_in_computer_science" title="List of pioneers in computer science">List of pioneers in computer science</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=PCI_Express&oldid=1256148712">https://en.wikipedia.org/w/index.php?title=PCI_Express&oldid=1256148712</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Computer-related_introductions_in_2004" title="Category:Computer-related introductions in 2004">Computer-related introductions in 2004</a></li><li><a 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