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id="toc-Program_Status_Word_(PSW)" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Program_Status_Word_(PSW)"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Program Status Word (PSW)</span> </div> </a> <ul id="toc-Program_Status_Word_(PSW)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Interruption_system" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Interruption_system"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Interruption system</span> </div> </a> <button aria-controls="toc-Interruption_system-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Interruption system subsection</span> </button> <ul id="toc-Interruption_system-sublist" class="vector-toc-list"> <li id="toc-Input/Output_interruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Input/Output_interruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>Input/Output interruption</span> </div> </a> <ul id="toc-Input/Output_interruption-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Program_interruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Program_interruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>Program interruption</span> </div> </a> <ul id="toc-Program_interruption-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Supervisor_Call_interruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Supervisor_Call_interruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.3</span> <span>Supervisor Call interruption</span> </div> </a> <ul id="toc-Supervisor_Call_interruption-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_interruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#External_interruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.4</span> <span>External interruption</span> </div> </a> <ul id="toc-External_interruption-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Machine_Check_interruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Machine_Check_interruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.5</span> <span>Machine Check interruption</span> </div> </a> <ul id="toc-Machine_Check_interruption-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Input/Output" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Input/Output"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Input/Output</span> </div> </a> <button aria-controls="toc-Input/Output-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Input/Output subsection</span> </button> <ul id="toc-Input/Output-sublist" class="vector-toc-list"> <li id="toc-Channel_status" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Channel_status"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Channel status</span> </div> </a> <ul id="toc-Channel_status-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Unit_status" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Unit_status"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2</span> <span>Unit status</span> </div> </a> <ul id="toc-Unit_status-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Channel_Address_Word" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Channel_Address_Word"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3</span> <span>Channel Address Word</span> </div> </a> <ul id="toc-Channel_Address_Word-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Channel_Command_Word" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Channel_Command_Word"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4</span> <span>Channel Command Word</span> </div> </a> <ul id="toc-Channel_Command_Word-sublist" class="vector-toc-list"> <li id="toc-CCW_Command_codes" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#CCW_Command_codes"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4.1</span> <span>CCW Command codes</span> </div> </a> <ul id="toc-CCW_Command_codes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-CCW_flags" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#CCW_flags"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4.2</span> <span>CCW flags</span> </div> </a> <ul id="toc-CCW_flags-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Channel_Status_Word" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Channel_Status_Word"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.5</span> <span>Channel Status Word</span> </div> </a> <ul id="toc-Channel_Status_Word-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-I/O_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#I/O_instructions"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6</span> <span>I/O instructions</span> </div> </a> <ul id="toc-I/O_instructions-sublist" class="vector-toc-list"> <li id="toc-Start_I/O_(SIO)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Start_I/O_(SIO)"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6.1</span> <span>Start I/O (SIO)</span> </div> </a> <ul id="toc-Start_I/O_(SIO)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Test_I/O_(TIO)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Test_I/O_(TIO)"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6.2</span> <span>Test I/O (TIO)</span> </div> </a> <ul id="toc-Test_I/O_(TIO)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Halt_I/O_(HIO)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Halt_I/O_(HIO)"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6.3</span> <span>Halt I/O (HIO)</span> </div> </a> <ul id="toc-Halt_I/O_(HIO)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Test_Channel_(TCH)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Test_Channel_(TCH)"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6.4</span> <span>Test Channel (TCH)</span> </div> </a> <ul id="toc-Test_Channel_(TCH)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Operator_controls" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Operator_controls"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Operator controls</span> </div> </a> <ul id="toc-Operator_controls-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Optional_features" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Optional_features"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Optional features</span> </div> </a> <button aria-controls="toc-Optional_features-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Optional features subsection</span> </button> <ul id="toc-Optional_features-sublist" class="vector-toc-list"> <li id="toc-Byte-aligned_operands" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Byte-aligned_operands"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.1</span> <span>Byte-aligned operands</span> </div> </a> <ul id="toc-Byte-aligned_operands-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Decimal_arithmetic" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Decimal_arithmetic"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.2</span> <span>Decimal arithmetic</span> </div> </a> <ul id="toc-Decimal_arithmetic-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Direct_Control" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Direct_Control"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.3</span> <span>Direct Control</span> </div> </a> <ul id="toc-Direct_Control-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Floating-point_arithmetic" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Floating-point_arithmetic"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.4</span> <span>Floating-point arithmetic</span> </div> </a> <ul id="toc-Floating-point_arithmetic-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Interval_timer" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Interval_timer"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.5</span> <span>Interval timer</span> </div> </a> <ul id="toc-Interval_timer-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multi-system_operation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Multi-system_operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.6</span> <span>Multi-system operation</span> </div> </a> <ul id="toc-Multi-system_operation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Storage_protection" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Storage_protection"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.7</span> <span>Storage protection</span> </div> </a> <ul id="toc-Storage_protection-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Deviations_and_extensions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Deviations_and_extensions"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Deviations and extensions</span> </div> </a> <ul id="toc-Deviations_and_extensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" 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.infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">System/360</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data"><a href="/wiki/IBM" title="IBM">IBM</a></td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data">32-bit</td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">April 7, 1964<span class="noprint">; 60 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">1964-04-07</span>)</span></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="/wiki/Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">CISC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data">Register-Register<br />Register-Memory<br />Memory-Memory</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Variable <small>(2, 4 or 6 bytes long)</small></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data"><a href="/wiki/Status_register" title="Status register">Condition code</a>, indexing, counting</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Big</td></tr><tr><th scope="row" class="infobox-label">Page size</th><td class="infobox-data">N/A, except for <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">360/67</a></td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Yes</td></tr><tr><th colspan="2" class="infobox-header"><a href="/wiki/Processor_register" title="Processor register">Registers</a></th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/General-purpose_register" class="mw-redirect" title="General-purpose register">General-purpose</a></th><td class="infobox-data">16× 32-bit</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Floating_point" class="mw-redirect" title="Floating point">Floating point</a></th><td class="infobox-data"><a href="/wiki/IBM_hexadecimal_floating-point" title="IBM hexadecimal floating-point">4× 64-bit</a></td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline 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.sidebar-none{float:none;clear:both;margin:0.5em 1em 1em 0}.mw-parser-output .sidebar-outer-title{padding:0 0.4em 0.2em;font-size:125%;line-height:1.2em;font-weight:bold}.mw-parser-output .sidebar-top-image{padding:0.4em}.mw-parser-output .sidebar-top-caption,.mw-parser-output .sidebar-pretitle-with-top-image,.mw-parser-output .sidebar-caption{padding:0.2em 0.4em 0;line-height:1.2em}.mw-parser-output .sidebar-pretitle{padding:0.4em 0.4em 0;line-height:1.2em}.mw-parser-output .sidebar-title,.mw-parser-output .sidebar-title-with-pretitle{padding:0.2em 0.8em;font-size:145%;line-height:1.2em}.mw-parser-output .sidebar-title-with-pretitle{padding:0.1em 0.4em}.mw-parser-output .sidebar-image{padding:0.2em 0.4em 0.4em}.mw-parser-output .sidebar-heading{padding:0.1em 0.4em}.mw-parser-output .sidebar-content{padding:0 0.5em 0.4em}.mw-parser-output .sidebar-content-with-subgroup{padding:0.1em 0.4em 0.2em}.mw-parser-output .sidebar-above,.mw-parser-output .sidebar-below{padding:0.3em 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.sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar nomobile nowraplinks plainlist"><tbody><tr><th class="sidebar-title">History of <a href="/wiki/IBM_mainframe" title="IBM mainframe">IBM mainframes</a>, 1952–present</th></tr><tr><th class="sidebar-heading"> Market name</th></tr><tr><td class="sidebar-content"> <ul><li><a href="/wiki/IBM_700/7000_series" title="IBM 700/7000 series">700/7000 series</a></li> <li><a href="/wiki/IBM_1400_series" title="IBM 1400 series">1400 series</a></li> <li><a href="/wiki/IBM_System/360" title="IBM System/360">System/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">System/370</a></li> <li><a href="/wiki/IBM_30XX_mainframe_lines" title="IBM 30XX mainframe lines">30XX series</a> (<a href="/wiki/IBM_303X" title="IBM 303X">303X</a>, <a href="/wiki/IBM_308X" title="IBM 308X">308X</a>, <a href="/wiki/IBM_3090" title="IBM 3090">3090</a>)</li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">System/390</a></li> <li><a href="/wiki/IBM_zSeries" class="mw-redirect" title="IBM zSeries">eServer zSeries (900, 800; 990, 890)</a></li> <li><a href="/wiki/IBM_System_z9" title="IBM System z9">System z9</a></li> <li><a href="/wiki/IBM_System_z10" title="IBM System z10">System z10</a></li> <li><a href="/wiki/IBM_zEnterprise_System" class="mw-redirect" title="IBM zEnterprise System">zEnterprise System (z196, zEC12)</a></li> <li><a href="/wiki/IBM_Z" title="IBM Z"> IBM Z (z13, z14, z15, z16)</a></li></ul></td> </tr><tr><th class="sidebar-heading"> Architecture</th></tr><tr><td class="sidebar-content"> <ul><li><a class="mw-selflink selflink">System/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">System/370</a></li> <li><a href="/wiki/IBM_System/370-XA" title="IBM System/370-XA">S/370-XA</a></li> <li><a href="/wiki/ESA/370" class="mw-redirect" title="ESA/370">ESA/370</a></li> <li><a href="/wiki/ESA/390" class="mw-redirect" title="ESA/390">ESA/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output 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.navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:IBM_mainframes" title="Template:IBM mainframes"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:IBM_mainframes" title="Template talk:IBM mainframes"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:IBM_mainframes" title="Special:EditPage/Template:IBM mainframes"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/IBM_System/360" title="IBM System/360">IBM System/360</a></div> <p>The <b>IBM System/360 architecture</b> is the model independent <a href="/wiki/Computer_architecture" title="Computer architecture">architecture</a> for the entire <a href="/wiki/S/360" class="mw-redirect" title="S/360">S/360</a> line of <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframe computers</a>, including but not limited to the <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a>. The elements of the architecture are documented in the <i>IBM System/360 Principles of Operation</i><sup id="cite_ref-A22-6821_1-0" class="reference"><a href="#cite_note-A22-6821-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-A22-6821-7_2-0" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> and the <i>IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information</i> manuals.<sup id="cite_ref-A22-6843_3-0" class="reference"><a href="#cite_note-A22-6843-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Features">Features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=1" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="infobox" style="font-size:88%"> <caption align="center"><i>IBM S/360 registers</i> </caption> <tbody><tr> <td style="border-style: none;"> <table class="wikitable" style="font-size:75%"> <caption>General Registers 0-15 </caption> <tbody><tr> <td colspan="34" style="border-style: none;"><br /> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td colspan="32">Two's complement value </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;">0 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">31 </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr></tbody></table> </td></tr> <tr> <td style="border-style: none;"> <table class="wikitable" style="font-size:75%"> <caption>Floating Point Registers 0-6 </caption> <tbody><tr> <td colspan="34" style="border-style: none;"><br /> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td>S </td> <td colspan="7">Biased exponent </td> <td colspan="24">Mantissa </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;">0 </td> <td style="width:1%; text-align:left; border-style: none none none none;">1 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">7 </td> <td style="width:1%; text-align:left; border-style: none none none none;">8 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">31 </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td colspan="34" style="border-style: none;"><br /> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td colspan="32">Mantissa (continued) </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;">32 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">63 </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr></tbody></table> </td></tr> <tr> <td style="border-style: none;"> <table class="wikitable" style="font-size:75%"> <caption>S/360 PSW<sup id="cite_ref-FOOTNOTES36015[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Program_Status_Word]_4-0" class="reference"><a href="#cite_note-FOOTNOTES36015[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Program_Status_Word]-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <td colspan="34" style="border-style: none;"><br /> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td colspan="6">Chan.<br />Mask </td> <td>I<br />O </td> <td>E<br />X </td> <td colspan="4">Key </td> <td>A </td> <td>M </td> <td>W </td> <td>P </td> <td colspan="16">Interruption Code </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;">0 </td> <td style="width:1%; text-align:left; border-style: none none none none;">1 </td> <td style="width:1%; text-align:left; border-style: none none none none;">2 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">4 </td> <td style="width:1%; text-align:left; border-style: none none none none;">5 </td> <td style="width:1%; text-align:left; border-style: none none none none;">6 </td> <td style="width:1%; text-align:left; border-style: none none none none;">7 </td> <td style="width:1%; text-align:left; border-style: none none none none;">8 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">11 </td> <td style="width:1%; text-align:left; border-style: none none none none;">12 </td> <td style="width:1%; text-align:left; border-style: none none none none;">13 </td> <td style="width:1%; text-align:left; border-style: none none none none;">14 </td> <td style="width:1%; text-align:left; border-style: none none none none;">15 </td> <td style="width:1%; text-align:left; border-style: none none none none;">16 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">31 </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td colspan="34" style="border-style: none;"><br /> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td colspan="2">ILC </td> <td colspan="2">CC </td> <td colspan="4">Program<br />Mask </td> <td colspan="24">Instruction Address </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;">32 </td> <td style="width:1%; text-align:right; border-style: none none none none;">33 </td> <td style="width:1%; text-align:left; border-style: none none none none;">34 </td> <td style="width:1%; text-align:right; border-style: none none none none;">35 </td> <td style="width:1%; text-align:left; border-style: none none none none;">36 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;">39 </td> <td style="width:1%; text-align:left; border-style: none none none none;">40 </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:left; border-style: none none none none;"> </td> <td style="width:1%; text-align:right; border-style: none none none none;'">63 </td> <td style="width:.5%; text-align:left; border-style: none none none none;"> </td></tr> <tr> <td colspan="34" style="border-style: none;"> <table class="wikitable mw-collapsible autocollapse"> <caption><span class="nowrap">S/360 PSW abbreviations</span> </caption> <tbody><tr> <th style="width:10%; text-align:left;">Bits </th> <th style="width:10%; text-align:left;">Field </th> <th style="width:80%; text-align:left;">Meaning </th></tr> <tr> <td>0-5 </td> <td> </td> <td>Channel Masks for channels 0-5 </td></tr> <tr> <td>6 </td> <td>IO </td> <td>I/O Mask for channels > 5 </td></tr> <tr> <td>7 </td> <td>EX </td> <td>External Mask </td></tr> <tr> <td>8-11 </td> <td>Key </td> <td>PSW key </td></tr> <tr> <td>12 </td> <td>A </td> <td><b>A</b>SCII mode for decimal arithmetic </td></tr> <tr> <td>13 </td> <td>M </td> <td>Machine-check mask </td></tr> <tr> <td>14 </td> <td>W </td> <td>Wait state </td></tr> <tr> <td>15 </td> <td>P </td> <td>Problem state </td></tr> <tr> <td>16-31 </td> <td>IC </td> <td>Interruption Code<sup id="cite_ref-FOOTNOTES36015_–&#32,_16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Interruption]_5-0" class="reference"><a href="#cite_note-FOOTNOTES36015_–&#32,_16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Interruption]-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>32-33 </td> <td>ILC </td> <td>Instruction-Length Code<sup id="cite_ref-FOOTNOTES36077[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage88_Interruptions]_6-0" class="reference"><a href="#cite_note-FOOTNOTES36077[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage88_Interruptions]-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>34-35 </td> <td>CC </td> <td>Condition Code </td></tr> <tr> <td>36-39 </td> <td>PM </td> <td> <table class="wikitable mw-collapsible autocollapse"> <caption style="text-align: left;"><span class="nowrap">Program Mask</span> </caption> <tbody><tr> <th>Bit </th> <th>Meaning </th></tr> <tr> <td>36 </td> <td>Fixed-point overflow </td></tr> <tr> <td>37 </td> <td>Decimal overflow </td></tr> <tr> <td>38 </td> <td>Exponent underflow </td></tr> <tr> <td>39 </td> <td>Significance </td></tr></tbody></table> </td></tr> <tr> <td>40-63 </td> <td>IA </td> <td>Instruction Address </td></tr></tbody></table> </td></tr></tbody></table> <ul><li>IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.</li></ul> </td></tr></tbody></table> <p>The System/360 architecture provides the following features: </p> <ul><li>16 <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> general-purpose registers</li> <li>4 64-bit <a href="/wiki/IBM_hexadecimal_floating-point" title="IBM hexadecimal floating-point">floating-point</a> registers</li> <li>64-bit processor status register (PSW), which includes a 24-bit <a href="/wiki/Program_counter" title="Program counter">instruction address</a></li> <li>24-bit (16 MB) byte-addressable memory space</li> <li><a href="/wiki/Big-endian" class="mw-redirect" title="Big-endian">Big-endian</a> byte/word order</li> <li>A <i>standard instruction set</i>, including fixed-point binary arithmetic and logical instructions, present on all System/360 models (except the <a href="/wiki/IBM_System/360_Model_20" title="IBM System/360 Model 20">Model 20</a>, see below). <ul><li>A <i>commercial instruction set</i>, adding decimal arithmetic instructions, is optional on some models, as is a <i>scientific instruction set</i>, which adds floating-point instructions. The <i>universal instruction set</i> includes all of the above plus the storage protection instructions and is standard for some models.</li> <li>The <a href="/wiki/IBM_System/360_Model_44" title="IBM System/360 Model 44">Model 44</a> provides a few unique instructions for data acquisition and real-time processing and is missing the storage-to-storage instructions. However, IBM offered a '<i>Commercial Instruction Set"</i> feature that ran in bump storage and simulated the missing instructions.</li> <li>The <a href="/wiki/IBM_System/360_Model_20" title="IBM System/360 Model 20">Model 20</a> offers a stripped-down version of the standard instruction set, limited to eight general registers with halfword (16-bit) instructions only, plus the commercial instruction set, and unique instructions for input/output.</li> <li>The <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">Model 67</a> includes some instructions to handle 32-bit addresses and "dynamic address translation", with additional privileged instructions to provide virtual memory.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li></ul></li></ul> <div class="mw-heading mw-heading2"><h2 id="Memory">Memory</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=2" title="Edit section: Memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Memory (<i>storage</i>) in System/360 is addressed in terms of <a href="/wiki/8-bit" class="mw-redirect" title="8-bit">8-bit</a> bytes. Various instructions operate on larger units called <i>halfword</i> (2 bytes), <i>fullword</i> (4 bytes), <i>doubleword</i> (8 bytes), <i>quad word</i> (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as <a href="/wiki/Big-endian" class="mw-redirect" title="Big-endian">big-endian</a>. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term <i>word</i> refers to a <i>fullword</i>. </p><p>The original architecture of System/360 provided for up to 2<sup>24</sup> = 16,777,216 bytes of memory. The later <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">Model 67</a> extended the architecture to allow up to 2<sup>32</sup> = 4,294,967,296<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>NB 1<span class="cite-bracket">]</span></a></sup> bytes of virtual memory. </p> <div class="mw-heading mw-heading2"><h2 id="Addressing">Addressing</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=3" title="Edit section: Addressing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>System/360 uses truncated addressing similar to that of the <a href="/wiki/UNIVAC_III" title="UNIVAC III">UNIVAC III</a>.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>NB 2<span class="cite-bracket">]</span></a></sup> general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses. </p> <div class="mw-heading mw-heading2"><h2 id="Data_formats">Data formats</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=4" title="Edit section: Data formats"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">Floating-point arithmetic</a> features. </p> <ul><li><b>Characters</b> are stored as 8-bit bytes.</li> <li><b>Integers</b> are stored as two's complement binary halfword or fullword values.</li> <li><b><a href="/wiki/Packed_decimal" class="mw-redirect" title="Packed decimal">Packed decimal</a></b> numbers are stored as 1 to 16 8-bit bytes containing an odd number of decimal digits followed by a 4-bit sign. Sign values of hexadecimal A, C, E, and F are positive and sign values of hexadecimal B and D are negative. Digit values of hexadecimal A-F and sign values of 0-9 are invalid, but the PACK and UNPK instructions do not test for validity.</li> <li><b><a href="/wiki/Zoned_decimal" class="mw-redirect" title="Zoned decimal">Zoned decimal</a></b> numbers are stored as 1 to 16 8-bit bytes, each containing a zone in bits 0-3 and a digit in bits 4-7. The zone of the rightmost byte is interpreted as a sign.</li> <li><b><a href="/wiki/IBM_hexadecimal_floating-point" title="IBM hexadecimal floating-point">Floating point</a></b> numbers are only stored as fullword or doubleword values on older models. On the 360/85<sup id="cite_ref-A22-6916_11-0" class="reference"><a href="#cite_note-A22-6916-11"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> and 360/195<sup id="cite_ref-A22-6943_12-0" class="reference"><a href="#cite_note-A22-6943-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> there are also extended precision floating point numbers stored as quadwords. For all three formats, bit 0 is a sign and bits 0-7 are a characteristic (exponent, biased by 64). Bits 8-31 (8-63) are a hexadecimal fraction. For extended precision, the low order doubleword has its own sign and characteristic, which are ignored on input and generated on output.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Instruction_formats">Instruction formats</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=5" title="Edit section: Instruction formats"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats: </p> <ul><li><b>RR</b> (two bytes). Generally byte 1 specifies two 4-bit register numbers, but in some cases, e.g., SVC, byte 1 is a single 8-bit immediate field.</li> <li><b>RS</b> (four bytes). Byte 1 specifies two register numbers; bytes 2-3 specify a base and displacement.</li> <li><b>RX</b> (four bytes). Bits 0-3 of byte 1 specify either a register number or a modifier; bits 4-7 of byte 1 specify the number of the general register to be used as an index; bytes 2-3 specify a base and displacement.</li> <li><b>SI</b> (four bytes). Byte 1 specifies an immediate field; bytes 2-3 specify a base and displacement.</li> <li><b>SS</b> (six bytes). Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length fields is length-1.</li></ul> <p>Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0. </p> <div class="mw-heading mw-heading2"><h2 id="Program_Status_Word_(PSW)"><span id="Program_Status_Word_.28PSW.29"></span>Program Status Word (PSW)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=6" title="Edit section: Program Status Word (PSW)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Program_Status_Word" class="mw-redirect" title="Program Status Word">Program Status Word</a></div> <p>The <b>Program Status Word</b> (<b>PSW</b>)<sup id="cite_ref-A22-6821-7_2-1" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 71–72">: 71–72 </span></sup> contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks. </p> <table class="wikitable collapsible"> <caption>PSW format </caption> <tbody><tr> <th align="center" valign="bottom">Bits </th> <th align="center" valign="bottom">Contents </th> <th align="left" valign="bottom">Explanation </th></tr> <tr> <td align="center" valign="top">0-7 </td> <td valign="top" style="align:left;"><span class="anchor" id="System_Mask"></span>System Mask </td> <td valign="top">bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,<sup id="cite_ref-ChanNum_14-0" class="reference"><a href="#cite_note-ChanNum-14"><span class="cite-bracket">[</span>NB 3<span class="cite-bracket">]</span></a></sup> bit 7: enable External interruptions (timer, interrupt key, and external signal)<sup class="reference"><a href="#Pops">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 71">: 71 </span></sup> </td></tr> <tr> <td align="center" valign="top">8-11 </td> <td>Protection key<span class="anchor" id="Key"></span> </td> <td>CPU protection key to compare against storage protection keys </td></tr> <tr> <td align="center" valign="top">12<span class="anchor" id="AMWP"></span> </td> <td valign="top">ASCII mode </td> <td>enable ASCII mode for packed decimal instructions, never used by IBM software<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>NB 4<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td align="center" valign="top">13 </td> <td valign="top">Machine checks </td> <td>enable Machine check interruptions </td></tr> <tr> <td align="center" valign="top">14 </td> <td valign="top">Wait State </td> <td>processor is halted, an interruption, if enabled, will cause the processor to resume executing instructions </td></tr> <tr> <td align="center" valign="top">15 </td> <td valign="top">Problem state </td> <td>enable to prevent the use of instructions reserved for supervisor state </td></tr> <tr> <td align="center" valign="top">16-31 </td> <td valign="top"><span class="anchor" id="Interruption_Code"></span>Interruption Code </td> <td>code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loaded<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 77">: 77 </span></sup> </td></tr> <tr> <td align="center" valign="top">32-33 </td> <td><span class="anchor" id="InstructionLengthCode"></span>Instruction Length Code </td> <td>length in halfwords or 0 if unavailable </td></tr> <tr> <td align="center" valign="top">34-35 </td> <td><span class="anchor" id="ConditionCode"></span>Condition Code </td> <td>see individual instructions for encoding </td></tr> <tr> <td align="center" valign="top">36-39 </td> <td valign="top"><span class="anchor" id="Program_Mask"></span>Program Mask </td> <td>bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 71">: 71 </span></sup> </td></tr> <tr> <td align="center" valign="top">40-63 </td> <td valign="top"><span class="anchor" id="Instruction_Address"></span>Instruction Address </td> <td valign="top">address of next instruction, except for a program interruptions with ILC 0 </td></tr></tbody></table> <p><span class="anchor" id="LPSW"></span><b>Load Program Status Word</b> (<b>LPSW</b>) is a privileged <a href="/wiki/Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instruction</a> that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is most often used to "return" from an interruption by loading the "old" PSW which is associated with the interruption class. Other privileged instructions (e.g., SSM, STNSM, STOSM, SPKA, etcetera) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW; and one non-privileged instruction (SPM) is available for manipulating the program mask. </p> <div class="mw-heading mw-heading2"><h2 id="Interruption_system">Interruption system</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=7" title="Edit section: Interruption system"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The architecture<sup id="cite_ref-A22-6821-7_2-2" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 77–83">: 77–83 </span></sup> defines 5 classes of <a href="/wiki/Interrupt" title="Interrupt">interruption</a>. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>NB 5<span class="cite-bracket">]</span></a></sup> and <a href="/wiki/Asynchrony_(computing)" class="mw-redirect" title="Asynchrony (computing)">asynchronous</a> events. </p> <table class="wikitable collapsible"> <tbody><tr> <th>Interruption class</th> <th>Old PSW<br />hex dec</th> <th>New PSW<br />hex dec </th> <th align="right" valign="top">Priority </th></tr> <tr> <td><a href="#Input/Output_interruption">Input/Output</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 78–79">: 78–79 </span></sup></td> <td>38   56</td> <td>78  120</td> <td align="right">4 </td></tr> <tr> <td><a href="#Program_interruption">Program</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 79–80.1">: 79–80.1 </span></sup></td> <td>28   40</td> <td>68 104</td> <td align="right">2 </td></tr> <tr> <td><a href="#Supervisor_Call_interruption">Supervisor Call</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 80.1–81">: 80.1–81 </span></sup></td> <td>20   32</td> <td>60   96</td> <td align="right">2 </td></tr> <tr> <td><a href="#External_interruption">External</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 81–82">: 81–82 </span></sup></td> <td>18   24</td> <td>58   88</td> <td align="right">3 </td></tr> <tr> <td><a href="#Machine_Check_interruption">Machine Check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 82–83">: 82–83 </span></sup></td> <td>30   48</td> <td>70  112</td> <td align="right">1 </td></tr></tbody></table> <p>There are two storage fields assigned to each class of interruption on the S/360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW location and then loads the PSW from the new PSW location. This generally replaces the instruction address, thereby effecting a branch, and (optionally) sets and/or resets other fields within the PSW, thereby effecting a mode change. </p><p>The S/360 architecture defines a priority to each interruption class, but it is only relevant when two interruptions occur simultaneously; an interruption routine can be interrupted by any other enabled interruption, including another occurrence of the initial interruption. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the "first-level" interruption handlers. "Second-level" interruption handlers are generally designed for stacked interruptions (multiple occurrences of interruptions of the same interruption class). </p> <div class="mw-heading mw-heading3"><h3 id="Input/Output_interruption"><span id="Input.2FOutput_interruption"></span>Input/Output interruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=8" title="Edit section: Input/Output interruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An I/O interruption<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 78–79">: 78–79 </span></sup> occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for <a href="/wiki/Asynchrony_(computing)" class="mw-redirect" title="Asynchrony (computing)">asynchronous</a> events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the <a href="#Channel_Status_Word">CSW</a> at location 64 ('40'X). </p> <div class="mw-heading mw-heading3"><h3 id="Program_interruption">Program interruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=9" title="Edit section: Program interruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A Program interruption<sup id="cite_ref-A22-6821-7_2-3" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 16, 79–80.1">: 16, 79–80.1 </span></sup> occurs when an instruction encounters one<sup id="cite_ref-multimpr_18-0" class="reference"><a href="#cite_note-multimpr-18"><span class="cite-bracket">[</span>NB 6<span class="cite-bracket">]</span></a></sup> of 15<sup id="cite_ref-NotArchExc_19-0" class="reference"><a href="#cite_note-NotArchExc-19"><span class="cite-bracket">[</span>NB 7<span class="cite-bracket">]</span></a></sup> exceptions; however, if the <a href="#Program_Mask">Program Mask</a> bit corresponding to an exception is 0 then there is no interruption for that exception. On 360/65,<sup id="cite_ref-A22-6884_20-0" class="reference"><a href="#cite_note-A22-6884-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 12">: 12 </span></sup> 360/67<sup id="cite_ref-GA27-2719_13-2" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 46">: 46 </span></sup> and 360/85<sup id="cite_ref-A22-6916_11-1" class="reference"><a href="#cite_note-A22-6916-11"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 12">: 12 </span></sup> the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0. The Interruption code may be any of </p> <table class="wikitable collapsible"> <caption>Interruption codes for Program interruptions<br />old PSW bits 26-31 </caption> <tbody><tr> <th style="text-align:right;width:6em">hex<br />bits 26-31 </th> <th>Dec </th> <th style="wisth:20m">Exception </th></tr> <tr> <td align="right" valign="top">0 </td> <td align="right" valign="top">0 </td> <td> <p>Imprecise interruption<sup id="cite_ref-multimpr_18-1" class="reference"><a href="#cite_note-multimpr-18"><span class="cite-bracket">[</span>NB 6<span class="cite-bracket">]</span></a></sup> on 360/91,<sup id="cite_ref-A22-6907_17-1" class="reference"><a href="#cite_note-A22-6907-17"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 15">: 15 </span></sup> 360/95 or 360/195<sup id="cite_ref-A22-6943_12-4" class="reference"><a href="#cite_note-A22-6943-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 14">: 14 </span></sup> </p> <table class="wikitable collapsible collapsed"> <caption><span class="nowrap">Old PSW bits for multiple imprecise interruption codes</span> </caption> <tbody><tr> <th style="text-align:right;width:6em">bit </th> <th>Exception </th></tr> <tr> <td>16 </td> <td>Protection </td></tr> <tr> <td>17 </td> <td>Addressing </td></tr> <tr> <td>18 </td> <td>Specification<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>NB 8<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>19 </td> <td>Data </td></tr> <tr> <td>20 </td> <td>Fixed-Point Overflow </td></tr> <tr> <td>21 </td> <td>Fixed-Point Divide </td></tr> <tr> <td>22 </td> <td>Exponent Overflow </td></tr> <tr> <td>23 </td> <td>Exponent Underflow </td></tr> <tr> <td>24 </td> <td>Significance </td></tr> <tr> <td>25 </td> <td>Floating-Point Divide </td></tr> <tr> <td>26 </td> <td>Decimal Overflow<sup id="cite_ref-NoDec_22-0" class="reference"><a href="#cite_note-NoDec-22"><span class="cite-bracket">[</span>NB 9<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>27 </td> <td>Decimal Divide<sup id="cite_ref-NoDec_22-1" class="reference"><a href="#cite_note-NoDec-22"><span class="cite-bracket">[</span>NB 9<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> </td></tr> <tr> <td align="right">1 </td> <td align="right">1 </td> <td><a href="#Operation_exception">Operation</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> </td></tr> <tr> <td align="right">2 </td> <td align="right">2 </td> <td><a href="#Privileged_operation_exception">Privileged operation</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> </td></tr> <tr> <td align="right">3 </td> <td align="right">3 </td> <td><a href="#Execute_exception">Execute</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> </td></tr> <tr> <td align="right">4 </td> <td align="right">4 </td> <td><a href="#Protection_exception">Protection</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> </td></tr> <tr> <td align="right">5 </td> <td align="right">5 </td> <td><a href="#Addressing_exception">Addressing</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 79–80">: 79–80 </span></sup> </td></tr> <tr> <td align="right">6 </td> <td align="right">6 </td> <td><a href="#Specification_exception">Specification</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">7 </td> <td align="right">7 </td> <td><a href="#Data_exception">Data</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">8 </td> <td align="right">8 </td> <td><a href="#Fixed-point_overflow_exception">Fixed-point overflow</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">9 </td> <td align="right">9 </td> <td><a href="#Fixed-point_divide_exception">Fixed-point divide</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">A </td> <td align="right">10 </td> <td><a href="#Decimal_overflow_exception">Decimal overflow</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">B </td> <td align="right">11 </td> <td><a href="#Decimal_divide_exception">Decimal divide</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">C </td> <td align="right">12 </td> <td><a href="#Exponent_overflow_exception">Exponent overflow</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">D </td> <td align="right">13 </td> <td><a href="#Exponent_underflow_exception">Exponent underflow</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">E </td> <td align="right">14 </td> <td><a href="#Significance_exception">Significance</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> </td></tr> <tr> <td align="right">F </td> <td align="right">15 </td> <td><a href="#Floating-point_divide_exception">Floating-point divide</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80.1">: 80.1 </span></sup> </td></tr> <tr> <td align="right">10 </td> <td align="right">16 </td> <td> <p>Segment Translation<sup id="cite_ref-GA27-2719_13-3" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 17">: 17 </span></sup><sup id="cite_ref-NotArchExc_19-1" class="reference"><a href="#cite_note-NotArchExc-19"><span class="cite-bracket">[</span>NB 7<span class="cite-bracket">]</span></a></sup> </p> </td></tr> <tr> <td align="right">11 </td> <td align="right">17 </td> <td> <p>Page Translation<sup id="cite_ref-GA27-2719_13-4" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 17">: 17 </span></sup><sup id="cite_ref-NotArchExc_19-2" class="reference"><a href="#cite_note-NotArchExc-19"><span class="cite-bracket">[</span>NB 7<span class="cite-bracket">]</span></a></sup> </p> </td></tr> <tr> <td align="right">12 </td> <td align="right">18 </td> <td> <p>SSM Exception<sup id="cite_ref-A22-6884_20-1" class="reference"><a href="#cite_note-A22-6884-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-NotArchExc_19-3" class="reference"><a href="#cite_note-NotArchExc-19"><span class="cite-bracket">[</span>NB 7<span class="cite-bracket">]</span></a></sup> </p> </td></tr></tbody></table> <ul><li>An <b>operation exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> is recognized when a program attempts to execute an instruction with an opcode that the computer does not implement. In particular, an operation exception is recognized when a program is written for an optional feature, e.g., floating point, that is not installed.</li> <li>A <b>privileged operation exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> is recognized when a program attempts to execute a privileged instruction when the problem state bit in the PSW is 1.</li> <li>An <b>execute exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> is recognized when the operand of an <a href="/wiki/Execute_instruction" title="Execute instruction">EXECUTE instruction (EX)</a> is another EXECUTE instruction.</li> <li>A <b>protection exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 79">: 79 </span></sup> is recognized when a program attempts to store into a location whose storage protect key does not match<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>NB 10<span class="cite-bracket">]</span></a></sup> the PSW key, or to fetch from a fetch protected location whose storage protect key does not match the PSW key.</li> <li>An <b>addressing exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 79–80">: 79–80 </span></sup> is recognized when a program attempts to access a storage location that is not currently available. This normally occurs with an address beyond the capacity of the machine, but it may also occur on machines that allow blocks of storage to be taken offline.</li> <li>A <b>specification exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when an instruction has a length or register field with values not permitted by the operation, or when it has an operand address that does not satisfy the alignment requirements of the opcode, e.g., a LH instruction with an odd operand address on a machine without the byte alignment feature.</li> <li>A <b>data exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when a decimal instruction specifies invalid operands, e.g., invalid data, invalid overlap.</li> <li>A <b>fixed-point overflow exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when significant bits are lost in a fixed point arithmetic or shift instruction, other than divide.</li> <li>A <b>fixed-point divide exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when significant bits are lost in a fixed point divide or Convert to Binary instruction.</li> <li>A <b>decimal overflow exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when significant digits are lost in a decimal arithmetic instruction, other than divide.</li> <li>A <b>decimal divide exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when significant bits are lost in a decimal divide instruction. The destination is not altered.</li> <li>An <b>exponent overflow exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when the characteristic in a floating-point arithmetic operation exceeds 127 and the fraction is not zero.</li> <li>An <b>exponent underflow exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when the characteristic in a floating-point arithmetic operation is negative and the fraction is not zero.</li> <li>A <b>significance exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80">: 80 </span></sup> is recognized when the fraction in a floating-point add or subtract operation is zero.</li> <li>A <b>floating-point divide exception</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 80.1">: 80.1 </span></sup> is recognized when the fraction in the divisor of a floating-point divide operation is zero.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Supervisor_Call_interruption">Supervisor Call interruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=10" title="Edit section: Supervisor Call interruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A Supervisor Call interruption<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 80.1–81">: 80.1–81 </span></sup> occurs as the result of a <a href="/wiki/Supervisor_Call_instruction" title="Supervisor Call instruction">Supervisor Call instruction</a>; the system stores bits 8-15 of the SVC instruction as the Interruption Code. </p> <div class="mw-heading mw-heading3"><h3 id="External_interruption">External interruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=11" title="Edit section: External interruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An External<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 81">: 81 </span></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>NB 11<span class="cite-bracket">]</span></a></sup> interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1 </p> <table class="wikitable collapsible"> <caption>Interruption codes for External interruptions </caption> <tbody><tr> <th valign="top" style="text-align:right;width:8em">PSW bit </th> <th>Type of external interruption </th></tr> <tr> <td align="right"> <p>24 </p> </td> <td>Timer </td></tr> <tr> <td align="right"> <p>25 </p> </td> <td>Interrupt key </td></tr> <tr> <td align="right" valign="top"> <p>26 </p> </td> <td>External signal 2<br />Malfunction alert on 360/65<sup id="cite_ref-A22-6884_20-2" class="reference"><a href="#cite_note-A22-6884-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> in Multisystem mode </td></tr> <tr> <td align="right" valign="top"> <p>27 </p> </td> <td>External signal 3<br />System Call on 360/65<sup id="cite_ref-A22-6884_20-3" class="reference"><a href="#cite_note-A22-6884-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> in Multisystem mode </td></tr> <tr> <td align="right"> <p>28 </p> </td> <td>External signal 4 </td></tr> <tr> <td align="right"> <p>29 </p> </td> <td>External signal 5 </td></tr> <tr> <td align="right"> <p>30 </p> </td> <td>External signal 6 </td></tr> <tr> <td align="right"> <p>31 </p> </td> <td>External signal 7 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Machine_Check_interruption">Machine Check interruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=12" title="Edit section: Machine Check interruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A Machine Check interruption<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 82–83">: 82–83 </span></sup> occurs to report unusual conditions associated with the channel or CPU that cannot be reported by another class of interruption. The most important class of conditions causing a Machine Check is a hardware error such as a parity error found in registers or storage, but some models may use it to report less serious conditions. Both the interruption code and the data stored in the scanout area at '80'x (128 decimal) are model dependent. </p> <div class="mw-heading mw-heading2"><h2 id="Input/Output"><span id="Input.2FOutput"></span>Input/Output</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=13" title="Edit section: Input/Output"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information on physical interface: <a href="/wiki/Bus_and_Tag" title="Bus and Tag">Bus and Tag</a></div> <p>This article describes I/O from the CPU perspective. It does not discuss the channel cable or connectors, which have a <a href="/wiki/Bus_and_Tag" title="Bus and Tag">separate article</a>; there is a summary <a href="/wiki/IBM_System/360#Channels" title="IBM System/360">elsewhere</a> and details can be found in the IBM literature<sup id="cite_ref-A22-6843_3-1" class="reference"><a href="#cite_note-A22-6843-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and in FIPS PUB 60-2.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>I/O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through <a href="/wiki/IBM_System/360_Model_50" title="IBM System/360 Model 50">360/50</a>) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiple <b>subchannel</b>s, each containing the status of an individual channel program. A subchannel associated with multiple devices that cannot concurrently have channel programs is referred to as <b>shared</b>; a subchannel representing a single device is referred to as <b>unshared</b>. </p><p>There are three types of channels on the S/360: </p> <ul><li><span class="anchor" id="IBM_Byte_Mux"></span>A <b>byte multiplexer channel</b> is capable of executing multiple <b>CCW</b>s concurrently; it is normally used to attach slow devices such as card readers and telecommunications lines. A byte multiplexer channel could have a number of selector subchannels, each with only a single subchannel, which behave like low-speed selector channels.</li> <li><span class="anchor" id="IBM_Sel"></span>A <b>selector channel</b> has only a single subchannel, and hence is only capable of executing one channel command at a time. It is normally used to attach fast devices that are not capable of exploiting a block multiplexer channel to suspend the connection, such as magnetic tape drives.</li> <li><span class="anchor" id="IBM_Blk_Mux"></span>A <b>block multiplexer channel</b> is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which there is a mechanical delay after completion of data transfer, e.g., for seeks on moving-head DASD. The block multiplexer channel was a late addition to the System/360 architecture; early machines had only byte multiplexer channels and selector channels. The block multiplexer channel was an optional feature only on the models 85 and 195. The block multiplexor channel was also available on the later <a href="/wiki/IBM_System/370" title="IBM System/370">System/370</a> computers.</li></ul> <p>Conceptually peripheral equipment is attached to a S/360 through <i>control units</i>, which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that <a href="/wiki/Cycle_stealing" title="Cycle stealing">steal cycles</a> from the processor. </p><p>Peripheral devices are addressed with 16-bit<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>NB 12<span class="cite-bracket">]</span></a></sup> addresses.,<sup id="cite_ref-A22-6821-7_2-4" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 89">: 89 </span></sup> referred to as <i>cua</i> or <i>cuu</i>; this article will use the term <i>cuu</i>. The high 8 bits identify a channel, numbered from 0 to 6,<sup id="cite_ref-ChanNum_14-1" class="reference"><a href="#cite_note-ChanNum-14"><span class="cite-bracket">[</span>NB 3<span class="cite-bracket">]</span></a></sup> while the low 8 bits identify a device on that channel. A device may have multiple <i>cuu</i> addresses. </p><p>Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel. </p><p>Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O was processed. If not, then the selection was passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N. </p><p>There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword <i>Channel Address Word</i> (<b>CAW</b>). Performing an I/O normally requires the following: </p> <ul><li>initializing the <b>CAW</b> with the storage key and the address of the first CCW</li> <li>issuing a <i>Start I/O</i> (<b>SIO</b>) instruction that specifies the <i>cuu</i> for the operation</li> <li>waiting<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>NB 13<span class="cite-bracket">]</span></a></sup> for an I/O interruption</li> <li>handling any unusual conditions indicated in the <i>Channel Status Word</i> (<b>CSW</b>)</li></ul> <p>A channel program consists of a sequence of <i>Channel Control Words</i> (<b>CCW</b>s) chained together (see below.) Normally the channel fetches <b>CCW</b>s from consecutive doublewords, but a control unit can direct the channel to skip a CCW and a <i>Transfer In Channel</i> (<b>TIC</b>) <b>CCW</b> can direct the channel to start fetching <b>CCW</b>s from a new location. </p><p>There are several defined ways for a channel command to complete. Some of these allow the channel to continue fetching CCWs, while others terminate the channel program. In general, if the CCW does not have the chain-command bit set and is not a TIC, then the channel will terminate the I/O operation and cause an I/O interruption when the command completes. Certain status bits from the control unit suppress chaining. </p><p>The most common ways for a command to complete are for the count to be exhausted when chain-data is not set and for the control unit to signal that no more data transfers should be made. If Suppress-Length-Indication (SLI) is not set and one of those occurs without the other, chaining is not allowed. The most common situations that suppress chaining are unit-exception and unit-check. However, the combination of unit-check and status-modifier does not suppress chaining; rather, it causes the channel to do a command retry, reprocessing the same CCW. </p><p>In addition to the interruption signal sent to the CPU when an I/O operation is complete, a channel can also send a Program-Controlled interruption (PCI) to the CPU while the channel program is running, without terminating the operation, and a delayed device-end interruption after the I/O completion interruption. </p> <div class="mw-heading mw-heading3"><h3 id="Channel_status">Channel status</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=14" title="Edit section: Channel status"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These conditions are detected by the channel and indicated in the <a href="#Channel_Status_Word">CSW</a>.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 116–118">: 116–118 </span></sup> </p> <ul><li><span class="anchor" id="Program-controlled_interruption_status"></span><span class="anchor" id="PCI_status"></span><b><a href="#CSW_Program-controlled_interruption_status">Program-controlled interruption</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 116–117">: 116–117 </span></sup> indicates that the channel has fetched a CCW with the PCI bit set. The channel continues processing; this interruption simply informs the CPU of the channel's progress. An example of the use of Program-controlled interruption is in the "Program Fetch" function of Contents Supervision, whereby the control program is notified that a Control/Relocation Record has been read. To ensure that this record has been completely read into main storage, a "disabled bit spin", one of the few which remains in the control program, is initiated. Satisfaction of the spin indicates that the Control/Relocation Record is completely in main storage and the immediately preceding Text Record may be relocated. After relocation, a NOP CCW is changed to a TIC and the channel program continues. In this way, an entire load module may be read and relocated while utilizing only one <a href="/wiki/EXCP" class="mw-redirect" title="EXCP">EXCP</a>, and possibly only one revolution of the disk drive. PCI also has applications in teleprocessing access method buffer management.</li> <li><span class="anchor" id="Incorrect_length"></span><span class="anchor" id="IL"></span><b><a href="#CSW_Incorrect_length">Incorrect length</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 117">: 117 </span></sup> indicates that the data transfer for a command completed before the Count was exhausted. This indication is suppressed if the <a href="#CCW-SuppressLengthIndication">Suppress-Length-Indication</a> bit in the CCW is set.</li> <li><b><a href="#CSW_Program_check">Program check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 117">: 117 </span></sup> indicates one of the following errors <ul><li>Nonzero bits where zeros are required</li> <li>An invalid data or CCW address</li> <li>The CAW or a TIC refers to a TIC</li></ul></li> <li><span class="anchor" id="Protection_check"></span><b><a href="#CSW_Protection_check">Protection check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 117–118">: 117–118 </span></sup> indicates that the protection key in the CAW is non-zero and does not match the storage protection key.</li> <li><span class="anchor" id="Channel_data_check"></span><span class="anchor" id="CDC"></span><b><a href="#CSW_Channel_data_check">Channel data check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup> indicates a parity error during a data transfer.</li> <li><span class="anchor" id="Channel_control_check"></span><span class="anchor" id="CCC"></span><b><a href="#CSW_Channel_control_check">Channel control check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup> indicates a channel malfunction other than <a href="#Channel_data_check">Channel data check</a> or <a href="#Interface_control_check">Interface control check</a>.</li> <li><span class="anchor" id="Interface_control_check"></span><span class="anchor" id="ICC"></span><b><a href="#CSW_Interface_control_check">Interface control check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup> indicates an invalid signal in the channel to control unit interface.</li> <li><span class="anchor" id="Chaining_check"></span><b><a href="#CSW_Chaining_check">Chaining check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup> indicates lost data during data chaining.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Unit_status">Unit status</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=15" title="Edit section: Unit status"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These conditions are presented to the channel by the control unit or device.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 113–116">: 113–116 </span></sup> In some cases they are handled by the channel and in other cases they are indicated in the <a href="#Channel_Status_Word">CSW</a>. There is no distinction between conditions detected by the control unit and conditions detected by the device. </p> <ul><li><span class="anchor" id="Attention"></span><b><a href="#CSW_Attention">Attention</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 113">: 113 </span></sup> indicates an unusual condition not associated with an ongoing channel program. It often indicates some sort of operator action like requesting input, in which case the CPU would respond by issuing a read-type command, most often a sense command (04h) from which additional information could be deduced. Attention is a special condition, and requires specific operating system support, and for which the operating system has a special attention table<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>NB 14<span class="cite-bracket">]</span></a></sup> with a necessarily limited number of entries.</li> <li><span class="anchor" id="Status_modifier"></span><span class="anchor" id="SM"></span><b><a href="#CSW_Status_modifier">Status modifier</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 113–114">: 113–114 </span></sup> (SM) indicates one of three unusual conditions <ul><li>A Test I/O instruction was issued to a device that does not support it.</li> <li>A <a href="#Busy">Busy</a> status refers to the control unit rather than to the device.</li> <li>A device has detected a condition that requires skipping a CCW. A CCW with a command for which Status Modifier is possible will normally specify command chaining, in which case the SM is processed by the channel and does not cause an interruption.</li></ul></li></ul> <dl><dd><dl><dd>A typical channel program where SM occurs is</dd></dl></dd></dl> <pre> ... Search Id Equal TIC *-8 Read Data </pre> <dl><dd><dl><dd>where the TIC causes the channel to refetch the search until the device indicates a successful search by raising SM.</dd></dl></dd></dl> <ul><li><span class="anchor" id="Control_unit_end"></span><b><a href="#CSW_Control_unit_end">Control unit end</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 114">: 114 </span></sup> indicates that a previous control unit busy status has been cleared.</li> <li><span class="anchor" id="Busy"></span><b><a href="#CSW_Busy">Busy</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 114–115">: 114–115 </span></sup> indicates that a device (<a href="#Status_modifier">SM</a>=0) or a control unit (<a href="#Status_modifier">SM</a>=1) is busy.</li> <li><span class="anchor" id="Channel_end"></span><span class="anchor" id="CE"></span><b><a href="#CSW_Channel_end">Channel end</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 115">: 115 </span></sup> indicates that the device has completed the data transfer for a channel command. There may also be an <a href="#Incorrect_length">Incorrect length</a> indication if the Count field of the CCW is exhausted, depending on the value of the <a href="#CCW-SuppressLengthIndication">Suppress-Length-Indication</a> bit.</li> <li><span class="anchor" id="Device_end"></span><span class="anchor" id="DE"></span><b><a href="#CSW_Device_end">Device end</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 115">: 115 </span></sup> indicates that the device has completed an operation and is ready to accept another. DE may be signalled concurrently with <a href="#Channel_en">CE</a> or may be delayed.</li> <li><span class="anchor" id="Unit_check"></span><span class="anchor" id="UC"></span><b><a href="#CSW_Unit_check">Unit check</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 115–116">: 115–116 </span></sup> indicates that the device or control unit has detected an unusual conditions and that details may be obtained by issuing a Sense command.</li> <li><span class="anchor" id="Unit_exception"></span><span class="anchor" id="UE"></span><b><a href="#CSW_Unit_exception">Unit exception</a></b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 116">: 116 </span></sup> indicates that the device has detected an unusual condition, e.g., end of file.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Channel_Address_Word">Channel Address Word</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=16" title="Edit section: Channel Address Word"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The fullword <i>Channel Address Word</i><sup id="cite_ref-A22-6821-7_2-5" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 99">: 99 </span></sup> (CAW) contains a 4-bit storage protection key and a 24-bit address of the channel program to be started. </p> <div class="mw-heading mw-heading3"><h3 id="Channel_Command_Word">Channel Command Word</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=17" title="Edit section: Channel Command Word"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A <i>Channel Command Word</i> is a doubleword containing the following: </p> <ul><li>an 8-bit channel <a href="#CCW_Command_codes">Command Code</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 100">: 100 </span></sup></li> <li>a 24-bit address<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 100–101">: 100–101 </span></sup></li> <li>a 5-bit flag field<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 99–100, 101–105">: 99–100, 101–105 </span></sup></li> <li>an unsigned halfword Count field<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 100–101">: 100–101 </span></sup></li></ul> <div class="mw-heading mw-heading4"><h4 id="CCW_Command_codes">CCW Command codes</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=18" title="Edit section: CCW Command codes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The low order 2 or 4 bits determine the six types of operations that the channel performs;.<sup id="cite_ref-A22-6821-7_2-6" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 100, 105">: 100, 105 </span></sup> The encoding is </p> <table class="wikitable collapsible"> <caption>CCW Command codes </caption> <tbody><tr> <th style="font-family:monospace; width:7em">bits </th> <th>Command </th></tr> <tr> <td style="font-family:monospace">**** 0000 </td> <td>Invalid in a CCW, simulated by the processor's Test I/O (TIO) instruction </td></tr> <tr> <td style="font-family:monospace">MMMM 0100 </td> <td>Sense<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 106–107">: 106–107 </span></sup> </td></tr> <tr> <td style="font-family:monospace">**** 1000 </td> <td>Transfer in Channel (TIC)<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 107–108">: 107–108 </span></sup> </td></tr> <tr> <td style="font-family:monospace">MMMM 1100 </td> <td>Read Backward<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 105–106">: 105–106 </span></sup> </td></tr> <tr> <td style="font-family:monospace">MMMM MM01 </td> <td>Write<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 105">: 105 </span></sup> </td></tr> <tr> <td style="font-family:monospace">MMMM MM10 </td> <td>Read<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 105">: 105 </span></sup> </td></tr> <tr> <td style="font-family:monospace">MMMM MM11 </td> <td>Control<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 106–107">: 106–107 </span></sup> </td></tr></tbody></table> <p>The meaning of the high order six or four bits, the modifier bits, <b>M</b> in the table above, depends upon the type of I/O device attached, see e.g., <a href="/wiki/Direct-access_storage_device" title="Direct-access storage device">DASD</a> <a href="/wiki/Count_key_data" title="Count key data">CKD CCWs</a>. All eight bits are sent to and interpreted in the associated control unit (or its functional equivalent). </p><p>Control is used to cause a state change in a device or control unit, often associated with mechanical motion, e.g., rewind, seek. </p><p>Sense is used to read data describing the status of the device. The most important case is that when a command terminates with unit check, the specific cause can only be determined by doing a Sense and examining the data returned. A Sense command with the modifier bits all zero is always valid. </p><p>A noteworthy deviation from the architecture is that DASD use Sense command codes for Reserve and Release, instead of using Control. </p> <div class="mw-heading mw-heading4"><h4 id="CCW_flags">CCW flags</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=19" title="Edit section: CCW flags"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The flags in a CCW affect how it executes and terminates. </p> <table class="wikitable collapsible"> <caption>CCW flags </caption> <tbody><tr> <th align="right" valign="top" style="width:5em">bit </th> <th> </th> <th>flag </th> <th>effect </th></tr> <tr> <td align="right" valign="top">32 </td> <td valign="top"><span class="anchor" id="CCW-CD"></span>CD </td> <td valign="top"><span class="anchor" id="CCW-ChainData"></span>Chain-Data </td> <td>Continue operation using the storage area defined by the next CCW.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 101–103">: 101–103 </span></sup> </td></tr> <tr> <td align="right" valign="top">33 </td> <td valign="top"><span class="anchor" id="CCW-CC"></span>CC </td> <td valign="top"><span class="anchor" id="CCW-ChainCommand"></span>Chain-Command </td> <td>Continue with the Command in the next CCW.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 101, 103">: 101, 103 </span></sup> </td></tr> <tr> <td align="right" valign="top">34 </td> <td valign="top"><span class="anchor" id="CCW-SLI"></span>SLI<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>NB 15<span class="cite-bracket">]</span></a></sup> </td> <td valign="top"><span class="anchor" id="CCW-SuppressLengthindication"></span>Suppress-Length-Indication </td> <td>Continue channel program after count mis-match.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 99–100">: 99–100 </span></sup> </td></tr> <tr> <td align="right" valign="top">35 </td> <td valign="top"><span class="anchor" id="CCW-SKIP"></span>SKIP </td> <td valign="top">Skip </td> <td>Do not read from or write into storage.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 103–104">: 103–104 </span></sup> </td></tr> <tr> <td align="right" valign="top">36 </td> <td valign="top"><span class="anchor" id="CCW-PCI"></span>PCI </td> <td valign="top"><span class="anchor" id="CCW-ProgramControlledInterupt"></span>Program-Controlled-Interruption </td> <td>Request interruption when fetching CCW.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 104–105">: 104–105 </span></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Channel_Status_Word">Channel Status Word</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=20" title="Edit section: Channel Status Word"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <i>Channel Status Word</i> (CSW)<sup id="cite_ref-A22-6821-7_2-7" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 113–121">: 113–121 </span></sup> provides data associated with an I/O interruption. </p> <table class="wikitable collapsible"> <caption>CSW format </caption> <tbody><tr> <th align="right" valign="top" style="width:5em">bits </th> <th>field </th></tr> <tr> <td align="right">0-3 </td> <td>Key<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 119">: 119 </span></sup> </td></tr> <tr> <td align="right">4-7 </td> <td>0000 </td></tr> <tr> <td align="right">8-31 </td> <td>Command Address<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 119">: 119 </span></sup> </td></tr> <tr> <td align="right">32-47 </td> <td>Status<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 113–118">: 113–118 </span></sup> </td></tr> <tr> <td align="right" valign="top">32-39 </td> <td valign="top"> <dl><dd>Unit Status Conditions<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 113–116">: 113–116 </span></sup></dd> <dd>Detected by the device or control unit</dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Attention"></span>32 </td> <td> <dl><dd><a href="#Attention">Attention</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 113">: 113 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Status_modifier"></span>33 </td> <td> <dl><dd><a href="#Status_modifier">Status modifier</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 113–114">: 113–114 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Control_unit_end"></span>34 </td> <td> <dl><dd><a href="#Control_unit_end">Control unit end</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 114">: 114 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Busy"></span>35 </td> <td> <dl><dd><a href="#Busy">Busy</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 114–115">: 114–115 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Channel_end"></span>36 </td> <td> <dl><dd><a href="#Channel_end">Channel end</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 115">: 115 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Device_end"></span>37 </td> <td> <dl><dd><a href="#Device_end">Device end</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 115">: 115 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Unit_check"></span>38 </td> <td> <dl><dd><a href="#Unit_check">Unit check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 115–116">: 115–116 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Unit_exception"></span>39 </td> <td> <dl><dd><a href="#Unit_exception">Unit exception</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 116">: 116 </span></sup></dd></dl> </td></tr> <tr> <td align="right" valign="top">40-47 </td> <td valign="top"> <dl><dd>Channel Status Conditions<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 116–118">: 116–118 </span></sup></dd> <dd>Detected by the channel.</dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Program-controlled_interruption_status"></span>40 </td> <td> <dl><dd><a href="#Program-controlled_interruption_status">Program-controlled interruption</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 116–117">: 116–117 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Incorrect_length"></span>41 </td> <td> <dl><dd><a href="#Incorrect_length">Incorrect length</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 117">: 117 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Program_check"></span>42 </td> <td> <dl><dd><a href="#Program_check">Program check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 117">: 117 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Protection_check"></span>43 </td> <td> <dl><dd><a href="#Protection_check">Protection check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 117–118">: 117–118 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Channel_data_check"></span>44 </td> <td> <dl><dd><a href="#Channel_data_check">Channel data check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Channel_control_check"></span>45 </td> <td> <dl><dd><a href="#Channel_control_check">Channel control check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Interface_control_check"></span>46 </td> <td> <dl><dd><a href="#Interface_control_check">Interface control check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup></dd></dl> </td></tr> <tr> <td align="right"><span class="anchor" id="CSW_Chaining_check"></span>47 </td> <td> <dl><dd><a href="#Chaining_check">Chaining check</a><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 118">: 118 </span></sup></dd></dl> </td></tr> <tr> <td align="right">48-63 </td> <td>Count<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 120">: 120 </span></sup> </td></tr></tbody></table> <ul><li>The <b>Protection Key</b> field contains the protect key from the CAW at the time that the I/O operation was initiated for I/O complete or PCI interruptions.<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 119">: 119 </span></sup></li> <li>The <b>Command Address</b> field contains the address+8 of the last CCW fetched for an I/O complete or PCI interruption. However, there are 9 exceptions<sup class="reference"><a href="#PoOps">PoOps</a></sup>.<sup class="reference nowrap"><span title="Page: 119">: 119 </span></sup></li> <li>The <b>Status</b> field contains one byte of <a href="#Channel_status">Channel status</a> bits, indicating conditions detected by the channel<sup class="reference"><a href="#PoOps">PoOps</a></sup>,<sup class="reference nowrap"><span title="Pages: 116–118">: 116–118 </span></sup> and one byte of <a href="#Unit_status">Unit status</a> bits, indicating conditions detected by the I/O unit<sup class="reference"><a href="#PoOps">PoOps</a></sup>.<sup class="reference nowrap"><span title="Pages: 113–116">: 113–116 </span></sup> There is no distinction between conditions detected by the control unit and conditions detected by the device.</li> <li>The <b>Residual Count</b> is a half word that gives the number of bytes in the area described by the CCW that have not been transferred to or from the channel<sup class="reference"><a href="#PoOps">PoOps</a></sup>.<sup class="reference nowrap"><span title="Page: 120">: 120 </span></sup> The difference between the count in the CCW and the residual count gives the number of bytes transferred.</li></ul> <div class="mw-heading mw-heading3"><h3 id="I/O_instructions"><span id="I.2FO_instructions"></span>I/O instructions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=21" title="Edit section: I/O instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The S/360 has four<sup id="cite_ref-FOOTNOTES36093–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage105_Control_of_Input/Output_Devices]_30-0" class="reference"><a href="#cite_note-FOOTNOTES36093–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage105_Control_of_Input/Output_Devices]-30"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> I/O instructions: Start I/O (SIO), Test I/O (TIO), Halt I/O (HIO) and Test Channel (TCH). All four are privileged and thus will cause a privileged operation program interruption if used in problem state. The B<sub>1</sub> (base) and D<sub>1</sub> (displacement) fields are used to calculate the cuu (channel and device number); bits 8-15 of the instructions are unused and should be zero for compatibility with the S/370. </p> <div class="mw-heading mw-heading4"><h4 id="Start_I/O_(SIO)"><span id="Start_I.2FO_.28SIO.29"></span>Start I/O (SIO)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=22" title="Edit section: Start I/O (SIO)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SIO<sup id="cite_ref-FOOTNOTES36094–95[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage106_Start_I/O]_31-0" class="reference"><a href="#cite_note-FOOTNOTES36094–95[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage106_Start_I/O]-31"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> attempts to start the channel program pointed to by the <a href="#Channel_Address_Word">CAW</a>, using the storage protection key in the CAW. </p> <div class="mw-heading mw-heading4"><h4 id="Test_I/O_(TIO)"><span id="Test_I.2FO_.28TIO.29"></span>Test I/O (TIO)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=23" title="Edit section: Test I/O (TIO)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TIO<sup id="cite_ref-FOOTNOTES36095–96[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage107_Test_I/O]_32-0" class="reference"><a href="#cite_note-FOOTNOTES36095–96[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage107_Test_I/O]-32"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> tests the status of a channel and device. It may also store a <a href="#_Channel_Status_Word">CSW</a>, in which case it completes with condition code 1. </p> <div class="mw-heading mw-heading4"><h4 id="Halt_I/O_(HIO)"><span id="Halt_I.2FO_.28HIO.29"></span>Halt I/O (HIO)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=24" title="Edit section: Halt I/O (HIO)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>HIO<sup id="cite_ref-FOOTNOTES36096–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage108_Halt_I/O]_33-0" class="reference"><a href="#cite_note-FOOTNOTES36096–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage108_Halt_I/O]-33"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> attempt to terminate an active channel program. It may also store a <a href="#_Channel_Status_Word">CSW</a>, in which case it completes with condition code 1. </p> <div class="mw-heading mw-heading4"><h4 id="Test_Channel_(TCH)"><span id="Test_Channel_.28TCH.29"></span>Test Channel (TCH)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=25" title="Edit section: Test Channel (TCH)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TCH<sup id="cite_ref-FOOTNOTES36098[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage110_Test_Channel]_34-0" class="reference"><a href="#cite_note-FOOTNOTES36098[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage110_Test_Channel]-34"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> tests the status of a channel. It does not affect the status of an active channel program and does not store a <a href="#_Channel_Status_Word">CSW</a>, </p> <div class="mw-heading mw-heading2"><h2 id="Operator_controls">Operator controls</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=26" title="Edit section: Operator controls"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_System_360_operator_controls.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bc/IBM_System_360_operator_controls.png/200px-IBM_System_360_operator_controls.png" decoding="async" width="200" height="200" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bc/IBM_System_360_operator_controls.png/300px-IBM_System_360_operator_controls.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bc/IBM_System_360_operator_controls.png/400px-IBM_System_360_operator_controls.png 2x" data-file-width="1600" data-file-height="1600" /></a><figcaption>operator controls</figcaption></figure> <p>The architecture of System/360 specified the existence of several common functions, but did not specify their means of implementation. This allowed IBM to use different physical means, e.g., dial, keyboard, pushbutton, roller, image or text on a CRT, for selecting the functions and values on different processors. Any reference to <i>key</i> or <i>switch</i> should be read as applying to, e.g., a light-pen selection, an equivalent keyboard sequence. </p> <ul><li><b>System Reset</b> sends a reset signal on every I/O channel and clears the processor state; all pending interruptions are cancelled. System Reset is not guaranteed to correct parity errors in general registers, floating point registers or storage. System Reset does not reset the state of shared I/O devices.</li> <li><b><span class="anchor" id="Initial_Program_Load"></span>Initial Program Load</b> (IPL)<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 123">: 123 </span></sup> is a process for loading a program when there isn't a loader available in storage, usually because the machine was just powered on or to load an alternative operating system.<sup id="cite_ref-A22-6821-7_2-8" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 123">: 123 </span></sup> This process is sometimes known as <a href="/wiki/Booting" title="Booting">Booting</a>.</li></ul> <dl><dd><dl><dd>As part of the IPL facility the operator has a means of specifying a 12-bit<sup id="cite_ref-ChanNum_14-2" class="reference"><a href="#cite_note-ChanNum-14"><span class="cite-bracket">[</span>NB 3<span class="cite-bracket">]</span></a></sup> device address, typically with three dials as shown in the operator controls drawing. When the operator<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>NB 16<span class="cite-bracket">]</span></a></sup> selects the <i>Load</i> function, the system performs a <i>System Reset</i>, sends a Read IPL<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>NB 17<span class="cite-bracket">]</span></a></sup> channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetching <i>CCW</i>s at location 8; the effect is as if the channel had fetched a CCW with a length of 24, and address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at location 2 and loads the PSW from location 0.</dd></dl></dd></dl> <dl><dd><dl><dd>Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.</dd></dl></dd></dl> <ul><li><b>Emergency pull switch</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> (Emergency power off, EPO) sends an EPO signal to every I/O channel, then turns off power to the processor complex. Because EPO bypasses the normal sequencing of power down, damage can result, and the EPO control has a mechanical latch to ensure that a customer engineer inspects the equipment before attempting to power it back on.</li> <li><b>Power on</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> powers up all components of the processor complex and performs a system reset.</li> <li><b>Power off</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> initiates an orderly power-off sequence. Although the contents of storage are preserved, the associated storage keys may be lost.</li> <li>The <b>Interrupt</b> key<sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> causes an <a href="#External_interruption">external interruption</a> with bit 25 set in the External Old PSW.</li> <li>The <b>Wait light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> indicates that the <a href="#Program_Status_Word_(PSW)">PSW</a> has bit 14 (wait) set; the processor is temporarily halted but resumes operation when an interruption condition occurs.</li> <li>The <b>Manual light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> indicates that the CPU is in a stopped state.</li> <li>The <b>System light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> indicates that a meter is running, either due to CPU activity or due to I/O channel activity.</li> <li>The <b>Test light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> indicates that certain operator controls are active, when certain facilities, e.g., INSTRUCTION STEP, have been used by a Diagnose instruction or when abnormal thermal conditions exist. The details are model dependent.</li> <li>The <b>Load light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 124">: 124 </span></sup> is turned on by IPL and external start. It is turned off by loading the PSW from location 0 at the completion of the load process.</li> <li>The <b>Load unit</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 124–125">: 124–125 </span></sup> controls provide the rightmost 11<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>NB 18<span class="cite-bracket">]</span></a></sup> bits of the device from which to perform an IPL.</li> <li>The <b>Load Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> starts the <a href="#Initial_Program_Load">IPL</a> sequence.</li> <li>The <b>Prefix Select Key Switch</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> selects whether <a href="#Initial_Program_Load">IPL</a> will use the primary prefix or the alternative prefix.</li> <li>The <b>System-Reset Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> initiates a <a href="#System_Reset">System Reset</a>.</li> <li>The <b>Stop Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> puts the CPU in a stopped state; channel programs continue running and interruption conditions remain pending.</li> <li>The <b>Rate Switch</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> determines the mode in which the processor fetches instructions. Two modes are defined by the architecture: <ul><li>PROCESS</li> <li>INSTRUCTION STEP</li></ul></li> <li>The <b>Start Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 125">: 125 </span></sup> initiates instruction fetching in accordance with the setting of the <a href="#Rate_Switch">Rate Switch</a>.</li> <li>The <b>Storage-Select Switch</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> determines the type of resource accessed by the <a href="#Store_Key">Store Key</a> and <a href="#Display_Key">Display Key</a>. Three selections are defined by the architecture: <ul><li>Main storage</li> <li>General registers</li> <li>Floating-point registers</li></ul></li> <li>The <b>Address Switches</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> specify the address or register number for the <a href="#Store_Key">Store Key</a>, <a href="#Display_Key">Display Key</a> and, on some models, the <a href="#Set_IC_Key">Set IC Key</a>..</li> <li>The <b>Data Switches</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> specify the data for the <a href="#Store_Key">Store Key</a> and, on some models, the <a href="#Set_IC_Key">Set IC Key</a>.</li> <li>The <b>Store Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> stores the value in the <a href="#Data_Switches">Data Switches</a> as specified by the <a href="/wiki/">Storage-Select Switch</a> and the <a href="#Address_Switches">Address Switches</a>.</li> <li>The <b>Display Key</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> displays the value specified by the <a href="/wiki/">Storage-Select Switch</a> and the <a href="#Address_Switches">Address Switches</a>.</li> <li>The <b>Set IC=</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> sets the instruction address portion of the PSW from the <a href="#Data_Switches">Data Switches</a> or the <a href="#Address_Switches">Address Switches</a>, depending on the model.</li> <li>The <b>Address-Compare Switches</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> select the mode of comparison and what is compared. Stop on instruction address compare is present on all models, but stop on data address compare is only present on some models.</li> <li>The <b>Alternate-Prefix Light</b><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 126">: 126 </span></sup> is on when the prefix trigger is in the alternate state.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Optional_features">Optional features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=27" title="Edit section: Optional features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Byte-aligned_operands">Byte-aligned operands</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=28" title="Edit section: Byte-aligned operands"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>On some models, e.g., the <a href="/wiki/IBM_System/360_Model_85" title="IBM System/360 Model 85">S/360-85</a>,<sup id="cite_ref-A22-6916_11-2" class="reference"><a href="#cite_note-A22-6916-11"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs depending on receiving a program check type 6 (alignment) on those instructions must be modified. </p> <div class="mw-heading mw-heading3"><h3 id="Decimal_arithmetic">Decimal arithmetic</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=29" title="Edit section: Decimal arithmetic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The decimal arithmetic feature provides instructions that operate on packed decimal data. A packed decimal number has 1-31 decimal digits followed by a 4-bit sign. All of the decimal arithmetic instructions except PACK and UNPACK generate a Data exception if a digit is not in the range 0-9 or a sign is not in the range A-F. </p> <div class="mw-heading mw-heading3"><h3 id="Direct_Control">Direct Control</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=30" title="Edit section: Direct Control"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <i>Direct Control</i><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 17.1">: 17.1 </span></sup> feature provides six external signal lines and an 8-bit data path to/from storage.<sup id="cite_ref-A22-6845_38-0" class="reference"><a href="#cite_note-A22-6845-38"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Floating-point_arithmetic">Floating-point arithmetic</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=31" title="Edit section: Floating-point arithmetic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The floating-point arithmetic feature provides 4 64-bit floating point registers and instructions to operate on 32 and 64 bit hexadecimal floating point numbers. The 360/85 and 360/195 also support 128 bit extended precision floating point numbers. </p> <div class="mw-heading mw-heading3"><h3 id="Interval_timer">Interval timer</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=32" title="Edit section: Interval timer"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>If the interval timer feature<sup id="cite_ref-A22-6821-7_2-9" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 17.1">: 17.1 </span></sup> is installed, the processor decrements the word at location 80 ('50'X) at regular intervals; the architecture does not specify the interval but does require that value subtracted make it appear as though 1 were subtracted from bit 23 300 times per second. The smaller models decremented at the same frequency (50 Hz or 60 Hz) as the AC power supply, but larger models had a high resolution timer feature. The processor causes an External interruption when the timer goes to zero. </p> <div class="mw-heading mw-heading3"><h3 id="Multi-system_operation">Multi-system operation</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=33" title="Edit section: Multi-system operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><i>Multi-system operation</i><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Pages: 17.1–18">: 17.1–18 </span></sup> is a set of features to support multi-processor systems, e.g., <a href="#Direct_Control">Direct Control</a>, direct address relocation (prefixing). </p> <div class="mw-heading mw-heading3"><h3 id="Storage_protection">Storage protection</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=34" title="Edit section: Storage protection"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>If the storage protection feature<sup id="cite_ref-A22-6821-7_2-10" class="reference"><a href="#cite_note-A22-6821-7-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Pages: 17-17.1">: 17-17.1 </span></sup> is installed, then there is a 4-bit storage key associated with every 2,048-byte block of storage and that key is checked when storing into any address in that block by either a CPU or an I/O channel. A CPU or channel key of 0 disables the check; a nonzero CPU or channel key allows data to be stored only in a block with the matching key. </p><p>Storage Protection was used to prevent a defective application from writing over storage belonging to the operating system or another application. This permitted testing to be performed along with production. Because the key was only four bits in length, the maximum number of different applications that could be run simultaneously was 15. </p><p>An additional option available on some models was fetch protection. It allowed the operating system to specify that blocks were protected from fetching as well as from storing. </p> <div class="mw-heading mw-heading2"><h2 id="Deviations_and_extensions">Deviations and extensions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=35" title="Edit section: Deviations and extensions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/IBM_System/360_Model_20" title="IBM System/360 Model 20">System/360 Model 20</a> is radically different and should not be considered to be a S/360. </p><p>The <a href="/wiki/IBM_System/360_Model_44" title="IBM System/360 Model 44">System/360 Model 44</a> is missing certain instructions, but a feature allowed the missing instructions to be simulated in hidden memory thus allowing the use of standard S/360 operating systems and applications. </p><p>Some models have features that extended the architecture, e.g., emulation instructions, paging, and some models make minor deviations from the architecture. Examples include: </p> <ul><li>The multisystem feature on the S/360-65 which modifies the behavior of the direct control feature and of the Set System Mask (SSM) instruction.<sup id="cite_ref-A22-6884_20-4" class="reference"><a href="#cite_note-A22-6884-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li> <li>The <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">System/360 Model 67</a>-2 had similar, but incompatible, changes.<sup id="cite_ref-GA27-2719_13-5" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup></li></ul> <p>Some deviations served as prototypes for features of the <a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a> architecture. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=36" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Memory_protection_key" class="mw-redirect" title="Memory protection key">Memory protection key</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=37" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 35em;"> <ol class="references"> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text">Twice the size of the later System/370</span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text">A specification of general register 0 yield a base address of zero rather than the register content.</span> </li> <li id="cite_note-ChanNum-14"><span class="mw-cite-backlink">^ <a href="#cite_ref-ChanNum_14-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ChanNum_14-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-ChanNum_14-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text">On a processor that complies with the S/360 architecture, the highest channel number is 6. Eleven bits are sufficient to identify the cuu, and seven bits are sufficient to provide masking of I/O interruptions. However, on a 360/67-2 with two 2846 channel controllers, channels are numbered 0-6 and 8-14;<sup id="cite_ref-GA27-2719_13-0" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 15">: 15 </span></sup> similarly, the 360/195 had an extended channel feature<sup id="cite_ref-A22-6943_12-1" class="reference"><a href="#cite_note-A22-6943-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 21">: 21 </span></sup> but numbered the channels 0 through 13.<sup id="cite_ref-A22-6943_12-2" class="reference"><a href="#cite_note-A22-6943-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 25">: 25 </span></sup> I/O interruptions for Channel Controller 1 on the 360/67-2 were masked using control registers, and the 360/195 used bit 7 (Channel 6) of the System Mask as a summary mask bit for channels 6 and up. <i>Interruptions from More than Seven Channels</i><sup><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 121.4">: 121.4 </span></sup> describes the summary masking for additional channels, but other text in Principles of Operation still refers to a limit of 7 channels. Standard software supported channels 0-F.</span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text">Because the design of the S/360 occurred simultaneously with the development of ASCII, IBM's ASCII support did not match the standard that was ultimately adopted.</span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text">The S/360 literature does not use the terms fault or <a href="/wiki/Trap_(computing)" class="mw-redirect" title="Trap (computing)">trap</a></span> </li> <li id="cite_note-multimpr-18"><span class="mw-cite-backlink">^ <a href="#cite_ref-multimpr_18-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-multimpr_18-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">On the 360/91,<sup id="cite_ref-A22-6907_17-0" class="reference"><a href="#cite_note-A22-6907-17"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 15">: 15 </span></sup> 360/95 and 360/195<sup id="cite_ref-A22-6943_12-3" class="reference"><a href="#cite_note-A22-6943-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 14">: 14 </span></sup> a Program interruption may occur for multiple imprecise exceptions. The ILC in the Program Old PSW is 0, bits 26-31 are 0 and bits 16-27 are a mask indicating which exceptions occurred; there is no provision for reporting multiple occurrences of the same exception. Reporting of multiple imprecise exceptions is not part of the S/360 architecture.</span> </li> <li id="cite_note-NotArchExc-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-NotArchExc_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-NotArchExc_19-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-NotArchExc_19-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-NotArchExc_19-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text">There are 17 possible exceptions on the 360/67,<sup id="cite_ref-GA27-2719_13-1" class="reference"><a href="#cite_note-GA27-2719-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 17">: 17 </span></sup> but page exception and segment exception are not part of the S/360 architecture; similarly, interruption code 18 ('0012'X) on a 360/65 multiprocessor is not part of the S/360 architecture.</span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text">The Specification bit is not used for imprecise interruptions on the 360/195</span> </li> <li id="cite_note-NoDec-22"><span class="mw-cite-backlink">^ <a href="#cite_ref-NoDec_22-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-NoDec_22-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Not Used on 360/91</span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text">A PSW key of 0 matches any storage key.</span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text">Even though a timer expiration is an internal event, it causes an External interruption and for this reason, this interruption is usually referred to as a timer/external interruption.</span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text">Because of the limits on the channel number, S/360 and early S/370 software only used 12 bits to store device addresses.</span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text">But continuing with unrelated work.</span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text">The OS uses the attention index in a <a href="/wiki/Unit_Control_Block" title="Unit Control Block">Unit Control Block</a> (UCB) as an index into the attention table.</span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text">Also known as Suppress Incorrect Length Indication (SILI)</span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text">Or an equivalent automated facility.</span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text">Read with all modifier bits zero</span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text">There is an inconsistency, in that <i>Interruptions from More than Seven Channels</i><sup class="reference"><a href="#PoOps">PoOps</a></sup><sup class="reference nowrap"><span title="Page: 121.4">: 121.4 </span></sup> allows for more channels.</span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=38" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <dl><dt><b>S360</b></dt> <dd><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFS360" class="citation book cs1"><i>IBM System/360 Principles of Operation</i>. Systems Reference Library (Eighth ed.). IBM. September 1968. A22-6821-7.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Principles+of+Operation&rft.series=Systems+Reference+Library&rft.edition=Eighth&rft.pub=IBM&rft.date=1968-09&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></dd></dl> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-A22-6821-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-A22-6821_1-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1964" class="citation book cs2">IBM (1964), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf"><i>IBM System/360 Principles of Operation</i></a> <span class="cs1-format">(PDF)</span>, First Edition, A22-6821-0</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Principles+of+Operation&rft.series=First+Edition&rft.date=1964&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2FprincOps%2FA22-6821-0_360PrincOps.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6821-7-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6821-7_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-7"><sup><i><b>h</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-8"><sup><i><b>i</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-9"><sup><i><b>j</b></i></sup></a> <a href="#cite_ref-A22-6821-7_2-10"><sup><i><b>k</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="PoOps" class="citation book cs2">IBM (September 1968), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf"><i>IBM System/360 Principles of Operation</i></a> <span class="cs1-format">(PDF)</span>, Eighth Edition, A22-6821-7</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Principles+of+Operation&rft.series=Eighth+Edition&rft.date=1968-09&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2FprincOps%2FA22-6821-7_360PrincOpsDec67.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span> Revised by <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1970" class="citation book cs2">IBM (May 12, 1970), <i>ibid.</i>, GN22-0354</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=ibid.&rft.date=1970-05-12&rft.au=IBM&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span> and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1970" class="citation book cs2">IBM (June 8, 1970), <i>ibid.</i>, GN22-0361</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=ibid.&rft.date=1970-06-08&rft.au=IBM&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6843-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6843_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6843_3-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="ChanOEMI" class="citation book cs2">IBM, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/A22-6843-3_360channelOEM.pdf"><i>IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information</i></a> <span class="cs1-format">(PDF)</span>, Fifth Edition, A22-6843-3</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+I%2FO+Interface+Channel+to+Control+Unit+Original+Equipment+Manufacturers%27+Information&rft.series=Fifth+Edition&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2FA22-6843-3_360channelOEM.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-FOOTNOTES36015[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Program_Status_Word]-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36015[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Program_Status_Word]_4-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, p. 15, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=16">Program Status Word</a>.</span> </li> <li id="cite_note-FOOTNOTES36015_–&#32,_16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Interruption]-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36015_–&#32,_16[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage16_Interruption]_5-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, pp. 15 –&#32, 16, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=16">Interruption</a>.</span> </li> <li id="cite_note-FOOTNOTES36077[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage88_Interruptions]-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36077[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage88_Interruptions]_6-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, p. 77, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=88">Interruptions</a>.</span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM_Corporation1974" class="citation book cs1">IBM Corporation (1974). <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/systemSummary/GA22-6810-12_360sysSumJan74.pdf"><i>IBM System/360 System Summary</i></a> <span class="cs1-format">(PDF)</span>. p. 3-3<span class="reference-accessdate">. Retrieved <span class="nowrap">July 16,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+System+Summary&rft.pages=3-3&rft.date=1974&rft.au=IBM+Corporation&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2FsystemSummary%2FGA22-6810-12_360sysSumJan74.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/univac/univac3/UT-2488_UNIVACIII_ref_Jun62.pdf"><i>Reference Manual UNIVAC III Data Processing System</i></a> <span class="cs1-format">(PDF)</span>, Sperry Rand Corporation, 1962, UT-2488</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Reference+Manual+UNIVAC+III+Data+Processing+System&rft.pub=Sperry+Rand+Corporation&rft.date=1962&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Funivac%2Funivac3%2FUT-2488_UNIVACIII_ref_Jun62.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6916-11"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6916_11-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6916_11-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-A22-6916_11-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1968" class="citation book cs2">IBM (June 1968), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6916-1_360-85_funcChar_Jun68.pdf"><i>IBM System/360 Model 85 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>, SECOND EDITION, A22-6916-1</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Model+85+Functional+Characteristics&rft.series=SECOND+EDITION&rft.date=1968-06&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2Ffunctional_characteristics%2FA22-6916-1_360-85_funcChar_Jun68.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6943-12"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6943_12-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6943_12-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-A22-6943_12-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-A22-6943_12-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-A22-6943_12-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1970" class="citation book cs2">IBM (August 1970), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA22-6943-1_360-195_Functional_Characteristics_197008.pdf"><i>IBM System/360 Model 195 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>, Second Edition, GA22-6943-1</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Model+195+Functional+Characteristics&rft.series=Second+Edition&rft.date=1970-08&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2Ffunctional_characteristics%2FGA22-6943-1_360-195_Functional_Characteristics_197008.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-GA27-2719-13"><span class="mw-cite-backlink">^ <a href="#cite_ref-GA27-2719_13-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-GA27-2719_13-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-GA27-2719_13-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-GA27-2719_13-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-GA27-2719_13-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-GA27-2719_13-5"><sup><i><b>f</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="GA27-2719-2" class="citation book cs2">IBM (February 1972), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf"><i>IBM System/360 Model 67 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>, Third Edition, GA27-2719-2</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Model+67+Functional+Characteristics&rft.series=Third+Edition&rft.date=1972-02&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2Ffunctional_characteristics%2FGA27-2719-2_360-67_funcChar.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6907-17"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6907_17-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6907_17-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="A22-6907-2" class="citation book cs2">IBM (1968-03-18), <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6907-2_360-91_funcChar.pdf"><i>IBM System/360 Model 91 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>, Third Edition, A22-6907-2</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Model+91+Functional+Characteristics&rft.series=Third+Edition&rft.date=1968-03-18&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2Ffunctional_characteristics%2FA22-6907-2_360-91_funcChar.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-A22-6884-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-A22-6884_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-A22-6884_20-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-A22-6884_20-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-A22-6884_20-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-A22-6884_20-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM1968" class="citation book cs2">IBM (September 1968), "Appendix A. Multiprocessing System", <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6884-3_360-65_funcChar.pdf"><i>IBM System/360 Model 65 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>, Fourth Edition, pp. 30–34, A22-6884-3</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Appendix+A.+Multiprocessing+System&rft.btitle=IBM+System%2F360+Model+65+Functional+Characteristics&rft.series=Fourth+Edition&rft.pages=30-34&rft.date=1968-09&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2Ffunctional_characteristics%2FA22-6884-3_360-65_funcChar.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation report cs1"><a rel="nofollow" class="external text" href="https://nvlpubs.nist.gov/nistpubs/Legacy/FIPS/fipspub60-2.pdf">I/O Channel Interface</a> <span class="cs1-format">(PDF)</span> (Report). <a href="/wiki/National_Technical_Information_Service" title="National Technical Information Service">National Technical Information Service</a>. July 29, 1983. FIPS PUB 60-2<span class="reference-accessdate">. Retrieved <span class="nowrap">May 18,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=report&rft.btitle=I%2FO+Channel+Interface&rft.pub=National+Technical+Information+Service&rft.date=1983-07-29&rft_id=https%3A%2F%2Fnvlpubs.nist.gov%2Fnistpubs%2FLegacy%2FFIPS%2Ffipspub60-2.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> <li id="cite_note-FOOTNOTES36093–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage105_Control_of_Input/Output_Devices]-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36093–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage105_Control_of_Input/Output_Devices]_30-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, pp. 93–98, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=105">Control of Input/Output Devices</a>.</span> </li> <li id="cite_note-FOOTNOTES36094–95[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage106_Start_I/O]-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36094–95[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage106_Start_I/O]_31-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, pp. 94–95, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=106">Start I/O</a>.</span> </li> <li id="cite_note-FOOTNOTES36095–96[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage107_Test_I/O]-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36095–96[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage107_Test_I/O]_32-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, pp. 95–96, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=107">Test I/O</a>.</span> </li> <li id="cite_note-FOOTNOTES36096–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage108_Halt_I/O]-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36096–98[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage108_Halt_I/O]_33-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, pp. 96–98, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=108">Halt I/O</a>.</span> </li> <li id="cite_note-FOOTNOTES36098[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage110_Test_Channel]-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTES36098[httpbitsaversorgpdfibm360princOpsA22-6821-7_360PrincOpsDec67pdfpage110_Test_Channel]_34-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFS360">S360</a>, p. 98, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=110">Test Channel</a>.</span> </li> <li id="cite_note-A22-6845-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-A22-6845_38-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIBM" class="citation book cs2">IBM, <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/A22-6845-2_System_360_Direct_Control_and_External_Interrupt_Features_OEM_Information.pdf"><i>IBM System/360 Direct Control and External Interrupt Features Original Equipment Manufacturers' Information</i></a> <span class="cs1-format">(PDF)</span>, Third Edition, A22-6845-2</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F360+Direct+Control+and+External+Interrupt+Features+Original+Equipment+Manufacturers%27+Information&rft.series=Third+Edition&rft.au=IBM&rft_id=http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F360%2FA22-6845-2_System_360_Direct_Control_and_External_Interrupt_Features_OEM_Information.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=39" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPrasad1989" class="citation book cs1">Prasad, N.S. (1989). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/ibmmainframesarc00pras"><i>IBM Mainframes</i></a></span>. McGraw-Hill. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0070506868" title="Special:BookSources/0070506868"><bdi>0070506868</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+Mainframes&rft.pub=McGraw-Hill&rft.date=1989&rft.isbn=0070506868&rft.aulast=Prasad&rft.aufirst=N.S.&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2Fibmmainframesarc00pras&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span> — Chapter 3 (pp. 41–110) describes the System/360 architecture.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGreiner2011" class="citation conference cs1">Greiner, Dan (August 10, 2011). <a rel="nofollow" class="external text" href="https://share.confex.com/share/117/webprogram/Handout/Session9220/IBM%20zArchitecture%20CPU%20History.pdf">"IBM z/Architecture CPU Features - A Historical Perspective"</a> <span class="cs1-format">(PDF)</span>. <a rel="nofollow" class="external text" href="https://share.confex.com/share/117/webprogram/Session9220.html"><i>Evolution of The IBM Mainframe Architecture</i></a>. <a rel="nofollow" class="external text" href="https://share.confex.com/share/117/webprogram/start.html">SHARE 117 in Orlando</a>. <a href="/wiki/SHARE_(computing)" title="SHARE (computing)">SHARE</a>. Session 9220<span class="reference-accessdate">. Retrieved <span class="nowrap">February 7,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.atitle=IBM+z%2FArchitecture+CPU+Features+-+A+Historical+Perspective&rft.btitle=Evolution+of+The+IBM+Mainframe+Architecture&rft.pub=SHARE&rft.date=2011-08-10&rft.aulast=Greiner&rft.aufirst=Dan&rft_id=https%3A%2F%2Fshare.confex.com%2Fshare%2F117%2Fwebprogram%2FHandout%2FSession9220%2FIBM%2520zArchitecture%2520CPU%2520History.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+System%2F360+architecture" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_System/360_architecture&action=edit&section=40" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/GC20-1667-1_intro360arch.pdf">Introduction to IBM System/360 Architecture</a> (Student Text)</li></ul>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=IBM_System/360_architecture&oldid=1231183488">https://en.wikipedia.org/w/index.php?title=IBM_System/360_architecture&oldid=1231183488</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Computing_platforms" title="Category:Computing platforms">Computing platforms</a></li><li><a href="/wiki/Category:IBM_System/360_mainframe_line" title="Category:IBM System/360 mainframe line">IBM System/360 mainframe line</a></li><li><a href="/wiki/Category:Computer_architecture" title="Category:Computer architecture">Computer architecture</a></li><li><a href="/wiki/Category:Computer-related_introductions_in_1964" title="Category:Computer-related introductions in 1964">Computer-related introductions in 1964</a></li></ul></div><div id="mw-hidden-catlinks" class="mw-hidden-catlinks mw-hidden-cats-hidden">Hidden categories: <ul><li><a href="/wiki/Category:Articles_with_short_description" title="Category:Articles with short description">Articles with short description</a></li><li><a href="/wiki/Category:Short_description_is_different_from_Wikidata" title="Category:Short description is different from Wikidata">Short description is different from Wikidata</a></li></ul></div></div> </div> </main> </div> <div class="mw-footer-container"> <footer id="footer" class="mw-footer" > <ul id="footer-info"> <li id="footer-info-lastmod"> This page was last edited on 26 June 2024, at 23:05<span class="anonymous-show"> (UTC)</span>.</li> <li id="footer-info-copyright">Text is available under the <a href="/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License" title="Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License">Creative Commons Attribution-ShareAlike 4.0 License</a>; additional terms may apply. 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Template:IBM_mainframes"," 8.23% 94.385 1 Template:Sidebar"," 7.55% 86.607 2 Template:Reflist"," 6.60% 75.626 1 Template:Short_description"," 4.83% 55.378 8 Template:Sfn"]},"scribunto":{"limitreport-timeusage":{"value":"0.565","limit":"10.000"},"limitreport-memusage":{"value":7959858,"limit":52428800},"limitreport-logs":"anchor_id_list = table#1 {\n [\"A22-6907-2\"] = 1,\n [\"AMWP\"] = 1,\n [\"Attention\"] = 1,\n [\"Busy\"] = 1,\n [\"CCC\"] = 1,\n [\"CCW-CC\"] = 1,\n [\"CCW-CD\"] = 1,\n [\"CCW-ChainCommand\"] = 1,\n [\"CCW-ChainData\"] = 1,\n [\"CCW-PCI\"] = 1,\n [\"CCW-ProgramControlledInterupt\"] = 1,\n [\"CCW-SKIP\"] = 1,\n [\"CCW-SLI\"] = 1,\n [\"CCW-SuppressLengthindication\"] = 1,\n [\"CDC\"] = 1,\n [\"CE\"] = 1,\n [\"CITEREFGreiner2011\"] = 1,\n [\"CITEREFIBM\"] = 1,\n [\"CITEREFIBM1964\"] = 1,\n [\"CITEREFIBM1968\"] = 2,\n [\"CITEREFIBM1970\"] = 3,\n [\"CITEREFIBM_Corporation1974\"] = 1,\n [\"CITEREFPrasad1989\"] = 1,\n [\"CITEREFS360\"] = 1,\n [\"CSW_Attention\"] = 1,\n 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