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[o]" accesskey="o"> Log in</a></li> </ul> </div> </div> <div id="p-user-menu-anon-editor" class="vector-menu mw-portlet mw-portlet-user-menu-anon-editor" > <div class="vector-menu-heading"> Pages for logged out editors <a href="/wiki/Help:Introduction" aria-label="Learn more about editing">learn more</a> </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-anoncontribs" class="mw-list-item"><a href="/wiki/Special:MyContributions" title="A list of edits made from this IP address [y]" accesskey="y">Contributions</a></li><li id="pt-anontalk" class="mw-list-item"><a href="/wiki/Special:MyTalk" title="Discussion about edits from this IP address [n]" accesskey="n">Talk</a></li> </ul> </div> </div> </div> </div> </nav> </div> </header> </div> <div class="mw-page-container"> <div class="mw-page-container-inner"> <div class="vector-sitenotice-container"> <div id="siteNotice"></div> </div> <div class="vector-column-start"> <div class="vector-main-menu-container"> <div id="mw-navigation"> <nav id="mw-panel" class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-pinned-container" class="vector-pinned-container"> </div> </nav> </div> </div> <div class="vector-sticky-pinned-container"> <nav id="mw-panel-toc" aria-label="Contents" data-event-name="ui.sidebar-toc" class="mw-table-of-contents-container vector-toc-landmark"> <div id="vector-toc-pinned-container" class="vector-pinned-container"> <div id="vector-toc" class="vector-toc vector-pinnable-element"> <div class="vector-pinnable-header vector-toc-pinnable-header vector-pinnable-header-pinned" data-feature-name="toc-pinned" data-pinnable-element-id="vector-toc" > <h2 class="vector-pinnable-header-label">Contents</h2> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-History" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#History"> <div class="vector-toc-text"> 1 History </div> </a> <ul id="toc-History-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Calling_CPUID" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Calling_CPUID"> <div class="vector-toc-text"> 2 Calling CPUID </div> </a> <button aria-controls="toc-Calling_CPUID-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Calling CPUID subsection </button> <ul id="toc-Calling_CPUID-sublist" class="vector-toc-list"> <li id="toc-EAX=0:_Highest_Function_Parameter_and_Manufacturer_ID" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=0:_Highest_Function_Parameter_and_Manufacturer_ID"> <div class="vector-toc-text"> 2.1 EAX=0: Highest Function Parameter and Manufacturer ID </div> </a> <ul id="toc-EAX=0:_Highest_Function_Parameter_and_Manufacturer_ID-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=1:_Processor_Info_and_Feature_Bits" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=1:_Processor_Info_and_Feature_Bits"> <div class="vector-toc-text"> 2.2 EAX=1: Processor Info and Feature Bits </div> </a> <ul id="toc-EAX=1:_Processor_Info_and_Feature_Bits-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=2:_Cache_and_TLB_Descriptor_Information" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=2:_Cache_and_TLB_Descriptor_Information"> <div class="vector-toc-text"> 2.3 EAX=2: Cache and TLB Descriptor Information </div> </a> <ul id="toc-EAX=2:_Cache_and_TLB_Descriptor_Information-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=3:_Processor_Serial_Number" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=3:_Processor_Serial_Number"> <div class="vector-toc-text"> 2.4 EAX=3: Processor Serial Number </div> </a> <ul id="toc-EAX=3:_Processor_Serial_Number-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=4_and_EAX=8000'001Dh:_Cache_Hierarchy_and_Topology" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=4_and_EAX=8000'001Dh:_Cache_Hierarchy_and_Topology"> <div class="vector-toc-text"> 2.5 EAX=4 and EAX=8000'001Dh: Cache Hierarchy and Topology </div> </a> <ul id="toc-EAX=4_and_EAX=8000'001Dh:_Cache_Hierarchy_and_Topology-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=4_and_EAX=Bh:_Intel_Thread/Core_and_Cache_Topology" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=4_and_EAX=Bh:_Intel_Thread/Core_and_Cache_Topology"> <div class="vector-toc-text"> 2.6 EAX=4 and EAX=Bh: Intel Thread/Core and Cache Topology </div> </a> <ul id="toc-EAX=4_and_EAX=Bh:_Intel_Thread/Core_and_Cache_Topology-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=5:_MONITOR/MWAIT_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=5:_MONITOR/MWAIT_Features"> <div class="vector-toc-text"> 2.7 EAX=5: MONITOR/MWAIT Features </div> </a> <ul id="toc-EAX=5:_MONITOR/MWAIT_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=6:_Thermal_and_Power_Management" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=6:_Thermal_and_Power_Management"> <div class="vector-toc-text"> 2.8 EAX=6: Thermal and Power Management </div> </a> <ul id="toc-EAX=6:_Thermal_and_Power_Management-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=7,_ECX=0:_Extended_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=7,_ECX=0:_Extended_Features"> <div class="vector-toc-text"> 2.9 EAX=7, ECX=0: Extended Features </div> </a> <ul id="toc-EAX=7,_ECX=0:_Extended_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=7,_ECX=1:_Extended_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=7,_ECX=1:_Extended_Features"> <div class="vector-toc-text"> 2.10 EAX=7, ECX=1: Extended Features </div> </a> <ul id="toc-EAX=7,_ECX=1:_Extended_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=7,_ECX=2:_Extended_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=7,_ECX=2:_Extended_Features"> <div class="vector-toc-text"> 2.11 EAX=7, ECX=2: Extended Features </div> </a> <ul id="toc-EAX=7,_ECX=2:_Extended_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=0Dh:_XSAVE_Features_and_State_Components" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=0Dh:_XSAVE_Features_and_State_Components"> <div class="vector-toc-text"> 2.12 EAX=0Dh: XSAVE Features and State Components </div> </a> <ul id="toc-EAX=0Dh:_XSAVE_Features_and_State_Components-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=12h:_SGX_Capabilities" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=12h:_SGX_Capabilities"> <div class="vector-toc-text"> 2.13 EAX=12h: SGX Capabilities </div> </a> <ul id="toc-EAX=12h:_SGX_Capabilities-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=14h,_ECX=0:_Processor_Trace" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=14h,_ECX=0:_Processor_Trace"> <div class="vector-toc-text"> 2.14 EAX=14h, ECX=0: Processor Trace </div> </a> <ul id="toc-EAX=14h,_ECX=0:_Processor_Trace-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=15h_and_EAX=16h:_CPU,_TSC,_Bus_and_Core_Crystal_Clock_Frequencies" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=15h_and_EAX=16h:_CPU,_TSC,_Bus_and_Core_Crystal_Clock_Frequencies"> <div class="vector-toc-text"> 2.15 EAX=15h and EAX=16h: CPU, TSC, Bus and Core Crystal Clock Frequencies </div> </a> <ul id="toc-EAX=15h_and_EAX=16h:_CPU,_TSC,_Bus_and_Core_Crystal_Clock_Frequencies-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=17h:_SoC_Vendor_Attribute_Enumeration" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=17h:_SoC_Vendor_Attribute_Enumeration"> <div class="vector-toc-text"> 2.16 EAX=17h: SoC Vendor Attribute Enumeration </div> </a> <ul id="toc-EAX=17h:_SoC_Vendor_Attribute_Enumeration-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=19h:_Intel_Key_Locker_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=19h:_Intel_Key_Locker_Features"> <div class="vector-toc-text"> 2.17 EAX=19h: Intel Key Locker Features </div> </a> <ul id="toc-EAX=19h:_Intel_Key_Locker_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=1Dh:_Tile_Information" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=1Dh:_Tile_Information"> <div class="vector-toc-text"> 2.18 EAX=1Dh: Tile Information </div> </a> <ul id="toc-EAX=1Dh:_Tile_Information-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=1Eh,_ECX=0:_TMUL_Information" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=1Eh,_ECX=0:_TMUL_Information"> <div class="vector-toc-text"> 2.19 EAX=1Eh, ECX=0: TMUL Information </div> </a> <ul id="toc-EAX=1Eh,_ECX=0:_TMUL_Information-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=1Eh,_ECX=1:_TMUL_Information" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=1Eh,_ECX=1:_TMUL_Information"> <div class="vector-toc-text"> 2.20 EAX=1Eh, ECX=1: TMUL Information </div> </a> <ul id="toc-EAX=1Eh,_ECX=1:_TMUL_Information-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=21h:_Reserved_for_TDX_enumeration" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=21h:_Reserved_for_TDX_enumeration"> <div class="vector-toc-text"> 2.21 EAX=21h: Reserved for TDX enumeration </div> </a> <ul id="toc-EAX=21h:_Reserved_for_TDX_enumeration-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=24h,_ECX=0:_AVX10_Converged_Vector_ISA" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=24h,_ECX=0:_AVX10_Converged_Vector_ISA"> <div class="vector-toc-text"> 2.22 EAX=24h, ECX=0: AVX10 Converged Vector ISA </div> </a> <ul id="toc-EAX=24h,_ECX=0:_AVX10_Converged_Vector_ISA-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=24h,_ECX=1:_Discrete_AVX10_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=24h,_ECX=1:_Discrete_AVX10_Features"> <div class="vector-toc-text"> 2.23 EAX=24h, ECX=1: Discrete AVX10 Features </div> </a> <ul id="toc-EAX=24h,_ECX=1:_Discrete_AVX10_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=2000'0000h:_Highest_Xeon_Phi_Function_Implemented" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=2000'0000h:_Highest_Xeon_Phi_Function_Implemented"> <div class="vector-toc-text"> 2.24 EAX=2000'0000h: Highest Xeon Phi Function Implemented </div> </a> <ul id="toc-EAX=2000'0000h:_Highest_Xeon_Phi_Function_Implemented-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=2000'0001h:_Xeon_Phi_Feature_Bits" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=2000'0001h:_Xeon_Phi_Feature_Bits"> <div class="vector-toc-text"> 2.25 EAX=2000'0001h: Xeon Phi Feature Bits </div> </a> <ul id="toc-EAX=2000'0001h:_Xeon_Phi_Feature_Bits-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=4000'0000h-4FFFF'FFFh:_Reserved_for_Hypervisors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=4000'0000h-4FFFF'FFFh:_Reserved_for_Hypervisors"> <div class="vector-toc-text"> 2.26 EAX=4000'0000h-4FFFF'FFFh: Reserved for Hypervisors </div> </a> <ul id="toc-EAX=4000'0000h-4FFFF'FFFh:_Reserved_for_Hypervisors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0000h:_Highest_Extended_Function_Implemented" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0000h:_Highest_Extended_Function_Implemented"> <div class="vector-toc-text"> 2.27 EAX=8000'0000h: Highest Extended Function Implemented </div> </a> <ul id="toc-EAX=8000'0000h:_Highest_Extended_Function_Implemented-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0001h:_Extended_Processor_Info_and_Feature_Bits" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0001h:_Extended_Processor_Info_and_Feature_Bits"> <div class="vector-toc-text"> 2.28 EAX=8000'0001h: Extended Processor Info and Feature Bits </div> </a> <ul id="toc-EAX=8000'0001h:_Extended_Processor_Info_and_Feature_Bits-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0002h,8000'0003h,8000'0004h:_Processor_Brand_String" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0002h,8000'0003h,8000'0004h:_Processor_Brand_String"> <div class="vector-toc-text"> 2.29 EAX=8000'0002h,8000'0003h,8000'0004h: Processor Brand String </div> </a> <ul id="toc-EAX=8000'0002h,8000'0003h,8000'0004h:_Processor_Brand_String-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0005h:_L1_Cache_and_TLB_Identifiers" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0005h:_L1_Cache_and_TLB_Identifiers"> <div class="vector-toc-text"> 2.30 EAX=8000'0005h: L1 Cache and TLB Identifiers </div> </a> <ul id="toc-EAX=8000'0005h:_L1_Cache_and_TLB_Identifiers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0006h:_Extended_L2_Cache_Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0006h:_Extended_L2_Cache_Features"> <div class="vector-toc-text"> 2.31 EAX=8000'0006h: Extended L2 Cache Features </div> </a> <ul id="toc-EAX=8000'0006h:_Extended_L2_Cache_Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0007h:_Processor_Power_Management_Information_and_RAS_Capabilities" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0007h:_Processor_Power_Management_Information_and_RAS_Capabilities"> <div class="vector-toc-text"> 2.32 EAX=8000'0007h: Processor Power Management Information and RAS Capabilities </div> </a> <ul id="toc-EAX=8000'0007h:_Processor_Power_Management_Information_and_RAS_Capabilities-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0008h:_Virtual_and_Physical_Address_Sizes" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0008h:_Virtual_and_Physical_Address_Sizes"> <div class="vector-toc-text"> 2.33 EAX=8000'0008h: Virtual and Physical Address Sizes </div> </a> <ul id="toc-EAX=8000'0008h:_Virtual_and_Physical_Address_Sizes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'000Ah:_SVM_features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'000Ah:_SVM_features"> <div class="vector-toc-text"> 2.34 EAX=8000'000Ah: SVM features </div> </a> <ul id="toc-EAX=8000'000Ah:_SVM_features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'001Fh:_Encrypted_Memory_Capabilities" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'001Fh:_Encrypted_Memory_Capabilities"> <div class="vector-toc-text"> 2.35 EAX=8000'001Fh: Encrypted Memory Capabilities </div> </a> <ul id="toc-EAX=8000'001Fh:_Encrypted_Memory_Capabilities-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8000'0021h:_Extended_Feature_Identification" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8000'0021h:_Extended_Feature_Identification"> <div class="vector-toc-text"> 2.36 EAX=8000'0021h: Extended Feature Identification </div> </a> <ul id="toc-EAX=8000'0021h:_Extended_Feature_Identification-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=8FFF'FFFFh:_AMD_Easter_Egg" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=8FFF'FFFFh:_AMD_Easter_Egg"> <div class="vector-toc-text"> 2.37 EAX=8FFF'FFFFh: AMD Easter Egg </div> </a> <ul id="toc-EAX=8FFF'FFFFh:_AMD_Easter_Egg-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=C000'0000h:_Highest_Centaur_Extended_Function" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=C000'0000h:_Highest_Centaur_Extended_Function"> <div class="vector-toc-text"> 2.38 EAX=C000'0000h: Highest Centaur Extended Function </div> </a> <ul id="toc-EAX=C000'0000h:_Highest_Centaur_Extended_Function-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EAX=C000'0001h:_Centaur_Feature_Information" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EAX=C000'0001h:_Centaur_Feature_Information"> <div class="vector-toc-text"> 2.39 EAX=C000'0001h: Centaur Feature Information </div> </a> <ul id="toc-EAX=C000'0001h:_Centaur_Feature_Information-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-CPUID_usage_from_high-level_languages" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#CPUID_usage_from_high-level_languages"> <div class="vector-toc-text"> 3 CPUID usage from high-level languages </div> </a> <button aria-controls="toc-CPUID_usage_from_high-level_languages-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle CPUID usage from high-level languages subsection </button> <ul id="toc-CPUID_usage_from_high-level_languages-sublist" class="vector-toc-list"> <li id="toc-Inline_assembly" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Inline_assembly"> <div class="vector-toc-text"> 3.1 Inline assembly </div> </a> <ul id="toc-Inline_assembly-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Wrapper_functions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Wrapper_functions"> <div class="vector-toc-text"> 3.2 Wrapper functions </div> </a> <ul id="toc-Wrapper_functions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-CPU-specific_information_outside_x86" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#CPU-specific_information_outside_x86"> <div class="vector-toc-text"> 4 CPU-specific information outside x86 </div> </a> <ul id="toc-CPU-specific_information_outside_x86-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 5 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 6 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> 7 Further reading </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 8 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button 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Available in 11 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-11" aria-hidden="true" > 11 languages </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B9%D8%B1%D9%81_%D9%88%D8%AD%D8%AF%D8%A9_%D8%A7%D9%84%D9%85%D8%B9%D8%A7%D9%84%D8%AC%D8%A9_%D8%A7%D9%84%D9%85%D8%B1%D9%83%D8%B2%D9%8A%D8%A9" title="معرف وحدة المعالجة المركزية – Arabic" lang="ar" hreflang="ar" data-title="معرف وحدة المعالجة المركزية" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target">العربية</a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/CPUID" title="CPUID – Catalan" lang="ca" hreflang="ca" data-title="CPUID" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target">Català</a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/CPUID" title="CPUID – Czech" lang="cs" hreflang="cs" data-title="CPUID" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target">Čeština</a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/CPUID" title="CPUID – German" lang="de" hreflang="de" data-title="CPUID" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target">Deutsch</a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/CPUID" title="CPUID – French" lang="fr" hreflang="fr" data-title="CPUID" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target">Français</a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/CPUID" title="CPUID – Korean" lang="ko" hreflang="ko" data-title="CPUID" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target">한국어</a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/CPUID" title="CPUID – Italian" lang="it" hreflang="it" data-title="CPUID" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target">Italiano</a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/CPUID" title="CPUID – Japanese" lang="ja" hreflang="ja" data-title="CPUID" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target">日本語</a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/CPUID" title="CPUID – Russian" lang="ru" hreflang="ru" data-title="CPUID" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target">Русский</a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/CPUID" title="CPUID – Ukrainian" lang="uk" hreflang="uk" data-title="CPUID" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target">Українська</a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/CPUID" title="CPUID – Chinese" lang="zh" hreflang="zh" data-title="CPUID" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target">中文</a></li> </ul> <div class="after-portlet after-portlet-lang"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q1024235#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></div> </div> </div> </div> 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id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Instruction for x86 microprocessors</div> In the <a href="/wiki/X86" title="X86">x86</a> architecture, the CPUID instruction (identified by a <code>CPUID</code> <a href="/wiki/Opcode" title="Opcode">opcode</a>) is a <a href="/wiki/Processor_supplementary_instruction" class="mw-redirect" title="Processor supplementary instruction">processor supplementary instruction</a> (its name derived from <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> Identification) allowing software to discover details of the processor. It was introduced by <a href="/wiki/Intel" title="Intel">Intel</a> in 1993 with the launch of the <a href="/wiki/Pentium" title="Pentium">Pentium</a> and <a href="/wiki/SL-enhanced_486" class="mw-redirect" title="SL-enhanced 486">SL-enhanced 486</a> processors.<a href="#cite_note-1">[1]</a> A program can use the <code>CPUID</code> to determine processor type and whether features such as <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>/<a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> are implemented. <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=1" title="Edit section: History">edit</a>]</div> Prior to the general availability of the <code>CPUID</code> instruction, programmers would write esoteric <a href="/wiki/Machine_code" title="Machine code">machine code</a> which exploited minor differences in CPU behavior in order to determine the processor make and model.<a href="#cite_note-2">[2]</a><a href="#cite_note-3">[3]</a><a href="#cite_note-debs_cpuident-4">[4]</a><a href="#cite_note-5">[5]</a> With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value. Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present. For example, in the Motorola 680x0 family — which never had a <code>CPUID</code> instruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In the <a href="/wiki/Motorola_68010" title="Motorola 68010">Motorola 68010</a> the instruction MOVE from SR became privileged. This notable instruction (and state machine) change allowed the 68010 to meet the <a href="/wiki/Popek_and_Goldberg_virtualization_requirements" title="Popek and Goldberg virtualization requirements">Popek and Goldberg virtualization requirements</a>. Because the 68000 offered an unprivileged MOVE from SR the 2 different CPUs could be told apart by a CPU error condition being triggered. While the <code>CPUID</code> instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 <code>CPUID</code> instruction. <div class="mw-heading mw-heading2"><h2 id="Calling_CPUID">Calling CPUID</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=2" title="Edit section: Calling CPUID">edit</a>]</div> The <code>CPUID</code> opcode is <code>0F A2</code>. In <a href="/wiki/Assembly_language" title="Assembly language">assembly language</a>, the <code>CPUID</code> instruction takes no parameters as <code>CPUID</code> implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. <code>CPUID</code> should be called with <code>EAX = 0</code> first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements. To obtain extended function information <code>CPUID</code> should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call <code>CPUID</code> with <code>EAX = 80000000h</code>. CPUID leaves greater than 3 but less than 80000000 are accessible only when the <a href="/wiki/Model-specific_register" title="Model-specific register">model-specific registers</a> have IA32_MISC_ENABLE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests, <a href="/wiki/Windows_NT_4.0" title="Windows NT 4.0">Windows NT 4.0</a> until SP6 did not boot properly unless this bit was set,<a href="#cite_note-6">[6]</a> but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. As of April 2024<a class="external text" href="https://en.wikipedia.org/w/index.php?title=CPUID&action=edit">[update]</a>, basic valid leaves go up to 23h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved". Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling <code>CPUID</code>. <div class="mw-heading mw-heading3"><h3 id="EAX=0:_Highest_Function_Parameter_and_Manufacturer_ID"><a href="/wiki/X86#32-bit" title="X86">EAX</a>=0: Highest Function Parameter and Manufacturer ID</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=3" title="Edit section: EAX=0: Highest Function Parameter and Manufacturer ID">edit</a>]</div> This returns the CPU's manufacturer ID string – a twelve-character <a href="/wiki/ASCII" title="ASCII">ASCII</a> string stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (the largest value that EAX can be set to before calling <code>CPUID</code>) is returned in EAX. Here is a list of processors and the highest function implemented. <table class="wikitable"> <caption>Highest Function Parameter </caption> <tbody><tr> <th>Processors</th> <th>Basic</th> <th>Extended </th></tr> <tr> <td>Earlier <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">Intel 486</a></td> <td colspan="2">CPUID Not Implemented </td></tr> <tr> <td>Later Intel 486 and <a href="/wiki/Pentium" title="Pentium">Pentium</a></td> <td>0x01</td> <td>Not Implemented </td></tr> <tr> <td><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a> and <a href="/wiki/Celeron" title="Celeron">Celeron</a></td> <td>0x02</td> <td>Not Implemented </td></tr> <tr> <td><a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a></td> <td>0x03</td> <td>Not Implemented </td></tr> <tr> <td><a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a></td> <td>0x02</td> <td>0x8000 0004 </td></tr> <tr> <td><a href="/wiki/Xeon" title="Xeon">Xeon</a></td> <td>0x02</td> <td>0x8000 0004 </td></tr> <tr> <td><a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a></td> <td>0x02</td> <td>0x8000 0004 </td></tr> <tr> <td>Pentium 4 with <a href="/wiki/Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a></td> <td>0x05</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a> (8xx)</td> <td>0x05</td> <td>0x8000 0008 </td></tr> <tr> <td>Pentium D (9xx)</td> <td>0x06</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Intel_Core#Core_2_Duo" title="Intel Core">Core Duo</a></td> <td>0x0A</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Intel_Core#Core_2_Duo" title="Intel Core">Core 2 Duo</a></td> <td>0x0A</td> <td>0x8000 0008 </td></tr> <tr> <td>Xeon <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#Xeon_3000-series_(uniprocessor)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">3000</a>, 5100, 5200, 5300, 5400 (<a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#Xeon_5000-series_(dual-processor)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">5000 series</a>)</td> <td>0x0A</td> <td>0x8000 0008 </td></tr> <tr> <td>Core 2 Duo <a href="/wiki/Wolfdale_(microprocessor)#Wolfdale" title="Wolfdale (microprocessor)">8000 series</a></td> <td>0x0D</td> <td>0x8000 0008 </td></tr> <tr> <td>Xeon 5200, 5400 series</td> <td>0x0A</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></td> <td>0x0A</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>-based processors</td> <td>0x0B</td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a>-based processors </td> <td>0x0D </td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>-based processors (proc base & max freq; Bus ref. freq) </td> <td>0x16 </td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/System_on_a_chip" title="System on a chip">System-On-Chip</a> Vendor Attribute Enumeration Main Leaf </td> <td>0x17 </td> <td>0x8000 0008 </td></tr> <tr> <td><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a>-based processors </td> <td>0x23 </td> <td>0x8000 0008 </td></tr></tbody></table> The following are known processor manufacturer ID strings: <ul><li><code>"AuthenticAMD"</code> – <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a></li> <li><code>"CentaurHauls"</code> – <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">IDT</a> WinChip/<a href="/wiki/Centaur_Technology" title="Centaur Technology">Centaur</a> (Including some VIA and Zhaoxin CPUs)</li> <li><code>"CyrixInstead"</code> – <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a>/early <a href="/wiki/STMicroelectronics" title="STMicroelectronics">STMicroelectronics</a> and <a href="/wiki/IBM" title="IBM">IBM</a></li> <li><code>"GenuineIntel"</code> – <a href="/wiki/Intel" title="Intel">Intel</a></li> <li><code>"GenuineIotel"</code> – Intel (rare)<a href="#cite_note-7">[7]</a><a href="#cite_note-8">[8]</a></li> <li><code>"TransmetaCPU"</code> – <a href="/wiki/Transmeta" title="Transmeta">Transmeta</a></li> <li><code>"GenuineTMx86"</code> – <a href="/wiki/Transmeta" title="Transmeta">Transmeta</a></li> <li><code>"Geode by NSC"</code> – <a href="/wiki/National_Semiconductor" title="National Semiconductor">National Semiconductor</a></li> <li><code>"NexGenDriven"</code> – <a href="/wiki/NexGen" title="NexGen">NexGen</a></li> <li><code>"RiseRiseRise"</code> – <a href="/wiki/Rise_Technology" title="Rise Technology">Rise</a></li> <li><code>"SiS SiS SiS "</code> – <a href="/wiki/Silicon_Integrated_Systems" title="Silicon Integrated Systems">SiS</a></li> <li><code>"UMC UMC UMC "</code> – <a href="/wiki/United_Microelectronics_Corporation" title="United Microelectronics Corporation">UMC</a></li> <li><code>"Vortex86 SoC"</code> – DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a></li> <li><code>"  Shanghai  "</code> – <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a></li> <li><code>"HygonGenuine"</code> – <a href="/wiki/AMD%E2%80%93Chinese_joint_venture" title="AMD–Chinese joint venture">Hygon</a></li> <li><code>"Genuine  RDC"</code> – RDC Semiconductor Co. Ltd.<a href="#cite_note-9">[9]</a></li> <li><code>"E2K MACHINE"</code> – <a href="/wiki/Elbrus_(computer)" title="Elbrus (computer)">MCST Elbrus</a><a href="#cite_note-inxi197_elbrus-10">[10]</a></li> <li><code>"VIA VIA VIA "</code> – <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA</a>[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>]</li> <li><code>"AMD ISBETTER"</code> – early engineering samples of <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a> processor<a href="#cite_note-11">[11]</a><a href="#cite_note-12">[12]</a>[<a href="/wiki/Wikipedia:NOTRS" class="mw-redirect" title="Wikipedia:NOTRS">better source needed</a>]</li></ul> The following are ID strings used by open source <a href="/wiki/Soft_microprocessor" title="Soft microprocessor">soft CPU cores</a>: <ul><li><code>"GenuineAO486"</code> – ao486 CPU (old)<a href="#cite_note-13">[13]</a><a href="#cite_note-:1-14">[14]</a></li> <li><code>"MiSTer AO486"</code> – ao486 CPU (new)<a href="#cite_note-15">[15]</a><a href="#cite_note-:1-14">[14]</a></li> <li><code>"GenuineIntel"</code> – v586 core<a href="#cite_note-16">[16]</a> (this is identical to the Intel ID string)</li></ul> The following are known ID strings from virtual machines: <ul><li><code>"MicrosoftXTA"</code> – Microsoft x86-to-ARM<a href="#cite_note-17">[17]</a></li> <li><code>"GenuineIntel"</code> – <a href="/wiki/Rosetta_(software)" title="Rosetta (software)">Apple Rosetta 2</a><a href="#cite_note-18">[18]</a></li> <li><code>"VirtualApple"</code> – Newer versions of Apple Rosetta 2</li> <li><code>"PowerVM Lx86"</code> – <a href="/wiki/PowerVM_Lx86" title="PowerVM Lx86">PowerVM Lx86</a> (x86 emulator for IBM <a href="/wiki/POWER5" title="POWER5">POWER5</a>/<a href="/wiki/POWER6" title="POWER6">POWER6</a> processors)<a href="#cite_note-19">[19]</a></li></ul> <div style="width:100%; height:1em; clear:both;"></div> For instance, on a <code>GenuineIntel</code> processor, values returned in EBX is <code>0x756e6547</code>, EDX is <code>0x49656e69</code> and ECX is <code>0x6c65746e</code>. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements. <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr mw-highlight-lines" dir="ltr"><pre> .intel_syntax noprefix .text .m0: .string "CPUID: %x\n" .m1: .string "Largest basic function number implemented: %i\n" .m2: .string "Vendor ID: %s\n" .globl main main: push r12 mov eax, 1 sub rsp, 16 cpuid lea rdi, .m0[rip] mov esi, eax call printf mov eax, 0 cpuid lea rdi, .m1[rip] mov esi, eax mov r12d, edx mov ebp, ecx call printf mov 3[rsp], ebx lea rsi, 3[rsp] lea rdi, .m2[rip] mov 7[rsp], r12d mov 11[rsp], ebp call printf add rsp, 16 pop r12 ret .section .note.GNU-stack,"",@progbits </pre></div> On some processors, it is possible to modify the Manufacturer ID string reported by CPUID.(EAX=0) by writing a new ID string to particular MSRs (<a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific registers</a>) using the <code>WRMSR</code> instruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return the <code>GenuineIntel</code> ID string.<a href="#cite_note-20">[20]</a> Processors that are known to possess such MSRs include: <table class="wikitable"> <caption>Processors with Manufacturer ID MSRs </caption> <tbody><tr> <th>Processor</th> <th>MSRs </th></tr> <tr> <td>IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a></td> <td><code>108h-109h</code><a href="#cite_note-21">[21]</a> </td></tr> <tr> <td><a href="/wiki/VIA_C3" title="VIA C3">VIA C3</a>, <a href="/wiki/VIA_C7" title="VIA C7">C7</a></td> <td><code>1108h-1109h</code><a href="#cite_note-22">[22]</a> </td></tr> <tr> <td><a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a></td> <td><code>1206h-1207h</code><a href="#cite_note-23">[23]</a> </td></tr> <tr> <td><a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Transmeta Crusoe</a>, <a href="/wiki/Transmeta_Efficeon" title="Transmeta Efficeon">Efficeon</a></td> <td><code>80860001h-80860003h</code><a href="#cite_note-transmeta_msr-24">[24]</a><a href="#cite_note-25">[25]</a> </td></tr> <tr> <td>AMD <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode</a> GX, LX</td> <td><code>3000h-3001h</code><a href="#cite_note-26">[26]</a> </td></tr> <tr> <td>DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a>EX2</td> <td><code>52444300h-52444301h</code><a href="#cite_note-27">[27]</a> </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=1:_Processor_Info_and_Feature_Bits">EAX=1: Processor Info and Feature Bits</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=4" title="Edit section: EAX=1: Processor Info and Feature Bits">edit</a>]</div> This returns the CPU's <a href="/wiki/Stepping_(version_numbers)" class="mw-redirect" title="Stepping (version numbers)">stepping</a>, model, and family information in register EAX (also called the signature of a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.<a href="#cite_note-28">[28]</a> <table class="wikitable" style="margin-left: auto; margin-right: auto; border: none;"> <caption>CPUID EAX=1: Processor Version Information in EAX </caption> <tbody><tr> <th colspan="32">EAX </th></tr> <tr> <th style="width: 75px">31 </th> <th style="width: 75px">30 </th> <th style="width: 75px">29 </th> <th style="width: 75px">28 </th> <th style="width: 75px">27 </th> <th style="width: 75px">26 </th> <th style="width: 75px">25 </th> <th style="width: 75px">24 </th> <th style="width: 75px">23 </th> <th style="width: 75px">22 </th> <th style="width: 75px">21 </th> <th style="width: 75px">20 </th> <th style="width: 75px">19 </th> <th style="width: 75px">18 </th> <th style="width: 75px">17 </th> <th style="width: 75px">16 </th> <th style="width: 75px">15 </th> <th style="width: 75px">14 </th> <th style="width: 75px">13 </th> <th style="width: 75px">12 </th> <th style="width: 75px">11 </th> <th style="width: 75px">10 </th> <th style="width: 75px">9 </th> <th style="width: 75px">8 </th> <th style="width: 75px">7 </th> <th style="width: 75px">6 </th> <th style="width: 75px">5 </th> <th style="width: 75px">4 </th> <th style="width: 75px">3 </th> <th style="width: 75px">2 </th> <th style="width: 75px">1 </th> <th style="width: 75px">0 </th></tr> <tr style="text-align: center"> <td colspan="4" style="background: lightgrey">Reserved </td> <td colspan="8">Extended Family ID </td> <td colspan="4">Extended Model ID </td> <td colspan="2" style="background: lightgrey">Reserved </td> <td colspan="2">Processor Type </td> <td colspan="4">Family ID </td> <td colspan="4">Model </td> <td colspan="4">Stepping ID </td></tr></tbody></table> <ul><li>Stepping ID is a product revision number assigned due to fixed <a href="/wiki/Errata" class="mw-redirect" title="Errata">errata</a> or other changes.</li> <li>The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.</li> <li>The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to the value of the Family ID field.</li> <li>The meaning of the Processor Type field is given in the table below.</li></ul> <table class="wikitable"> <caption>Processor Type </caption> <tbody><tr> <th>Type </th> <th>Encoding in <a href="/wiki/Binary_number" title="Binary number">Binary</a> </th></tr> <tr> <td>Original equipment manufacturer (<a href="/wiki/Original_equipment_manufacturer" title="Original equipment manufacturer">OEM</a>) Processor </td> <td style="text-align: center">00 </td></tr> <tr> <td><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">Intel Overdrive Processor</a> </td> <td style="text-align: center">01 </td></tr> <tr> <td>Dual processor (applicable to Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">P5 Pentium</a> processors only)<a href="#cite_note-29">[29]</a> </td> <td style="text-align: center">10 </td></tr> <tr> <td>Reserved value </td> <td style="text-align: center">11 </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> As of October 2023, the following x86 processor family IDs are known:<a href="#cite_note-30">[30]</a> <table class="wikitable"> <caption>CPUID EAX=1: Processor Family IDs </caption> <tbody><tr> <th>Family ID + Extended Family ID</th> <th>Intel</th> <th>AMD</th> <th>Other </th></tr> <tr> <th><code>0h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>1h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>2h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>3h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><a href="#cite_note-31">[a]</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>4h</code> </th> <td><a href="/wiki/I486" title="I486">486</a> </td> <td><a href="/wiki/Am486" title="Am486">486</a>,<a href="#cite_note-32">[31]</a> <a href="/wiki/Am5x86" title="Am5x86">5x86</a>, <a href="/wiki/AMD_%C3%89lan" title="AMD Élan">Élan</a> SC4xx/5xx<a href="#cite_note-33">[32]</a> </td> <td><a href="/wiki/Cyrix_5x86" title="Cyrix 5x86">Cyrix 5x86</a>,<a href="#cite_note-34">[33]</a> Cyrix <a href="/wiki/MediaGX" title="MediaGX">MediaGX</a>,<a href="#cite_note-cyrix_detguide-35">[34]</a> <a href="/wiki/UMC_Green_CPU" title="UMC Green CPU">UMC Green CPU</a>,<a href="#cite_note-debs_cpuident-4">[4]</a> <a href="/wiki/MCST" title="MCST">MCST</a> Elbrus (most models),<a href="#cite_note-inxi197_elbrus-10">[10]</a> <a href="/wiki/MiSTer" title="MiSTer">MiSTer</a> ao486<a href="#cite_note-36">[35]</a> </td></tr> <tr> <th><code>5h</code> </th> <td><a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, <a href="/wiki/Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a>, <a href="/wiki/Intel_Quark" title="Intel Quark">Quark X1000</a> </td> <td><a href="/wiki/AMD_K5" title="AMD K5">K5</a>, <a href="/wiki/AMD_K6" title="AMD K6">K6</a> </td> <td><a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a>, Cyrix <a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>,<a href="#cite_note-cyrix_detguide-35">[34]</a> <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode</a> (except NX), <a href="/wiki/NexGen" title="NexGen">NexGen</a> Nx586,<a href="#cite_note-debs_cpuident-4">[4]</a> IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a>, IDT WinChip 2, IDT WinChip 3, <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Transmeta Crusoe</a>, Rise <a href="/wiki/MP6" title="MP6">mP6</a>, <a href="/wiki/Silicon_Integrated_Systems" title="Silicon Integrated Systems">SiS</a> 550, DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a> (early),<a href="#cite_note-37">[36]</a> RDC IAD 100, <a href="/wiki/MCST" title="MCST">MCST</a> Elbrus-8C2<a href="#cite_note-inxi197_elbrus-10">[10]</a> </td></tr> <tr> <th><code>6h</code> </th> <td><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>, <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a>, <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a>, <a href="/wiki/Intel_Core" title="Intel Core">Intel Core</a> (all variants), <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a> (all variants), <a href="/wiki/Xeon" title="Xeon">Xeon</a> (except NetBurst <a href="/wiki/List_of_Intel_Xeon_processors_(NetBurst-based)" title="List of Intel Xeon processors (NetBurst-based)">variants</a>), <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> (except KNC) </td> <td>K7: <a href="/wiki/Athlon" title="Athlon">Athlon</a>, <a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon XP</a> </td> <td><a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a>MX/MII, <a href="/wiki/VIA_C3" title="VIA C3">VIA C3</a>, <a href="/wiki/VIA_C7" title="VIA C7">VIA C7</a>, <a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a>, DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a> (DX3,EX2<a href="#cite_note-38">[37]</a>), <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> ZX-A/B/C/C+, (<a href="/wiki/Centaur_Technology#CNS_core" title="Centaur Technology">Centaur CNS</a><a href="#cite_note-39">[38]</a>), <a href="/wiki/MCST" title="MCST">MCST</a> Elbrus-12C/16C/2C3<a href="#cite_note-inxi197_elbrus-10">[10]</a> </td></tr> <tr> <th><code>7h</code> </th> <td><a href="/wiki/Itanium" title="Itanium">Itanium</a> (in IA-32 mode) </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> KaiXian, <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> KaisHeng </td></tr> <tr> <th><code>8h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><a href="#cite_note-41">[b]</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>9h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Ah</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Bh</code> </th> <td><a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> (Knights Corner)<a href="#cite_note-intel_knc_ref-42">[40]</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Ch</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Dh</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Eh</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>0Fh</code> </th> <td><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a> (Pentium 4) </td> <td>K8/Hammer (<a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a>) </td> <td><a href="/wiki/Transmeta_Efficeon" title="Transmeta Efficeon">Transmeta Efficeon</a> </td></tr> <tr> <th><code>10h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/AMD_10h" title="AMD 10h">K10</a>: <a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>11h</code> </th> <td><a href="/wiki/Itanium_2" class="mw-redirect" title="Itanium 2">Itanium 2</a><a href="#cite_note-43">[41]</a> (in IA-32 mode)</td> <td><a href="/wiki/AMD_10h#Family_11h_and_12h_derivatives" title="AMD 10h">Turion X2</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>12h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/AMD_10h#Family_11h_and_12h_derivatives" title="AMD 10h">Llano</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>13h</code> </th> <td><a href="/wiki/Intel_Core" title="Intel Core">Intel Core</a> (Panther Cove and up)<a href="#cite_note-44">[42]</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>14h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>15h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a>, <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a>, <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a>, <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>16h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>, <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>17h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a>, <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>18h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="2" style="text-align:center"><a href="/wiki/AMD%E2%80%93Chinese_joint_venture" title="AMD–Chinese joint venture">Hygon Dhyana</a> </td></tr> <tr> <th><code>19h</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a>, <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><code>1Ah</code> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>(<a href="/wiki/Zen_5" title="Zen 5">Zen 5</a>)</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-31"><a href="#cite_ref-31">^</a> The <a href="/wiki/I386" title="I386">i386</a> processor does not support the <code>CPUID</code> instruction - it does however return Family ID <code>3h</code> in the reset-value of EDX. </li> <li id="cite_note-41"><a href="#cite_ref-41">^</a> Family ID <code>8h</code> has been reported to have been deliberately avoided for the Pentium 4 processor family due to incompatibility with Windows NT 4.0.<a href="#cite_note-40">[39]</a> </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <table class="wikitable"> <caption>CPUID EAX=1: Additional Information in EBX </caption> <tbody><tr> <th>Bits </th> <th>EBX </th> <th>Valid </th></tr> <tr> <th>7:0 </th> <td>Brand Index </td> <td> </td></tr> <tr> <th>15:8 </th> <td><code>CLFLUSH</code> line size (Value * 8 = cache line size in bytes) </td> <td>if <code>CLFLUSH</code> feature flag is set. CPUID.01.EDX.CLFSH [bit 19]= 1 </td></tr> <tr> <th>23:16 </th> <td>Maximum number of addressable IDs for logical processors in this physical package; The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.<a href="#cite_note-47">[a]</a> Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.<a href="#cite_note-48">[45]</a> </td> <td>if <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> feature flag is set. CPUID.01.EDX.HTT [bit 28]= 1 </td></tr> <tr> <th>31:24 </th> <td>Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.<a href="#cite_note-49">[b]</a> </td> <td>Pentium 4 and subsequent processors. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-47"><a href="#cite_ref-47">^</a> On CPUs with more than 128 logical processors in a single package (e.g. Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> 7290<a href="#cite_note-45">[43]</a> and AMD <a href="/wiki/List_of_AMD_Ryzen_processors#Storm_Peak_desktop" title="List of AMD Ryzen processors">Threadripper Pro 7995WX</a><a href="#cite_note-46">[44]</a>) the value in bit 23:16 is set to a non-power-of-2 value. </li> <li id="cite_note-49"><a href="#cite_ref-49">^</a> The Local APIC ID can also be identified via the cpuid 0Bh leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). On CPUs with more than 256 logical processors in one package (e.g. Xeon Phi 7290), leaf 0Bh must be used because the APIC ID does not fit into 8 bits. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility. <table class="wikitable"> <caption>CPUID EAX=1: Feature Information in EDX and ECX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EDX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">ECX<a href="#cite_note-52">[a]</a> </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature</th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>fpu</td> <td>Onboard <a href="/wiki/X87" title="X87">x87</a> FPU </td> <td>sse3</td> <td>SSE3 (<a href="/wiki/Prescott_New_Instructions" class="mw-redirect" title="Prescott New Instructions">Prescott New Instructions</a> - PNI) </td> <th>0 </th></tr> <tr> <th>1 </th> <td>vme</td> <td><a href="/wiki/Virtual_8086_Mode_Extensions" class="mw-redirect" title="Virtual 8086 Mode Extensions">Virtual 8086 mode extensions</a> (such as VIF, VIP, PVI) </td> <td>pclmulqdq</td> <td><code><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">PCLMULQDQ</a></code> (carry-less multiply) instruction </td> <th>1 </th></tr> <tr> <th>2 </th> <td>de</td> <td>Debugging extensions (<a href="/wiki/Control_register#CR4" title="Control register">CR4</a> bit 3) </td> <td>dtes64</td> <td>64-bit debug store (edx bit 21) </td> <th>2 </th></tr> <tr> <th>3 </th> <td>pse</td> <td><a href="/wiki/Page_Size_Extension" title="Page Size Extension">Page Size Extension</a> (4 MB pages) </td> <td>monitor</td> <td><code>MONITOR</code> and <code>MWAIT</code> instructions (<a href="/wiki/Prescott_New_Instructions" class="mw-redirect" title="Prescott New Instructions">PNI</a>) </td> <th>3 </th></tr> <tr> <th>4 </th> <td>tsc</td> <td><a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> and <code>RDTSC</code> instruction </td> <td>ds-cpl</td> <td>CPL qualified debug store </td> <th>4 </th></tr> <tr> <th>5 </th> <td>msr</td> <td><a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific registers</a> and <code>RDMSR</code>/<code>WRMSR</code> instructions </td> <td>vmx</td> <td><a href="/wiki/X86_virtualization" title="X86 virtualization">Virtual Machine eXtensions</a> </td> <th>5 </th></tr> <tr> <th>6 </th> <td>pae</td> <td><a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">Physical Address Extension</a> </td> <td>smx</td> <td>Safer Mode Extensions (<a href="/wiki/LaGrande" class="mw-redirect" title="LaGrande">LaGrande</a>) (<code>GETSEC</code> instruction) </td> <th>6 </th></tr> <tr> <th>7 </th> <td>mce</td> <td><a href="/wiki/Machine_Check_Exception" class="mw-redirect" title="Machine Check Exception">Machine Check Exception</a> </td> <td>est</td> <td>Enhanced <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> </td> <th>7 </th></tr> <tr> <th>8 </th> <td>cx8<a href="#cite_note-54">[b]</a></td> <td><code>CMPXCHG8B</code> (<a href="/wiki/Compare-and-swap" title="Compare-and-swap">compare-and-swap</a>) instruction </td> <td>tm2</td> <td><a href="/wiki/Thermal_Monitor_2" title="Thermal Monitor 2">Thermal Monitor 2</a> </td> <th>8 </th></tr> <tr> <th>9 </th> <td>apic<a href="#cite_note-56">[c]</a></td> <td>Onboard <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">Advanced Programmable Interrupt Controller</a> </td> <td>ssse3</td> <td><a href="/wiki/SSSE3" title="SSSE3">Supplemental SSE3</a> instructions </td> <th>9 </th></tr> <tr> <th>10 </th> <td style="background:lightgrey;">(mtrr)<a href="#cite_note-58">[d]</a> </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td>cnxt-id</td> <td>L1 Context ID </td> <th>10 </th></tr> <tr> <th>11 </th> <td>sep<a href="#cite_note-60">[e]</a></td> <td><code>SYSENTER</code> and <code>SYSEXIT</code> fast system call instructions </td> <td>sdbg</td> <td>Silicon Debug interface </td> <th>11 </th></tr> <tr> <th>12 </th> <td>mtrr</td> <td><a href="/wiki/Memory_Type_Range_Registers" class="mw-redirect" title="Memory Type Range Registers">Memory Type Range Registers</a> </td> <td>fma</td> <td><a href="/wiki/FMA_instruction_set" title="FMA instruction set">Fused multiply-add</a> (FMA3) </td> <th>12 </th></tr> <tr> <th>13 </th> <td>pge</td> <td><a href="/wiki/Page_table" title="Page table">Page</a> Global Enable bit in <a href="/wiki/Control_register#CR4" title="Control register">CR4</a> </td> <td>cx16</td> <td><code>CMPXCHG16B</code> instruction </td> <th>13 </th></tr> <tr> <th>14 </th> <td>mca</td> <td><a href="/wiki/Machine_check_architecture" class="mw-redirect" title="Machine check architecture">Machine check architecture</a> </td> <td>xtpr</td> <td>Can disable sending task priority messages </td> <th>14 </th></tr> <tr> <th>15 </th> <td>cmov</td> <td>Conditional move: <code>CMOV</code>, <code><a href="/wiki/FCMOV" title="FCMOV">FCMOV</a></code> and <code>FCOMI</code> instructions<a href="#cite_note-61">[f]</a> </td> <td>pdcm</td> <td>Perfmon & debug capability </td> <th>15 </th></tr> <tr> <th>16 </th> <td>pat</td> <td><a href="/wiki/Page_Attribute_Table" class="mw-redirect" title="Page Attribute Table">Page Attribute Table</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved)<a href="#cite_note-63">[g]</a> </td> <th>16 </th></tr> <tr> <th>17 </th> <td>pse-36</td> <td><a href="/wiki/PSE-36" title="PSE-36">36-bit page size extension</a> </td> <td>pcid</td> <td><a href="/wiki/Process_context_identifiers" class="mw-redirect" title="Process context identifiers">Process context identifiers</a> (<a href="/wiki/Control_register#CR4" title="Control register">CR4</a> bit 17) </td> <th>17 </th></tr> <tr> <th>18 </th> <td>psn</td> <td><a href="/wiki/Processor_Serial_Number#Controversy_about_privacy_issues" class="mw-redirect" title="Processor Serial Number">Processor Serial Number</a> supported and enabled<a href="#cite_note-64">[h]</a> </td> <td>dca</td> <td>Direct cache access for DMA writes<a href="#cite_note-65">[53]</a><a href="#cite_note-66">[54]</a> </td> <th>18 </th></tr> <tr> <th>19 </th> <td>clfsh</td> <td><code>CLFLUSH</code> cache line flush instruction (<a href="/wiki/SSE2" title="SSE2">SSE2</a>) </td> <td>sse4.1</td> <td><a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a> instructions </td> <th>19 </th></tr> <tr> <th>20 </th> <td>(nx)</td> <td><a href="/wiki/NX_bit" title="NX bit">No-execute (NX) bit</a> (<a href="/wiki/Itanium" title="Itanium">Itanium</a> only)<a href="#cite_note-ia64_sdm-67">[55]</a><a href="#cite_note-68">[i]</a> </td> <td>sse4.2</td> <td><a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a> instructions </td> <th>20 </th></tr> <tr> <th>21 </th> <td>ds</td> <td>Debug store: save trace of executed jumps </td> <td>x2apic</td> <td><a href="/wiki/X2APIC" class="mw-redirect" title="X2APIC">x2APIC</a> (enhanced APIC) </td> <th>21 </th></tr> <tr> <th>22 </th> <td>acpi</td> <td>Onboard thermal control MSRs for <a href="/wiki/Advanced_Configuration_and_Power_Interface" class="mw-redirect" title="Advanced Configuration and Power Interface">ACPI</a> </td> <td>movbe</td> <td><code>MOVBE</code> instruction (<a href="/wiki/Big-endian" class="mw-redirect" title="Big-endian">big-endian</a>) </td> <th>22 </th></tr> <tr> <th>23 </th> <td>mmx</td> <td><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> instructions (64-bit SIMD) </td> <td>popcnt</td> <td><code><a href="/wiki/Popcnt" class="mw-redirect" title="Popcnt">POPCNT</a></code> instruction </td> <th>23 </th></tr> <tr> <th>24 </th> <td>fxsr</td> <td><code>FXSAVE</code>, <code>FXRSTOR</code> instructions, <a href="/wiki/Control_register#CR4" title="Control register">CR4</a> bit 9 </td> <td>tsc-deadline</td> <td>APIC implements one-shot operation using a TSC deadline value </td> <th>24 </th></tr> <tr> <th>25 </th> <td>sse</td> <td><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE) instructions (aka "<a href="/wiki/Katmai_(microprocessor)" class="mw-redirect" title="Katmai (microprocessor)">Katmai</a> New Instructions"; 128-bit SIMD) </td> <td>aes-ni</td> <td><a href="/wiki/AES_instruction_set" title="AES instruction set">AES instruction set</a> </td> <th>25 </th></tr> <tr> <th>26 </th> <td>sse2</td> <td><a href="/wiki/SSE2" title="SSE2">SSE2</a> instructions </td> <td>xsave</td> <td>Extensible processor state save/restore: <code>XSAVE</code>, <code>XRSTOR</code>, <code>XSETBV</code>, <code>XGETBV</code> instructions </td> <th>26 </th></tr> <tr> <th>27 </th> <td>ss</td> <td>CPU cache implements self-<a href="/wiki/Cache_snooping" class="mw-redirect" title="Cache snooping">snoop</a> </td> <td>osxsave</td> <td><code>XSAVE</code> enabled by OS </td> <th>27 </th></tr> <tr> <th>28 </th> <td>htt</td> <td>Max APIC IDs reserved field is Valid<a href="#cite_note-71">[j]</a> </td> <td>avx</td> <td><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (256-bit SIMD) </td> <th>28 </th></tr> <tr> <th>29 </th> <td>tm</td> <td>Thermal monitor automatically limits temperature </td> <td>f16c</td> <td>Floating-point conversion instructions to/from <a href="/wiki/FP16" class="mw-redirect" title="FP16">FP16</a> format </td> <th>29 </th></tr> <tr> <th>30 </th> <td>ia64</td> <td><a href="/wiki/IA64" class="mw-redirect" title="IA64">IA64</a> processor emulating x86<a href="#cite_note-ia64_sdm-67">[55]</a> </td> <td>rdrnd</td> <td><code><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></code> (on-chip random number generator) feature </td> <th>30 </th></tr> <tr> <th>31 </th> <td>pbe</td> <td>Pending Break Enable (PBE# pin) wakeup capability </td> <td>hypervisor</td> <td><a href="/wiki/Hypervisor" title="Hypervisor">Hypervisor</a> present (always zero on physical CPUs)<a href="#cite_note-VMware_KB_1009458-72">[58]</a><a href="#cite_note-73">[59]</a><a href="#cite_note-74">[60]</a> </td> <th>31 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-52"><a href="#cite_ref-52">^</a> On some older processors, executing <code>CPUID</code> with a leaf index (EAX) greater than 0 may leave EBX and ECX unmodified, keeping their old values. For this reason, it is recommended to zero out EBX and ECX before executing <code>CPUID</code> with a leaf index of 1.Processors noted to exhibit this behavior include Cyrix MII<a href="#cite_note-50">[46]</a> and IDT WinChip 2.<a href="#cite_note-51">[47]</a> </li> <li id="cite_note-54"><a href="#cite_ref-54">^</a> On processors from IDT, Transmeta and Rise (vendor IDs <code>CentaurHauls</code>, <code>GenuineTMx86</code> and <code>RiseRiseRise</code>), the <code>CMPXCHG8B</code> instruction is always supported, however the feature bit for the instruction might not be set. This is a workaround for a bug in Windows NT.<a href="#cite_note-53">[48]</a> </li> <li id="cite_note-56"><a href="#cite_ref-56">^</a> On early <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a> (<code>AuthenticAMD</code> Family 5 Model 0) processors only, EDX bit 9 used to indicate support for PGE instead. This was moved to bit 13 from K5 Model 1 onwards.<a href="#cite_note-55">[49]</a> </li> <li id="cite_note-58"><a href="#cite_ref-58">^</a> Intel AP-485, revisions 006<a href="#cite_note-57">[50]</a> to 008, lists CPUID.(EAX=1):EDX[bit 10] as having the name "MTRR" (albeit described as "Reserved"/"Do not count on their value") - this name was removed in later revisions of AP-485, and the bit has been listed as reserved with no name since then. </li> <li id="cite_note-60"><a href="#cite_ref-60">^</a> On <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> (<code>GenuineIntel</code> Family 6 Model 1) processors only, EDX bit 11 is invalid - the bit is set, but the <code>SYSENTER</code> and <code>SYSEXIT</code> instructions are not supported on the Pentium Pro.<a href="#cite_note-59">[51]</a> </li> <li id="cite_note-61"><a href="#cite_ref-61">^</a> <code>FCMOV</code> and <code>FCOMI</code> instructions only available if onboard x87 FPU also present (indicated by EDX bit 0). </li> <li id="cite_note-63"><a href="#cite_ref-63">^</a> ECX bit 16 is listed as "Reserved" in public Intel and AMD documentation and is not set in any known processor. However, some versions of the <a href="/wiki/Windows_Vista" title="Windows Vista">Windows Vista</a> kernel are reported to be checking this bit<a href="#cite_note-62">[52]</a> - if it is set, Vista will recognize it as a "processor channels" feature. </li> <li id="cite_note-64"><a href="#cite_ref-64">^</a> On Intel and Transmeta<a href="#cite_note-transmeta_msr-24">[24]</a> CPUs that support PSN (Processor Serial Number), the PSN can be disabled by setting bit 21 of MSR <code>119h</code> (<code>BBL_CR_CTL</code>) to 1. Doing so will remove leaf 3 and cause CPUID.(EAX=1):EDX[bit 18] to return 0. </li> <li id="cite_note-68"><a href="#cite_ref-68">^</a> On non-Itanium x86 processors, support for the <a href="/wiki/NX_bit" title="NX bit">No-execute bit</a> is indicated in CPUID.(EAX=8000_0001):EDX[bit 20] instead. </li> <li id="cite_note-71"><a href="#cite_ref-71">^</a> EDX bit 28, if set, indicates that bits 23:16 of CPUID.(EAX=1):EBX are valid. If this bit is not set, then the CPU package contains only 1 logical processor.In older documentation, this bit is often listed as a "<a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> technology"<a href="#cite_note-69">[56]</a> flag - however, while this flag is a prerequisite for Hyper-Threading support, it does not by itself indicate support for Hyper-Threading and it has been set on many CPUs that do not feature any form of multi-threading technology.<a href="#cite_note-70">[57]</a> </li> </ol></div></div> Reserved fields should be masked before using them for processor identification purposes. <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=2:_Cache_and_TLB_Descriptor_Information">EAX=2: Cache and TLB Descriptor Information</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=5" title="Edit section: EAX=2: Cache and TLB Descriptor Information">edit</a>]</div> This returns a list of descriptors indicating cache and <a href="/wiki/Translation_Lookaside_Buffer" class="mw-redirect" title="Translation Lookaside Buffer">TLB</a> capabilities in EAX, EBX, ECX and EDX registers. On processors that support this leaf, calling <code>CPUID</code> with EAX=2 will cause the bottom byte of EAX to be set to <code>01h</code><a href="#cite_note-76">[a]</a> and the remaining 15 bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well - in particular, <code>00h</code> is used for an empty descriptor, <code>FFh</code> indicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, and <code>FEh</code> indicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. The descriptors may appear in any order. For each of the four registers (EAX,EBX,ECX,EDX), if bit 31 is set, then the register should not be considered to contain valid descriptors (e.g. on Itanium in IA-32 mode, CPUID(EAX=2) returns <code>80000000h</code> in EDX - this should be interpreted to mean that EDX contains no valid information, not that it contains a descriptor for a 512K L2 cache.) <div style="width:100%; height:1em; clear:both;"></div> The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value (or other information, where that applies). The suffixes used in the table are: <ul><li>K,M,G : binary kilobyte, megabyte, gigabyte (capacity for caches, page-size for TLBs)</li> <li>E : entries (for TLBs; e.g. 64E = 64 entries)</li> <li>p : page-size (e.g. 4Kp for TLBs where each entry describes one 4 KB <a href="/wiki/Page_(computer_memory)" title="Page (computer memory)">page</a>, 4K/2Mp for TLBs where each entry can describe either one 4 KB page or one 2 MB hugepage)</li> <li>L : cache-line size (e.g. 32L = 32-byte cache line size)</li> <li>S : cache sector size (e.g. 2S means that the cache uses sectors of 2 cache-lines each)</li> <li>A : associativity (e.g. 6A = 6-way <a href="/wiki/Cache_placement_policies" title="Cache placement policies">set-associative</a>, FA = fully-associative)</li></ul> <div style="overflow-x:auto"> <table class="wikitable"> <caption>Legend for cache/TLB descriptor byte encodings </caption> <tbody><tr> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">Level-1 instruction or data cache </td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">Level-2 cache </td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">Level-3 cache </td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">Instruction or data TLB </td> <td rowspan="1" style="background:#F6DE99;color:black;vertical-align:middle;text-align:center;">Level-2 shared TLB </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Other information </td> <td style="background: #ccc; color: black; vertical-align: middle; text-align: center">(reserved) </td></tr></tbody></table> <table class="wikitable" style="background:#ccc; color: black; vertical-align: middle; text-align: center"> <caption>CPUID EAX=2: Cache/TLB descriptor byte encodings </caption> <tbody><tr> <th></th> <th>x0</th> <th>x1</th> <th>x2</th> <th>x3</th> <th>x4</th> <th>x5</th> <th>x6</th> <th>x7</th> <th></th> <th>x8</th> <th>x9</th> <th>xA</th> <th>xB</th> <th>xC</th> <th>xD</th> <th>xE</th> <th>xF</th> <th> </th></tr> <tr> <th>0x </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">null descriptor</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 32E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 2E, 4Mp, FA</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 64E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 8E, 4Mp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 32E, 4Mp, 4A</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1I: 8K, 4A, 32L</td> <td> </td> <th>0x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1I: 16K, 4A, 32L</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1I: 32K, 4A, 64L</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 8K, 2A, 32L</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 4E, 4Mp, FA</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 16K, 4A, 32L</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 16K, 4A, 64L<a href="#cite_note-leaf2_ecc-78">[b]</a></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 24K, 6A, 64L<a href="#cite_note-leaf2_ecc-78">[b]</a></td> <td> </td> <th>0x </th></tr> <tr> <th>1x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">(L1D: 16K, 4A, 32L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td></td> <td></td> <td></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">(L1I: 16K, 4A, 32L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td> </td> <th>1x </th> <td></td> <td></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">(L2C: 96K, 6A, 64L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 128K, 2A, 64L</td> <td></td> <td> </td> <th>1x </th></tr> <tr> <th>2x </th> <td></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 8A, 64L<a href="#cite_note-82">[d]</a></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 512K, 4A, 64L, 2S</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 1M, 8A, 64L, 2S</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 16A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 2M, 8A, 64L, 2S</td> <td>(128-byte prefetch)<a href="#cite_note-cpuid2_winnt-83">[e]</a></td> <td>(128-byte prefetch)<a href="#cite_note-cpuid2_winnt-83">[e]</a> </td> <th>2x </th> <td>(128-byte prefetch)<a href="#cite_note-cpuid2_winnt-83">[e]</a></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 4M, 8A, 64L, 2S</td> <td></td> <td></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 32K, 8A, 64L</td> <td></td> <td></td> <td> </td> <th>2x </th></tr> <tr> <th>3x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1I: 32K, 8A, 64L</td> <td></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>3x </th> <td></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 128K, 4A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 192K, 6A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 128K, 2A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 4A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 384K, 6A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 4A, 64L, 2S<a href="#cite_note-ap485_36-87">[f]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 2A, 64L<a href="#cite_note-90">[g]</a> </td> <th>3x </th></tr> <tr> <th>4x </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">no L3 cache present</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 128K, 4A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 4A, 32L<a href="#cite_note-cyrix3_leaf2-92">[h]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 4A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 4A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 2M, 4A, 32L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 4M, 4A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 8M, 8A, 64L </td> <th>4x </th> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 3M, 12A, 64L </td> <td style="background: linear-gradient(to top right, #73CEFF 0%, #73CEFF 50%, #AADCFE 50%, #AADCFE); color: black; vertical-align: middle; text-align: center">L2C/L3C:<a href="#cite_note-93">[i]</a> 4M, 16A, 64L </td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 6M, 12A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 8M, 16A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 12M, 12A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 16M, 16A, 64L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 6M, 24A, 64L</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 32E, 4Kp<a href="#cite_note-96">[j]</a> </td> <th>4x </th></tr> <tr> <th>5x </th> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 64E,FA, 4K/2M/4Mp</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 128E,FA, 4K/2M/4Mp</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 256E,FA, 4K/2M/4Mp</td> <td></td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 7E, 2M/4Mp, FA</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 16E, 4Mp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 16E, 4Kp, 4A </td> <th>5x </th> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 16E, 4Kp, FA</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 32E, 2M/4Mp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 64E 4K/4Mp, FA</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 128E, 4K/4Mp, FA</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 256E, 4K/4Mp, FA</td> <td></td> <td> </td> <th>5x </th></tr> <tr> <th>6x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 16K, 8A, 64L</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 48E, 4Kp, FA</td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;line-height:1.2">Two DTLBs: 32E, 2M/4Mp, 4A + 4E, 1Gp, FA </td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 512E, 4Kp, 4A</td> <td></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 8K, 4A, 64L</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 16K, 4A, 64L </td> <th>6x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">L1D: 32K, 4A, 64L</td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 64E, 4Kp, 8A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 256E, 4Kp, 8A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 128E, 2M/4Mp, 8A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 16E, 1Gp, FA</td> <td></td> <td> </td> <th>6x </th></tr> <tr> <th>7x </th> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;"><a href="/wiki/Trace_cache" title="Trace cache">Trace cache</a>, 12K-μop, 8A<a href="#cite_note-cyrix_leaf2-98">[k]</a></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">Trace cache, 16K-μop, 8A</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">Trace cache, 32K-μop, 8A</td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">Trace cache, 64K-μop, 8A<a href="#cite_note-ap485_36-87">[f]</a></td> <td><a href="#cite_note-cyrix3_leaf2-92">[h]</a></td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 8E, 2M/4Mp, FA<a href="#cite_note-99">[l]</a></td> <td rowspan="1" style="background:#D6EBFC;color:black;vertical-align:middle;text-align:center;">(L1I: 16K, 4A, 64L)<a href="#cite_note-leaf2_itanium2-100">[m]</a><a href="#cite_note-cyrix3_leaf2-92">[h]</a> </td> <th>7x </th> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 4A, 64L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 128K, 8A, 64L, 2S</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 8A, 64L, 2S</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 8A, 64L, 2S</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 8A, 64L, 2S</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 2M, 8A, 64L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">(L2C: 256K, 8A, 128L)<a href="#cite_note-leaf2_itanium2-100">[m]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 2A, 64L </td> <th>7x </th></tr> <tr> <th>8x </th> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 8A, 64L<a href="#cite_note-cyrix_leaf2-98">[k]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">(L2C: 128K, 8A, 32L)<a href="#cite_note-cpuid2_winnt-83">[e]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 256K, 8A, 32L<a href="#cite_note-cyrix3_leaf2-92">[h]</a></td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 8A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 8A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 2M, 8A, 32L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 512K, 4A, 64L</td> <td rowspan="1" style="background:#AADCFE;color:black;vertical-align:middle;text-align:center;">L2C: 1M, 8A, 64L </td> <th>8x </th> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">(L3C: 2M, 4A, 64L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">(L3C: 4M, 4A, 64L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">(L3C: 8M, 4A, 64L)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">(L3C: 3M, 12A, 128L)<a href="#cite_note-leaf2_itanium2-100">[m]</a><a href="#cite_note-105">[n]</a></td> <td></td> <td> </td> <th>8x </th></tr> <tr> <th>9x </th> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">(ITLB: 64E,FA, 4K-256Mp)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">(DTLB: 32E,FA, 4K-256Mp)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td> </td> <th>9x </th> <td></td> <td></td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">(DTLB: 96E,FA, 4K-256Mp)<a href="#cite_note-leaf2_itanium-80">[c]</a></td> <td></td> <td></td> <td></td> <td> </td> <th>9x </th></tr> <tr> <th>Ax </th> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 32E, 4Kp, FA</td> <td></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>Ax </th> <td></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>Ax </th></tr> <tr> <th>Bx </th> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 128E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 8E, 2M/4Mp, 4A<a href="#cite_note-106">[o]</a></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 64E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 128E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 256E, 4Kp, 4A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 64E, 4Kp, 8A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">ITLB: 128E, 4Kp, 8A</td> <td> </td> <th>Bx </th> <td></td> <td></td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 64E, 4Kp, 4A</td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>Bx </th></tr> <tr> <th>Cx </th> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 8E, 4K/4Mp, 4A</td> <td rowspan="1" style="background:#F6DE99;color:black;vertical-align:middle;text-align:center;">L2TLB: 1024E, 4K/2Mp, 8A</td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 16E, 2M/4Mp, 4A<a href="#cite_note-107">[78]</a> </td> <td rowspan="1" style="background:#F6DE99;color:black;vertical-align:middle;text-align:center;line-height:1.2">Two L2 STLBs: 1536E, 4K/2Mp, 6A + 16E, 1Gp, 4A </td> <td rowspan="1" style="background:#F8F1E2;color:black;vertical-align:middle;text-align:center;">DTLB: 32E, 2M/4Mp, 4A</td> <td></td> <td></td> <td> </td> <th>Cx </th> <td></td> <td></td> <td rowspan="1" style="background:#F6DE99;color:black;vertical-align:middle;text-align:center;">L2TLB: 512E, 4Kp, 4A</td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>Cx </th></tr> <tr> <th>Dx </th> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 512K, 4A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 1M, 4A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 2M, 4A, 64L</td> <td></td> <td></td> <td></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 1M, 8A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 2M, 8A, 64L </td> <th>Dx </th> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 4M, 8A, 64L</td> <td></td> <td></td> <td></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 1.5M, 12A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 3M, 12A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 6M, 12A, 64L</td> <td> </td> <th>Dx </th></tr> <tr> <th>Ex </th> <td></td> <td></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 2M, 16A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 4M, 16A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 8M, 16A, 64L</td> <td></td> <td></td> <td> </td> <th>Ex </th> <td></td> <td></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 12M, 24A, 64L</td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 18M, 24A, 64L<a href="#cite_note-108">[79]</a></td> <td rowspan="1" style="background:#73CEFF;color:black;vertical-align:middle;text-align:center;">L3C: 24M, 24A, 64L</td> <td></td> <td></td> <td> </td> <th>Ex </th></tr> <tr> <th>Fx </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">64-byte prefetch<a href="#cite_note-leaf2_prefetch-110">[p]</a></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">128-byte prefetch<a href="#cite_note-leaf2_prefetch-110">[p]</a></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td> </td> <th>Fx </th> <td></td> <td></td> <td></td> <td></td> <td></td> <td></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Leaf 2 has no TLB info, use leaf 18h</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Leaf 2 has no cache info, use leaf 4 </td> <th>Fx </th></tr> <tr> <th></th> <th>x0</th> <th>x1</th> <th>x2</th> <th>x3</th> <th>x4</th> <th>x5</th> <th>x6</th> <th>x7</th> <th></th> <th>x8</th> <th>x9</th> <th>xA</th> <th>xB</th> <th>xC</th> <th>xD</th> <th>xE</th> <th>xF</th> <th> </th></tr></tbody></table> </div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-76"><a href="#cite_ref-76">^</a> In older Intel documentation, the bottom byte of the value returned in EAX is described as specifying the number of times the <code>CPUID</code> must be called with EAX=2 to get hold of all the cache/TLB descriptors. However, all known processors that implement this leaf return <code>01h</code> in this byte, and newer Intel documentation (SDM rev 053<a href="#cite_note-75">[61]</a> and later) specifies this byte as having the value <code>01h</code>. </li> <li id="cite_note-leaf2_ecc-78">^ <a href="#cite_ref-leaf2_ecc_78-0">a</a> <a href="#cite_ref-leaf2_ecc_78-1">b</a> For descriptors <code>0Dh</code> and <code>0Eh</code>, Intel AP-485 rev 37<a href="#cite_note-ap485_rev037-77">[62]</a> lists the caches they describe as having <a href="/wiki/Error_correction_code" title="Error correction code">ECC</a> - this was removed in rev 38 and later Intel documentation. </li> <li id="cite_note-leaf2_itanium-80">^ <a href="#cite_ref-leaf2_itanium_80-0">a</a> <a href="#cite_ref-leaf2_itanium_80-1">b</a> <a href="#cite_ref-leaf2_itanium_80-2">c</a> <a href="#cite_ref-leaf2_itanium_80-3">d</a> <a href="#cite_ref-leaf2_itanium_80-4">e</a> <a href="#cite_ref-leaf2_itanium_80-5">f</a> <a href="#cite_ref-leaf2_itanium_80-6">g</a> <a href="#cite_ref-leaf2_itanium_80-7">h</a> <a href="#cite_ref-leaf2_itanium_80-8">i</a> Descriptors <code>10h</code>, <code>15h</code>, <code>1Ah</code>, <code>88h</code>, <code>89h</code>, <code>8Ah</code>, <code>90h</code>, <code>96h</code>, <code>9Bh</code> are documented for the IA-32 operation mode of <a href="/wiki/Itanium" title="Itanium">Itanium</a> only.<a href="#cite_note-79">[63]</a> </li> <li id="cite_note-82"><a href="#cite_ref-82">^</a> The cache described by descriptor <code>21h</code> is in some places (e.g. AP-485 rev 36<a href="#cite_note-ap485_rev36-81">[64]</a> but not rev 37) referred to as an "MLC" (Mid-Level Cache). </li> <li id="cite_note-cpuid2_winnt-83">^ <a href="#cite_ref-cpuid2_winnt_83-0">a</a> <a href="#cite_ref-cpuid2_winnt_83-1">b</a> <a href="#cite_ref-cpuid2_winnt_83-2">c</a> <a href="#cite_ref-cpuid2_winnt_83-3">d</a> Descriptor values <code>26h</code>,<code>27h</code>,<code>28h</code> and <code>81h</code> are not listed in Intel documentation and are not used in any known released CPU. (<code>81h</code> has been seen in engineering samples of the cancelled <a href="/wiki/Intel_Timna" title="Intel Timna">Intel Timna</a>.<a href="#cite_note-101">[74]</a>) They have nevertheless been reported to be recognized by the <a href="/wiki/Windows_NT_kernel" class="mw-redirect" title="Windows NT kernel">Windows NT kernel</a> v5.1 (<a href="/wiki/Windows_XP" title="Windows XP">Windows XP</a>) and higher. <code>81h</code> is also recognized by v5.0 (<a href="/wiki/Windows_2000" title="Windows 2000">Windows 2000</a>).<a href="#cite_note-102">[75]</a> </li> <li id="cite_note-ap485_36-87">^ <a href="#cite_ref-ap485_36_87-0">a</a> <a href="#cite_ref-ap485_36_87-1">b</a> <a href="#cite_ref-ap485_36_87-2">c</a> <a href="#cite_ref-ap485_36_87-3">d</a> <a href="#cite_ref-ap485_36_87-4">e</a> <a href="#cite_ref-ap485_36_87-5">f</a> <a href="#cite_ref-ap485_36_87-6">g</a> Descriptors <code>39h-3Eh</code> and <code>73h</code> are listed in rev 36 of Intel AP-485,<a href="#cite_note-ap485_rev36-81">[64]</a> but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in <a href="/wiki/List_of_Intel_Celeron_processors#Netburst_based_Celerons" title="List of Intel Celeron processors">Netburst-based Celeron</a> CPUs, e.g. <code>39h</code> in <a href="/wiki/Celeron#Willamette-128" title="Celeron">"Willamette-128"</a>,<a href="#cite_note-84">[65]</a> <code>3Bh</code> in "Northwood-128",<a href="#cite_note-85">[66]</a> and <code>3Ch</code> in "Prescott-256"<a href="#cite_note-86">[67]</a>). </li> <li id="cite_note-90"><a href="#cite_ref-90">^</a> Descriptor <code>3Fh</code> is, as of November 2024, not listed in any known Intel documentation - it is nevertheless used in Intel <a href="/wiki/Tolapai" title="Tolapai">Tolapai</a> processors,<a href="#cite_note-88">[68]</a> and is listed in an Intel-provided Linux kernel patch.<a href="#cite_note-89">[69]</a> </li> <li id="cite_note-cyrix3_leaf2-92">^ <a href="#cite_ref-cyrix3_leaf2_92-0">a</a> <a href="#cite_ref-cyrix3_leaf2_92-1">b</a> <a href="#cite_ref-cyrix3_leaf2_92-2">c</a> <a href="#cite_ref-cyrix3_leaf2_92-3">d</a> Documentation for the VIA <a href="/wiki/Cyrix_III" title="Cyrix III">Cyrix III</a> "Joshua" processor (<code>CyrixInstead</code> Family 6 Model 5) indicates that this processor uses descriptor values <code>74h</code> and <code>77h</code> for its TLBs, and values <code>42h</code> and <code>82h</code> for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.<a href="#cite_note-91">[70]</a> </li> <li id="cite_note-93"><a href="#cite_ref-93">^</a> Descriptor <code>49h</code> indicates a level-3 cache on <code>GenuineIntel</code> Family 0Fh Model 6 (Pentium 4 based Xeon) CPUs, and a level-2 cache on other CPUs. </li> <li id="cite_note-96"><a href="#cite_ref-96">^</a> Intel's CPUID documentation does not specify the associativity of the ITLB indicated by descriptor <code>4Fh</code>. The processors that use this descriptor (Intel Atom <a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">"Bonnell"</a><a href="#cite_note-94">[71]</a>) are described elsewhere as having a fully-associative 32-entry ITLB.<a href="#cite_note-95">[72]</a> </li> <li id="cite_note-cyrix_leaf2-98">^ <a href="#cite_ref-cyrix_leaf2_98-0">a</a> <a href="#cite_ref-cyrix_leaf2_98-1">b</a> On Cyrix and Geode CPUs (Vendor IDs <code>CyrixInstead</code> and <code>Geode by NSC</code>), descriptors <code>70h</code> and <code>80h</code> have a different meaning:<a href="#cite_note-97">[73]</a> <ul><li>Descriptor <code>70h</code> indicates a 32-entry shared instruction+data 4-way-set-associative TLB with a 4K page size.</li> <li>Descriptor <code>80h</code> indicates a 16 KB shared instruction+data L1 cache with 4-way set-associativity and a cache-line size of 16 bytes.</li></ul> </li> <li id="cite_note-99"><a href="#cite_ref-99">^</a> Descriptor <code>76h</code> is listed as an 1 MB L2 cache in rev 37 of Intel AP-485,<a href="#cite_note-ap485_rev037-77">[62]</a> but as an instruction TLB in rev 38 and all later Intel documentation. </li> <li id="cite_note-leaf2_itanium2-100">^ <a href="#cite_ref-leaf2_itanium2_100-0">a</a> <a href="#cite_ref-leaf2_itanium2_100-1">b</a> <a href="#cite_ref-leaf2_itanium2_100-2">c</a> Descriptors <code>77h</code>, <code>7Eh</code>, <code>8Dh</code> are documented for the IA-32 operation mode of <a href="/wiki/Itanium_2" class="mw-redirect" title="Itanium 2">Itanium 2</a> only.<a href="#cite_note-103">[76]</a> </li> <li id="cite_note-105"><a href="#cite_ref-105">^</a> Under the IA-32 operation mode of Itanium 2, the L3 cache size is always reported as 3 MB regardless of the actual size of the cache.<a href="#cite_note-104">[77]</a> </li> <li id="cite_note-106"><a href="#cite_ref-106">^</a> For descriptor <code>B1h</code>, the TLB capacity is 8 elements when using 2 MB pages, but reduced to 4 elements when using 4 MB pages. </li> <li id="cite_note-leaf2_prefetch-110">^ <a href="#cite_ref-leaf2_prefetch_110-0">a</a> <a href="#cite_ref-leaf2_prefetch_110-1">b</a> The prefetch specified by descriptors <code>F0h</code> and <code>F1h</code> is the recommended stride for memory prefetching with the <code>PREFETCHNTA</code> instruction.<a href="#cite_note-109">[80]</a> </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=3:_Processor_Serial_Number">EAX=3: Processor Serial Number</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=6" title="Edit section: EAX=3: Processor Serial Number">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Pentium_III#Controversy_about_privacy_issues" title="Pentium III">Pentium III § Controversy about privacy issues</a></div> This returns the processor's serial number. The processor serial number was introduced on Intel <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a>, but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared). <a href="/wiki/Transmeta" title="Transmeta">Transmeta's</a> Efficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models. For Intel Pentium III CPUs, the serial number is returned in the EDX:ECX registers. For Transmeta Efficeon CPUs, it is returned in the EBX:EAX registers. And for Transmeta Crusoe CPUs, it is returned in the EBX register only. Note that the processor serial number feature must be enabled in the <a href="/wiki/BIOS" title="BIOS">BIOS</a> setting in order to function. <div class="mw-heading mw-heading3"><h3 id="EAX=4_and_EAX=8000'001Dh:_Cache_Hierarchy_and_Topology">EAX=4 and EAX=8000'001Dh: Cache Hierarchy and Topology</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=7" title="Edit section: EAX=4 and EAX=8000'001Dh: Cache Hierarchy and Topology">edit</a>]</div> These two leaves are used to provide information about the <a href="/wiki/Cache_hierarchy" title="Cache hierarchy">cache hierarchy</a> levels available to the processor core on which the <code>CPUID</code> instruction is run. Leaf <code>4</code> is used on Intel processors and leaf <code>8000'001Dh</code> is used on AMD processors - they both return data in EAX, EBX, ECX and EDX, using the same data format except that leaf <code>4</code> returns a few additional fields that are considered "reserved" for leaf <code>8000'001Dh</code>. They both provide CPU cache information in a series of sub-leaves selected by ECX - to get information about all the cache levels, it is necessary to invoke <code>CPUID</code> repeatedly, with EAX=<code>4</code> or <code>8000'001Dh</code> and ECX set to increasing values starting from 0 (0,1,2,...) until a sub-leaf not describing any caches (EAX[4:0]=0) is found. The sub-leaves that do return cache information may appear in any order, but all of them will appear before the first sub-leaf not describing any caches. In the below table, fields that are defined for leaf <code>4</code> but not for leaf <code>8000'001Dh</code> are highlighted with yellow cell coloring and a (#4) item. <table class="wikitable"> <caption>CPUID EAX=4 and 8000'001Dh: Cache property information in EAX, EBX and EDX </caption> <tbody><tr> <th>Bit </th> <th>EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="15"> </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="15"> </th> <th>EDX<a href="#cite_note-112">[a]</a> </th> <th>Bit </th></tr> <tr> <th>0 </th> <td rowspan="5">Cache Type: <ul><li>0: (No more caches)</li> <li>1: Data Cache</li> <li>2: Instruction Cache</li> <li>3: Unified Cache</li> <li>4-31: (reserved)</li></ul> </td> <td rowspan="10">System <a href="/wiki/False_sharing" title="False sharing">coherency line size</a> in bytes, minus 1 </td> <td><code>WBINVD</code> cache invalidation execution scope. A value of 0 indicates that the <code>INVD</code>/<code>WBINVD</code> instructions will invalidate all lower-levels caches of this cache, including caches that belong to sibling processors sharing this cache. A value of 1 indicates that lower-level caches of sibling processors that are sharing this cache are not guaranteed to be all cleared. </td> <th>0 </th></tr> <tr> <th>1 </th> <td>Cache inclusiveness. If 1, then cache is inclusive of lower-level caches. </td> <th>1 </th></tr> <tr> <th>2 </th> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">Complex cache indexing. If 1, then cache uses a complex function for cache indexing, else the cache is direct-mapped. (#4) </td> <th>2 </th></tr> <tr> <th>3 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>4 </th></tr> <tr> <th>7:5 </th> <td>Cache Level (starting from 1) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>7:5 </th></tr> <tr> <th>8 </th> <td>Self initializing cache level (1=doesn't need software initialization after reset) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>8 </th></tr> <tr> <th>9 </th> <td>Fully Associative Cache </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>9 </th></tr> <tr> <th>10 </th> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">(<code>WBINVD</code> cache invalidation execution scope)<a href="#cite_note-leaf4_knc-113">[b]</a> (#4) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>10 </th></tr> <tr> <th>11 </th> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">(Cache Inclusiveness)<a href="#cite_note-leaf4_knc-113">[b]</a> (#4) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>11 </th></tr> <tr> <th>13:12 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td rowspan="2">Physical line partitions (number of cache lines that share a cache address tag), minus 1 </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>13:12 </th></tr> <tr> <th>21:14 </th> <td rowspan="2">Maximum number of addressable IDs for logical processors sharing this cache, minus 1 </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>21:14 </th></tr> <tr> <th>25:22 </th> <td rowspan="2">Ways of <a href="/wiki/Cache_placement_policies#Set-associative_cache" title="Cache placement policies">cache associativity</a>, minus 1 </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>25:22 </th></tr> <tr> <th>31:26 </th> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">Maximum number of addressable IDs for processor cores in physical package, minus 1 (#4) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:26 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-112"><a href="#cite_ref-112">^</a> Intel AP-485, revisions 31<a href="#cite_note-111">[81]</a> and 32, list bits 9:0 of EDX as a "Prefetch Stride" field - this was removed in revision 33 and all later Intel documentation, and no processor is known to use EDX in this manner. </li> <li id="cite_note-leaf4_knc-113">^ <a href="#cite_ref-leaf4_knc_113-0">a</a> <a href="#cite_ref-leaf4_knc_113-1">b</a> For CPUID leaf 4, bits 11:10 of EAX are documented for the Xeon Phi "Knights Corner" (<code>GenuineIntel</code> Family <code>0Bh</code>) processor only.<a href="#cite_note-intel_knc_ref-42">[40]</a> For other processors, bits 1:0 of EDX should be used instead. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> For any caches that are valid and not fully-associative, the value returned in ECX is the number of sets in the cache minus 1. (For fully-associative caches, ECX should be treated as if it return the value 0.) For any given cache described by a sub-leaf of <code>CPUID</code> leaf <code>4</code> or <code>8000'001Dh</code>, the total cache size in bytes can be computed as: <code>CacheSize = (EBX[11:0]+1) * (EBX[21:12]+1) * (EBX[31:22]+1) * (ECX+1)</code> For example, on Intel <a href="/wiki/Crystalwell" class="mw-redirect" title="Crystalwell">Crystalwell</a> CPUs, executing CPUID with EAX=4 and ECX=4 will cause the processor to return the following size information for its level-4 cache in EBX and ECX: <code>EBX=03C0F03F</code> and <code>ECX=00001FFF</code> - this should be taken to mean that this cache has a cache line size of 64 bytes (EBX[11:0]+1), has 16 cache lines per tag (EBX[21:12]+1), is 16-way set-associative (EBX[31:22]+1) with 8192 sets (ECX+1), for a total size of 64*16*16*8192=134217728 bytes, or 128 binary megabytes. <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=4_and_EAX=Bh:_Intel_Thread/Core_and_Cache_Topology">EAX=4 and EAX=Bh: Intel Thread/Core and Cache Topology</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=8" title="Edit section: EAX=4 and EAX=Bh: Intel Thread/Core and Cache Topology">edit</a>]</div> These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.<a href="#cite_note-topo-114">[82]</a> As of 2013<a class="external text" href="https://en.wikipedia.org/w/index.php?title=CPUID&action=edit">[update]</a> AMD does not use these leaves but has alternate ways of doing the core enumeration.<a href="#cite_note-115">[83]</a> Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually the <a href="/wiki/X2APIC" class="mw-redirect" title="X2APIC">x2APIC</a> id of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf. The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond to the order in the physical hierarchy (<a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a>/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a "level type", which can be either SMT, core, or "invalid". The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level. As an example, a dual-core <a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a> processor capable of <a href="/wiki/Hyperthreading" class="mw-redirect" title="Hyperthreading">hyperthreading</a> (thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However, EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviously) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bits reserved for a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor. The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4. Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;<a href="#cite_note-116">[84]</a> errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using CPUID, even for the 2013 edition of Visual Studio,<a href="#cite_note-117">[85]</a> and also in the sandpile.org page for CPUID,<a href="#cite_note-118">[86]</a> but the Intel code sample for identifying processor topology<a href="#cite_note-topo-114">[82]</a> has the correct interpretation, and the current Intel Software Developer's Manual has a more clear language. The (open source) cross-platform production code<a href="#cite_note-wildfire-119">[87]</a> from <a href="/wiki/Wildfire_Games" title="Wildfire Games">Wildfire Games</a> also implements the correct interpretation of the Intel documentation. Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.<a href="#cite_note-120">[88]</a> Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method. <div class="mw-heading mw-heading3"><h3 id="EAX=5:_MONITOR/MWAIT_Features">EAX=5: MONITOR/MWAIT Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=9" title="Edit section: EAX=5: MONITOR/MWAIT Features">edit</a>]</div> This returns feature information related to the <code>MONITOR</code> and <code>MWAIT</code> instructions in the EAX, EBX, ECX and EDX registers. <table class="wikitable"> <caption>CPUID EAX=5: MONITOR/MWAIT feature information in EAX, EBX, EDX </caption> <tbody><tr> <th>Bit </th> <th>EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9"> </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9"> </th> <th>EDX </th> <th>Bit </th></tr> <tr> <th>3:0 </th> <td rowspan="4">Smallest monitor-line size in bytes </td> <td rowspan="4">Largest monitor-line size in bytes </td> <td>Number of C0<a href="#cite_note-121">[a]</a> sub-states supported for <code>MWAIT</code> </td> <th>3:0 </th></tr> <tr> <th>7:4 </th> <td>Number of C1 sub-states supported for <code>MWAIT</code> </td> <th>7:4 </th></tr> <tr> <th>11:8 </th> <td>Number of C2 sub-states supported for <code>MWAIT</code> </td> <th>11:8 </th></tr> <tr> <th>15:12 </th> <td>Number of C3 sub-states supported for <code>MWAIT</code> </td> <th>15:12 </th></tr> <tr> <th>19:16 </th> <td rowspan="4" style="text-align:center; background:lightgrey;">(reserved) </td> <td rowspan="4" style="text-align:center; background:lightgrey;">(reserved) </td> <td>Number of C4 sub-states supported for <code>MWAIT</code> </td> <th>19:16 </th></tr> <tr> <th>23:20 </th> <td>Number of C5 sub-states supported for <code>MWAIT</code> </td> <th>23:20 </th></tr> <tr> <th>27:24 </th> <td>Number of C6 sub-states supported for <code>MWAIT</code> </td> <th>27:24 </th></tr> <tr> <th>31:28 </th> <td>Number of C7 sub-states supported for <code>MWAIT</code> </td> <th>31:28 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-121"><a href="#cite_ref-121">^</a> The C0 to C7 states are processor-specific C-states, which do not necessarily correspond 1:1 to <a href="/wiki/ACPI#Processor_states" title="ACPI">ACPI C-states</a>. </li> </ol></div></div> <table class="wikitable"> <caption>CPUID EAX=5: MONITOR/MWAIT extension enumeration in ECX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">ECX </th></tr> <tr> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>EMX</td> <td>Enumeration of MONITOR/MWAIT extensions in ECX and EDX supported </td></tr> <tr> <th>1 </th> <td>IBE</td> <td>Supports treating interrupts as break-events for <code>MWAIT</code> even when interrupts are disabled </td></tr> <tr> <th>2 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>3 </th> <td>Monitorless_MWAIT</td> <td>Allow <code>MWAIT</code> to be used for power management without setting up memory monitoring with <code>MONITOR</code><a href="#cite_note-122">[89]</a> </td></tr> <tr> <th> 31:4   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="EAX=6:_Thermal_and_Power_Management">EAX=6: Thermal and Power Management</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=10" title="Edit section: EAX=6: Thermal and Power Management">edit</a>]</div> This returns feature bits in the EAX register and additional information in the EBX, ECX and EDX registers. <table class="wikitable"> <caption>CPUID EAX=6: Thermal/power management feature bits in EAX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th></tr> <tr> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>DTS</td> <td>Digital Thermal Sensor capability </td></tr> <tr> <th>1 </th> <td></td> <td><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Intel Turbo Boost</a> Technology capability </td></tr> <tr> <th>2 </th> <td>ARAT<a href="#cite_note-124">[a]</a></td> <td>Always Running <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">APIC</a> Timer capability </td></tr> <tr> <th>3 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>4 </th> <td>PLN</td> <td>Power Limit Notification capability </td></tr> <tr> <th>5 </th> <td>ECMD</td> <td>Extended Clock Modulation Duty capability </td></tr> <tr> <th>6 </th> <td>PTM</td> <td>Package Thermal Management capability </td></tr> <tr> <th>7 </th> <td>HWP</td> <td>Hardware-controlled <a href="/wiki/ACPI#Performance_state" title="ACPI">Performance States</a>. MSRs added: <ul><li><code>IA32_PM_ENABLE</code>(<code>770h</code>)</li> <li><code>IA32_HWP_CAPABILITIES</code>(<code>771h</code>)</li> <li><code>IA32_HWP_REQUEST</code>(<code>774h</code>)</li> <li><code>IA32_HWP_STATUS</code>(<code>777h</code></li></ul> </td></tr> <tr> <th>8 </th> <td>HWP_Notification</td> <td>HWP notification of dynamic guaranteed performance change - <code>IA32_HWP_INTERRUPT</code>(<code>773h</code>) MSR </td></tr> <tr> <th>9 </th> <td>HWP_Activity_Window</td> <td>HWP Activity Window control - bits 41:32 of <code>IA32_HWP_REQUEST</code> MSR </td></tr> <tr> <th>10 </th> <td>HWP_Energy_Performance_Preference</td> <td>HWP Energy/performance preference control - bits 31:24 of <code>IA32_HWP_REQUEST</code> MSR </td></tr> <tr> <th>11 </th> <td>HWP_Package_Level_Request</td> <td>HWP Package-level control - <code>IA32_HWP_REQUEST_PKG</code>(<code>772h</code>) MSR </td></tr> <tr> <th>12 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>13 </th> <td>HDC</td> <td>Hardware <a href="/wiki/Duty_cycle" title="Duty cycle">Duty Cycling</a> supported. MSRs added: <ul><li><code>IA32_PKG_HDC_CTL</code> (<code>DB0h</code>)</li> <li><code>IA32_PM_CTL1</code> (<code>DB1h</code>)</li> <li><code>IA32_THREAD_STALL</code> (<code>DB2h</code>)</li></ul> </td></tr> <tr> <th>14 </th> <td></td> <td><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Intel Turbo Boost</a> Max Technology 3.0 available </td></tr> <tr> <th>15 </th> <td></td> <td>Interrupts upon changes to <code>IA32_HWP_CAPABILITIES</code>.Highest_Performance (bits 7:0) supported </td></tr> <tr> <th>16 </th> <td></td> <td>HWP <a href="/wiki/Platform_Environment_Control_Interface" title="Platform Environment Control Interface">PECI</a> override supported - bits 63:60 of <code>IA32_HWP_PECI_REQUEST_INFO</code>(<code>775h</code>) MSR </td></tr> <tr> <th>17 </th> <td></td> <td>Flexible HWP - bits 63:59 of <code>IA32_HWP_REQUEST</code> MSR </td></tr> <tr> <th>18 </th> <td>Fast Access Mode</td> <td>Fast access mode for <code>IA32_HWP_REQUEST</code> MSR supported<a href="#cite_note-125">[b]</a> </td></tr> <tr> <th>19 </th> <td>HW_FEEDBACK</td> <td>Hardware Feedback Interface. Added MSRs: <ul><li><code>IA32_HW_FEEDBACK_PTR</code>(<code>17D0h</code>)</li> <li><code>IA32_HW_FEEDBACK_CONFIG</code>(<code>17D1h</code>) (bit 0 enables HFI, bit 1 enables Intel Thread Director)</li></ul> </td></tr> <tr> <th>20 </th> <td></td> <td><code>IA32_HWP_REQUEST</code> of idle logical processor ignored when only one of two logical processors that <a href="/wiki/Hyper-Threading" class="mw-redirect" title="Hyper-Threading">share a physical processor</a> is active. </td></tr> <tr> <th>21 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>22 </th> <td>HWP Control MSR</td> <td><code>IA32_HWP_CTL</code>(<code>776h</code>) MSR supported<a href="#cite_note-126">[91]</a> </td></tr> <tr> <th>23 </th> <td></td> <td>Intel Thread Director supported. Added MSRs: <ul><li><code>IA32_THREAD_FEEDBACK_CHAR</code>(<code>17D2h</code>)</li> <li><code>IA32_HW_FEEDBACK_THREAD_CONFIG</code>(<code>17D4h</code>)</li></ul> </td></tr> <tr> <th>24 </th> <td></td> <td><code>IA32_THERM_INTERRUPT</code> MSR bit 25 supported </td></tr> <tr> <th> 31:25   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-124"><a href="#cite_ref-124">^</a> On Intel Pentium 4 family processors only, bit 2 of EAX is used to indicate OPP (Operating Point Protection)<a href="#cite_note-123">[90]</a> instead of ARAT. </li> <li id="cite_note-125"><a href="#cite_ref-125">^</a> To enable fast (non-serializing) access mode for the <code>IA32_HWP_REQUEST</code> MSR on CPUs that support it, it is necessary to set bit 0 of the <code>FAST_UNCORE_MSRS_CTL</code>(<code>657h</code>) MSR. </li> </ol></div></div> <table class="wikitable"> <caption>CPUID EAX=6: Thermal/power management feature fields in EBX, ECX and EDX </caption> <tbody><tr> <th>Bit </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9"> </th> <th>ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9"> </th> <th>EDX </th> <th>Bit </th></tr> <tr> <th>0 </th> <td rowspan="4">Number of Interrupt Thresholds in Digital Thermal Sensor </td> <td>Effective frequency interface supported - <code>IA32_MPERF</code>(<code>0E7h</code>) and <code>IA32_APERF</code>(<code>0E8h</code>) MSRs </td> <td>Hardware Feedback reporting: Performance Capability Reporting supported </td> <th>0 </th></tr> <tr> <th>1 </th> <td>(ACNT2 Capability)<a href="#cite_note-129">[a]</a> </td> <td>Hardware Feedback reporting: Efficiency Capability Reporting supported </td> <th>1 </th></tr> <tr> <th>2 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td rowspan="3" style="text-align:center; background:lightgrey;">(reserved) </td> <th>2 </th></tr> <tr> <th>3 </th> <td>Performance-Energy Bias capability - <code>IA32_ENERGY_PERF_BIAS</code>(<code>1B0h</code>) MSR </td> <th>3 </th></tr> <tr> <th>7:4 </th> <td rowspan="4" style="text-align:center; background:lightgrey;">(reserved) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>7:4 </th></tr> <tr> <th>11:8 </th> <td rowspan="2">Number of Intel Thread Director classes supported by hardware </td> <td>Size of Hardware Feedback interface structure (in units of 4 KB) minus 1 </td> <th>11:8 </th></tr> <tr> <th>15:12 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>15:12 </th></tr> <tr> <th> 31:16   </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td>Index of this logical processor's row in hardware feedback interface structure </td> <th> 31:16   </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-129"><a href="#cite_ref-129">^</a> The "ACNT2 Capability" bit is listed in Intel AP-485 rev 038<a href="#cite_note-127">[92]</a> and 039, but not listed in any revision of the Intel SDM. The feature is known to exist in only a few Intel CPUs, e.g. Xeon "Harpertown" stepping E0.<a href="#cite_note-128">[93]</a> </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=7,_ECX=0:_Extended_Features">EAX=7, ECX=0: Extended Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=11" title="Edit section: EAX=7, ECX=0: Extended Features">edit</a>]</div> This returns extended feature flags in EBX, ECX, and EDX. Returns the maximum ECX value for EAX=7 in EAX. <table class="wikitable"> <caption>CPUID EAX=7,ECX=0: Extended feature bits in EBX, ECX and EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>fsgsbase</td> <td>Access to base of %fs and %gs </td> <td>prefetchwt1</td> <td><code>PREFETCHWT1</code> instruction </td> <td>(sgx-tem)<a href="#cite_note-leaf7_0_tdx-130">[a]</a></td> <td>? </td> <th>0 </th></tr> <tr> <th>1 </th> <td></td> <td>IA32_TSC_ADJUST MSR </td> <td>avx512-vbmi</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Vector Bit Manipulation Instructions </td> <td>sgx-keys</td> <td>Attestation Services for <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">Intel SGX</a> </td> <th>1 </th></tr> <tr> <th>2 </th> <td>sgx</td> <td><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">Software Guard Extensions</a> </td> <td>umip</td> <td>User-mode Instruction Prevention </td> <td>avx512-4vnniw</td> <td><a href="/wiki/AVX-512#4FMAPS_and_4VNNIW" title="AVX-512">AVX-512</a> 4-register Neural Network Instructions </td> <th>2 </th></tr> <tr> <th>3 </th> <td>bmi1</td> <td><a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1" class="mw-redirect" title="Bit Manipulation Instruction Sets">Bit Manipulation Instruction Set 1</a> </td> <td>pku</td> <td>Memory Protection Keys for User-mode pages </td> <td>avx512-4fmaps</td> <td><a href="/wiki/AVX-512#4FMAPS_and_4VNNIW" title="AVX-512">AVX-512</a> 4-register Multiply Accumulation Single precision </td> <th>3 </th></tr> <tr> <th>4 </th> <td>hle</td> <td><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> Hardware Lock Elision </td> <td>ospke</td> <td>PKU enabled by OS </td> <td>fsrm</td> <td>Fast Short <code>REP MOVSB</code> </td> <th>4 </th></tr> <tr> <th>5 </th> <td>avx2</td> <td><a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">Advanced Vector Extensions 2</a> </td> <td>waitpkg</td> <td>Timed pause and user-level monitor/wait instructions (<code>TPAUSE</code>, <code>UMONITOR</code>, <code>UMWAIT</code>) </td> <td>uintr</td> <td>User Inter-processor Interrupts </td> <th>5 </th></tr> <tr> <th>6 </th> <td>fdp-excptn-only</td> <td><a href="/wiki/X87" title="X87">x87</a> FPU data pointer register updated on exceptions only </td> <td>avx512-vbmi2</td> <td><a href="/wiki/AVX-512#VBMI2" title="AVX-512">AVX-512</a> Vector Bit Manipulation Instructions 2 </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>6 </th></tr> <tr> <th>7 </th> <td>smep</td> <td><a href="/wiki/Supervisor_Mode_Execution_Prevention" class="mw-redirect" title="Supervisor Mode Execution Prevention">Supervisor Mode Execution Prevention</a> </td> <td>cet_ss/shstk</td> <td>Control flow enforcement (CET): shadow stack (SHSTK alternative name) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7 </th></tr> <tr> <th>8 </th> <td>bmi2</td> <td><a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">Bit Manipulation Instruction Set 2</a> </td> <td>gfni</td> <td>Galois Field instructions </td> <td>avx512-vp2intersect</td> <td><a href="/wiki/AVX-512#VP2INTERSECT" title="AVX-512">AVX-512</a> vector intersection instructions on 32/64-bit integers </td> <th>8 </th></tr> <tr> <th>9 </th> <td>erms</td> <td>Enhanced <code>REP MOVSB/STOSB</code> </td> <td>vaes</td> <td>Vector <a href="/wiki/AES_instruction_set" title="AES instruction set">AES instruction set</a> (VEX-256/EVEX) </td> <td>srbds-ctrl</td> <td>Special Register Buffer Data Sampling Mitigations </td> <th>9 </th></tr> <tr> <th>10 </th> <td>invpcid</td> <td><code>INVPCID</code> instruction </td> <td>vpclmulqdq</td> <td><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL instruction set</a> (VEX-256/EVEX) </td> <td>md-clear</td> <td><code>VERW</code> instruction clears CPU buffers </td> <th>10 </th></tr> <tr> <th>11 </th> <td>rtm</td> <td><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> Restricted Transactional Memory </td> <td>avx512-vnni</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Vector Neural Network Instructions </td> <td>rtm-always-abort<a href="#cite_note-tsx-memory-ordering-131">[94]</a></td> <td>All TSX transactions are aborted </td> <th>11 </th></tr> <tr> <th>12 </th> <td>rdt-m/pqm</td> <td>Intel Resource Director (RDT) Monitoring or AMD Platform QOS Monitoring </td> <td>avx512-bitalg</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> BITALG instructions </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>12 </th></tr> <tr> <th>13 </th> <td></td> <td><a href="/wiki/X87" title="X87">x87</a> FPU CS and DS deprecated </td> <td>tme_en</td> <td>Total Memory Encryption MSRs available </td> <td>rtm-force-abort<a href="#cite_note-tsx-memory-ordering-131">[94]</a></td> <td>TSX_FORCE_ABORT (MSR <code>0x10f</code>) is available </td> <th>13 </th></tr> <tr> <th>14 </th> <td>mpx</td> <td><a href="/wiki/Intel_MPX" title="Intel MPX">Intel MPX</a> (Memory Protection Extensions) </td> <td>avx512-vpopcntdq</td> <td>AVX-512 Vector Population Count Double and Quad-word </td> <td>serialize</td> <td><code>SERIALIZE</code> instruction </td> <th>14 </th></tr> <tr> <th>15 </th> <td>rdt-a/pqe</td> <td>Intel Resource Director (RDT) Allocation or AMD Platform QOS Enforcement </td> <td>(fzm)<a href="#cite_note-leaf7_0_tdx-130">[a]</a></td> <td>? </td> <td>hybrid</td> <td>Mixture of CPU types in processor topology (e.g. <a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a>) </td> <th>15 </th></tr> <tr> <th>16 </th> <td>avx512-f</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Foundation </td> <td>la57</td> <td><a href="/wiki/Intel_5-level_paging" title="Intel 5-level paging">5-level paging</a> (57 address bits) </td> <td>tsxldtrk</td> <td><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> load address tracking suspend/resume instructions (<code>TSUSLDTRK</code> and <code>TRESLDTRK</code>) </td> <th>16 </th></tr> <tr> <th>17 </th> <td>avx512-dq</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Doubleword and Quadword Instructions </td> <td rowspan="5">mawau</td> <td rowspan="5">The value of userspace MPX Address-Width Adjust used by the <code>BNDLDX</code> and <code>BNDSTX</code> <a href="/wiki/Intel_MPX" title="Intel MPX">Intel MPX</a> instructions in 64-bit mode </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>17 </th></tr> <tr> <th>18 </th> <td>rdseed</td> <td><code><a href="/wiki/RDSEED" class="mw-redirect" title="RDSEED">RDSEED</a></code> instruction </td> <td>pconfig</td> <td>Platform configuration (Memory Encryption Technologies Instructions) </td> <th>18 </th></tr> <tr> <th>19 </th> <td>adx</td> <td><a href="/wiki/Intel_ADX" title="Intel ADX">Intel ADX</a> (Multi-Precision Add-Carry Instruction Extensions) </td> <td>lbr</td> <td>Architectural Last Branch Records </td> <th>19 </th></tr> <tr> <th>20 </th> <td>smap</td> <td><a href="/wiki/Supervisor_Mode_Access_Prevention" title="Supervisor Mode Access Prevention">Supervisor Mode Access Prevention</a> </td> <td>cet-ibt</td> <td>Control flow enforcement (CET): indirect branch tracking </td> <th>20 </th></tr> <tr> <th>21 </th> <td>avx512-ifma</td> <td><a href="/wiki/AVX-512#IFMA" title="AVX-512">AVX-512</a> Integer Fused Multiply-Add Instructions </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>21 </th></tr> <tr> <th>22 </th> <td>(pcommit)</td> <td>(<code>PCOMMIT</code> instruction, deprecated)<a href="#cite_note-133">[96]</a> </td> <td>rdpid</td> <td><code>RDPID</code> (Read Processor ID) instruction and IA32_TSC_AUX MSR </td> <td>amx-bf16</td> <td><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> tile computation on <a href="/wiki/Bfloat16_floating-point_format" title="Bfloat16 floating-point format">bfloat16</a> numbers </td> <th>22 </th></tr> <tr> <th>23 </th> <td>clflushopt</td> <td><code>CLFLUSHOPT</code> instruction </td> <td>kl</td> <td>AES Key Locker </td> <td>avx512-fp16</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> <a href="/wiki/FP16" class="mw-redirect" title="FP16">half-precision</a> floating-point arithmetic instructions<a href="#cite_note-134">[97]</a> </td> <th>23 </th></tr> <tr> <th>24 </th> <td>clwb</td> <td><code>CLWB</code> (Cache line writeback) instruction </td> <td>bus-lock-detect</td> <td>Bus lock debug exceptions </td> <td>amx-tile</td> <td><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> tile load/store instructions </td> <th>24 </th></tr> <tr> <th>25 </th> <td>pt</td> <td>Intel Processor Trace </td> <td>cldemote</td> <td><code>CLDEMOTE</code> (Cache line demote) instruction </td> <td>amx-int8</td> <td><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> tile computation on 8-bit integers </td> <th>25 </th></tr> <tr> <th>26 </th> <td>avx512-pf</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Prefetch Instructions </td> <td>(mprr)<a href="#cite_note-leaf7_0_tdx-130">[a]</a></td> <td>? </td> <td>ibrs / spec_ctrl</td> <td>Speculation Control, part of Indirect Branch Control (IBC): Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Prediction Barrier (IBPB)<a href="#cite_note-Intel_2018_SESEM-135">[98]</a><a href="#cite_note-136">[99]</a> </td> <th>26 </th></tr> <tr> <th>27 </th> <td>avx512-er</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Exponential and Reciprocal Instructions </td> <td>movdiri</td> <td><code>MOVDIRI</code> instruction </td> <td>stibp</td> <td>Single Thread Indirect Branch Predictor, part of IBC<a href="#cite_note-Intel_2018_SESEM-135">[98]</a> </td> <th>27 </th></tr> <tr> <th>28 </th> <td>avx512-cd</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Conflict Detection Instructions </td> <td>movdir64b</td> <td><code>MOVDIR64B</code> (64-byte direct store) instruction </td> <td>L1D_FLUSH</td> <td>IA32_FLUSH_CMD MSR </td> <th>28 </th></tr> <tr> <th>29 </th> <td>sha</td> <td><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA-1 and SHA-256 extensions</a> </td> <td>enqcmd</td> <td>Enqueue Stores and <code>EMQCMD</code>/<code>EMQCMDS</code> instructions </td> <td></td> <td>IA32_ARCH_CAPABILITIES MSR (lists speculative side channel mitigations<a href="#cite_note-Intel_2018_SESEM-135">[98]</a>) </td> <th>29 </th></tr> <tr> <th>30 </th> <td>avx512-bw</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Byte and Word Instructions </td> <td>sgx-lc</td> <td><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> Launch Configuration </td> <td></td> <td>IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities) </td> <th>30 </th></tr> <tr> <th>31 </th> <td>avx512-vl</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> Vector Length Extensions </td> <td>pks</td> <td>Protection keys for supervisor-mode pages </td> <td>ssbd</td> <td>Speculative Store Bypass Disable,<a href="#cite_note-Intel_2018_SESEM-135">[98]</a> as mitigation for <a href="/wiki/Speculative_Store_Bypass" title="Speculative Store Bypass">Speculative Store Bypass</a> (IA32_SPEC_CTRL) </td> <th>31 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-leaf7_0_tdx-130">^ <a href="#cite_ref-leaf7_0_tdx_130-0">a</a> <a href="#cite_ref-leaf7_0_tdx_130-1">b</a> <a href="#cite_ref-leaf7_0_tdx_130-2">c</a> As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel <a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> documentation<a href="#cite_note-intel_tdx_2020-132">[95]</a> and are not set in any known processor. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=7,_ECX=1:_Extended_Features">EAX=7, ECX=1: Extended Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=12" title="Edit section: EAX=7, ECX=1: Extended Features">edit</a>]</div> This returns extended feature flags in all four registers. <table class="wikitable"> <caption>CPUID EAX=7,ECX=1: Extended feature bits in EAX, EBX, ECX, and EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>sha512</td> <td><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA-512 extensions</a> </td> <td></td> <td>Intel PPIN (Protected Processor Inventory Number): IA32_PPIN_CTL (<code>04Eh</code>) and IA32_PPIN (<code>04Fh</code>) MSRs. </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>0 </th></tr> <tr> <th>1 </th> <td>sm3</td> <td><a href="/wiki/SM3_(hash_function)" title="SM3 (hash function)">SM3 hash extensions</a> </td> <td>pbndkb</td> <td>Total Storage Encryption: <code>PBNDKB</code> instruction and TSE_CAPABILITY (<code>9F1h</code>) MSR. </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>1 </th></tr> <tr> <th>2 </th> <td>sm4</td> <td><a href="/wiki/SM4_(cipher)" title="SM4 (cipher)">SM4 cipher extensions</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>legacy_reduced_isa</td> <td><a href="/wiki/X86S" class="mw-redirect" title="X86S">X86S</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>2 </th></tr> <tr> <th>3 </th> <td>rao-int</td> <td>Remote Atomic Operations on integers: <code>AADD</code>, <code>AAND</code>, <code>AOR</code>, <code>AXOR</code> instructions </td> <td>CPUIDMAXVAL_LIM_RMV</td> <td>If 1, then bit 22 of <code>IA32_MISC_ENABLE</code> cannot be set to 1 to limit the value returned by <code>CPUID.(EAX=0):EAX[7:0]</code>. </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td>avx-vnni</td> <td><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> Vector Neural Network Instructions (VNNI) (VEX encoded) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>sipi64</td> <td>64-bit SIPI (Startup InterProcessor Interrupt) </td> <td>avx-vnni-int8</td> <td>AVX VNNI INT8 instructions </td> <th>4 </th></tr> <tr> <th>5 </th> <td>avx512-bf16</td> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> instructions for <a href="/wiki/Bfloat16_floating-point_format" title="Bfloat16 floating-point format">bfloat16</a> numbers </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>MSR_IMM</td> <td> Immediate forms of the <code>RDMSR</code> and <code>WRMSRNS</code> instructions </td> <td>avx-ne-convert</td> <td>AVX no-exception FP conversion instructions (<a href="/wiki/Bfloat16" class="mw-redirect" title="Bfloat16">bfloat16</a>↔FP32 and <a href="/wiki/FP16" class="mw-redirect" title="FP16">FP16</a>→FP32) </td> <th>5 </th></tr> <tr> <th>6 </th> <td>lass</td> <td>Linear Address Space Separation (CR4 bit 27) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>6 </th></tr> <tr> <th>7 </th> <td>cmpccxadd</td> <td><code>CMPccXADD</code> instructions </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7 </th></tr> <tr> <th>8 </th> <td>archperfmonext</td> <td>Architectural Performance Monitoring Extended Leaf (EAX=23h) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>amx-complex</td> <td><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> support for "complex" tiles (<code>TCMMIMFP16PS</code> and <code>TCMMRLFP16PS</code>) </td> <th>8 </th></tr> <tr> <th>9 </th> <td>(dedup)<a href="#cite_note-137">[a]</a></td> <td>? </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>9 </th></tr> <tr> <th>10 </th> <td>fzrm</td> <td>Fast zero-length <code> REP MOVSB</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>avx-vnni-int16</td> <td>AVX VNNI INT16 instructions </td> <th>10 </th></tr> <tr> <th>11 </th> <td>fsrs</td> <td>Fast short <code>REP STOSB</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>11 </th></tr> <tr> <th>12 </th> <td>rsrcs</td> <td>Fast short <code>REP CMPSB</code> and <code>REP SCASB</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>12 </th></tr> <tr> <th>13 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>utmr</td> <td>User-timer events: IA32_UINTR_TIMER (<code>1B00h</code>) MSR </td> <th>13 </th></tr> <tr> <th>14 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>prefetchi</td> <td>Instruction-cache prefetch instructions (<code>PREFETCHIT0</code> and <code>PREFETCHIT1</code>) </td> <th>14 </th></tr> <tr> <th>15 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>user_msr</td> <td>User-mode MSR access instructions (<code>URDMSR</code> and <code>UWRMSR</code>) </td> <th>15 </th></tr> <tr> <th>16 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>16 </th></tr> <tr> <th>17 </th> <td>fred</td> <td>Flexible Return and Event Delivery<a href="#cite_note-intel_fred_spec-138">[100]</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>uiret-uif-from-rflags</td> <td>If 1, the <code>UIRET</code> (User Interrupt Return) instruction will set UIF (User Interrupt Flag) to the value of bit 1 of the RFLAGS image popped off the stack. </td> <th>17 </th></tr> <tr> <th>18 </th> <td>lkgs</td> <td><code>LKGS</code> Instruction<a href="#cite_note-intel_fred_spec-138">[100]</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>cet-sss</td> <td>If 1, then Control-Flow Enforcement (CET) Supervisor Shadow Stacks (SSS) are guaranteed not to become prematurely busy as long as shadow stack switching does not cause page faults on the stack being switched to.<a href="#cite_note-139">[101]</a><a href="#cite_note-140">[102]</a> </td> <th>18 </th></tr> <tr> <th>19 </th> <td>wrmsrns</td> <td><code>WRMSRNS</code> instruction (non-serializing write to <a href="/wiki/Model-specific_register" title="Model-specific register">MSRs</a>) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>avx10</td> <td>AVX10 Converged Vector ISA (see also leaf 24h)<a href="#cite_note-intel_avx10_1-141">[103]</a> </td> <th>19 </th></tr> <tr> <th>20 </th> <td>nmi_src</td> <td><a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a> source reporting<a href="#cite_note-intel_fred_spec-138">[100]</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>20 </th></tr> <tr> <th>21 </th> <td>amx-fp16</td> <td>AMX instructions for <a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">FP16</a> numbers </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>APX_F</td> <td><a href="/wiki/X86#APX_(Advanced_Performance_Extensions)" title="X86">Advanced Performance Extensions</a>, Foundation (adds REX2 and extended <a href="/wiki/EVEX_prefix" title="EVEX prefix">EVEX prefix</a> encodings to support 32 GPRs, as well as some new instructions)<a href="#cite_note-intel_apx20-142">[104]</a> </td> <th>21 </th></tr> <tr> <th>22 </th> <td>hreset</td> <td><code>HRESET</code> instruction, IA32_HRESET_ENABLE (<code>17DAh</code>) MSR, and Processor History Reset Leaf (EAX=20h) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>22 </th></tr> <tr> <th>23 </th> <td>avx-ifma</td> <td>AVX IFMA instructions </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>mwait</td> <td>MWAIT instruction<a href="#cite_note-143">[b]</a> </td> <th>23 </th></tr> <tr> <th>24 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>24 </th></tr> <tr> <th>25 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>25 </th></tr> <tr> <th>26 </th> <td>lam</td> <td>Linear Address Masking </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>26 </th></tr> <tr> <th>27 </th> <td>msrlist</td> <td><code>RDMSRLIST</code> and <code>WRMSRLIST</code> instructions, and the IA32_BARRIER (<code>02Fh</code>) MSR </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>27 </th></tr> <tr> <th>28 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>28 </th></tr> <tr> <th>29 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>29 </th></tr> <tr> <th>30 </th> <td>invd_disable_post_bios_done</td> <td>If 1, supports <code>INVD</code> instruction execution prevention after BIOS Done. </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>30 </th></tr> <tr> <th>31 </th> <td>MOVRS</td> <td><code>MOVRS</code> and <code>PREFETCHRST2</code> instructions supported (memory read/prefetch with read-shared hint) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-137"><a href="#cite_ref-137">^</a> As of April 2024, the DEDUP bit is listed only in Intel <a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> documentation<a href="#cite_note-intel_tdx_2020-132">[95]</a> and is not set in any known processor. </li> <li id="cite_note-143"><a href="#cite_ref-143">^</a> Support for the <code>MWAIT</code> instruction may be indicated by either CPUID.(EAX=1).ECX[3] or CPUID.(EAX=7,ECX=1).EDX[23]. (One or both may be set.) The former indicates support for the <code>MONITOR</code> instruction as well, while the latter does not indicate one way or another whether the <code>MONITOR</code> instruction is present. <code>MWAIT</code> without <code>MONITOR</code> may be present in systems that support the "Monitorless MWAIT" feature (which is itself indicated by CPUID.(EAX=5).ECX[3].) </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=7,_ECX=2:_Extended_Features">EAX=7, ECX=2: Extended Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=13" title="Edit section: EAX=7, ECX=2: Extended Features">edit</a>]</div> This returns extended feature flags in EDX. EAX, EBX and ECX are reserved. <table class="wikitable"> <caption>CPUID EAX=7,ECX=2: Extended feature bits in EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EDX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>psfd</td> <td>Fast Store Forwarding Predictor disable supported. (<code>SPEC_CTRL</code> (MSR <code>48h</code>) bit 7) </td></tr> <tr> <th>1 </th> <td>ipred_ctrl</td> <td>IPRED_DIS controls<a href="#cite_note-intel_bhi-144">[105]</a> supported. (<code>SPEC_CTRL</code> bits 3 and 4) IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved. </td></tr> <tr> <th>2 </th> <td>rrsba_ctrl</td> <td>RRSBA behavior<a href="#cite_note-145">[106]</a><a href="#cite_note-intel_bhi-144">[105]</a> disable supported. (<code>SPEC_CTRL</code> bits 5 and 6) </td></tr> <tr> <th>3 </th> <td>ddpd_u</td> <td>Data Dependent Prefetcher disable supported. (<code>SPEC_CTRL</code> bit 8) </td></tr> <tr> <th>4 </th> <td>bhi_ctrl</td> <td>BHI_DIS_S behavior<a href="#cite_note-intel_bhi-144">[105]</a> enable supported. (<code>SPEC_CTRL</code> bit 10) BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3. </td></tr> <tr> <th>5 </th> <td>mcdt_no</td> <td>If set, the processor does not exhibit <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">MXCSR</a> configuration dependent timing. </td></tr> <tr> <th>6 </th> <td></td> <td>UC-lock disable feature supported. </td></tr> <tr> <th>7 </th> <td>monitor_mitg_no</td> <td>If set, indicates that the <code>MONITOR</code>/<code>UMONITOR</code> instructions are not affected by performance/power issues caused by the instructions exceeding the capacity of an internal monitor tracking table. </td></tr> <tr> <th> 31:8   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=0Dh:_XSAVE_Features_and_State_Components">EAX=0Dh: XSAVE Features and State Components</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=14" title="Edit section: EAX=0Dh: XSAVE Features and State Components">edit</a>]</div> This leaf is used to enumerate XSAVE features and state components. The XSAVE instruction set extension is designed to save/restore CPU extended state (typically for the purpose of <a href="/wiki/Context_switch" title="Context switch">context switching</a>) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The <code>EAX=0Dh</code> CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits. The state-components can be subdivided into two groups: user-state (state-items that are visible to the application, e.g. <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration). The user-state items are enabled by setting their associated bits in the <code>XCR0</code> control register, while the supervisor-state items are enabled by setting their associated bits in the <code>IA32_XSS</code> (<code>0DA0h</code>) MSR - the indicated state items then become the state-components that can be saved and restored with the <code>XSAVE</code>/<code>XRSTOR</code> family of instructions. <div style="width:100%; height:1em; clear:both;"></div> The XSAVE mechanism can handle up to 63 state-components in this manner. State-components 0 and 1 (<a href="/wiki/X87" title="X87">x87</a> and <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, respectively) have fixed offsets and sizes - for state-components 2 to 62, their sizes, offsets and a few additional flags can be queried by executing <code>CPUID</code> with <code>EAX=0Dh</code> and <code>ECX</code> set to the index of the state-component. This will return the following items in EAX, EBX and ECX (with EDX being reserved): <table class="wikitable"> <caption>CPUID EAX=0Dh, ECX≥2: XSAVE state-component information </caption> <tbody><tr> <th>Bit</th> <th>EAX</th> <th>EBX</th> <th>ECX</th> <th>Bit </th></tr> <tr> <th>0 </th> <td rowspan="3">Size in bytes of state-component </td> <td rowspan="3">Offset of state-component from the start of the <code>XSAVE</code>/<code>XRSTOR</code> save area (This offset is 0 for supervisor state-components, since these can only be saved with the <code>XSAVES</code>/<code>XRSTORS</code> instruction, which use compacting.) </td> <td>User/supervisor state-component: <ul><li>0=user-state (enabled through <code>XCR0</code>)</li> <li>1=supervisor-state (enabled through <code>IA32_XSS</code>)</li></ul> </td> <th>0 </th></tr> <tr> <th>1 </th> <td>64-byte alignment enable when state save compaction is used. If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one. </td> <th>1 </th></tr> <tr> <th> 31:2   </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:2 </th></tr></tbody></table> Attempting to query an unsupported state-component in this manner results in EAX,EBX,ECX and EDX all being set to 0. Sub-leaves 0 and 1 of <code>CPUID</code> leaf <code>0Dh</code> are used to provide feature information: <table class="wikitable"> <caption>CPUID EAX=0Dh,ECX=0: XSAVE features </caption> <tbody><tr> <th>EBX</th> <th>ECX</th> <th>EDX:EAX </th></tr> <tr> <td>Maximum size (in bytes) of XSAVE save area for the set of state-components currently set in <code>XCR0</code>. </td> <td>Maximum size (in bytes) of XSAVE save area if all state-components supported by <code>XCR0</code> on this CPU were enabled at the same time. </td> <td>64-bit bitmap of state-components supported by <code>XCR0</code> on this CPU. </td></tr></tbody></table> <table class="wikitable"> <caption>CPUID EAX=0Dh,ECX=1: XSAVE extended features </caption> <tbody><tr> <th>EAX</th> <th>EBX</th> <th>EDX:ECX </th></tr> <tr> <td>XSAVE feature flags (see below table) </td> <td>Size (in bytes) of XSAVE area containing all the state-components currently set in <code>XCR0</code> and <code>IA32_XSS</code> combined. </td> <td>64-bit bitmap of state-components supported by <code>IA32_XSS</code> on this CPU. </td></tr></tbody></table> <table class="wikitable"> <caption>EAX=0Dh,ECX=1: XSAVE feature flags in EAX </caption> <tbody><tr> <th rowspan="2">Bit</th> <th colspan="2">EAX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>xsaveopt</td> <td><code>XSAVEOPT</code> instruction: save state-components that have been modified since last <code>XRSTOR</code> </td></tr> <tr> <th>1 </th> <td>xsavec</td> <td><code>XSAVEC</code> instruction: save/restore state with compaction </td></tr> <tr> <th>2 </th> <td>xgetbv_ecx1</td> <td><code>XGETBV</code> with <code>ECX=1</code> support </td></tr> <tr> <th>3 </th> <td>xss</td> <td><code>XSAVES</code> and <code>XRSTORS</code> instructions and <code>IA32_XSS</code> MSR: save/restore state with compaction, including supervisor state. </td></tr> <tr> <th>4 </th> <td>xfd</td> <td>XFD (Extended Feature Disable) supported </td></tr> <tr> <th> 31:5   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> As of July 2023, the XSAVE state-components that have been architecturally defined are: <table class="wikitable"> <caption>XSAVE State-components </caption> <tbody><tr> <th>Index</th> <th>Description</th> <th>Enabled with </th></tr> <tr> <th>0 </th> <td><a href="/wiki/X87" title="X87">x87</a> state</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">XCR0<a href="#cite_note-146">[a]</a> </td></tr> <tr> <th>1 </th> <td><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> state: <code>XMM0</code>-<code>XMM15</code> and <code>MXCSR</code></td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">XCR0 </td></tr> <tr> <th>2 </th> <td><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> state: top halves of <code>YMM0</code> to <code>YMM15</code> </td></tr> <tr> <th>3 </th> <td><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> state: <code>BND0</code>-<code>BND3</code> bounds registers </td></tr> <tr> <th>4 </th> <td>MPX state: <code>BNDCFGU</code> and <code>BNDSTATUS</code> registers </td></tr> <tr> <th>5 </th> <td><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> state: opmask registers <code>k0</code>-<code>k7</code> </td></tr> <tr> <th>6 </th> <td>AVX-512 "ZMM_Hi256" state: top halves of <code>ZMM0</code> to <code>ZMM15</code> </td></tr> <tr> <th>7 </th> <td>AVX-512 "Hi16_ZMM" state: <code>ZMM16</code>-<code>ZMM31</code> </td></tr> <tr> <th>8 </th> <td>Processor Trace state</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">IA32_XSS </td></tr> <tr> <th>9 </th> <td>PKRU (User Protection Keys) register</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">XCR0 </td></tr> <tr> <th>10 </th> <td>PASID (Process Address Space ID) state</td> <td rowspan="7" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">IA32_XSS </td></tr> <tr> <th>11 </th> <td>CET_U state (Control-flow Enforcement Technology: user-mode functionality MSRs) </td></tr> <tr> <th>12 </th> <td>CET_S state (CET: shadow stack pointers for rings 0,1,2) </td></tr> <tr> <th>13 </th> <td>HDC (Hardware Duty Cycling) state </td></tr> <tr> <th>14 </th> <td>UINTR (User-Mode Interrupts) state </td></tr> <tr> <th>15 </th> <td>LBR (Last Branch Record) state </td></tr> <tr> <th>16 </th> <td>HWP (Hardware P-state control) state </td></tr> <tr> <th>17 </th> <td><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> tile configuration state: <code>TILECFG</code></td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">XCR0 </td></tr> <tr> <th>18 </th> <td>AMX tile data registers: <code>tmm0</code>-<code>tmm7</code> </td></tr> <tr> <th>19 </th> <td><a href="/wiki/X86#APX_(Advanced_Performance_Extensions)" title="X86">APX</a> extended general-purpose registers: <code>r16</code>-<code>r31</code><a href="#cite_note-intel_apx20-142">[104]</a> </td></tr> <tr> <th> 20 to 61   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>62 </th> <td>Lightweight Profiling (LWP) (AMD only)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">XCR0 </td></tr> <tr> <th>63 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved)<a href="#cite_note-147">[b]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-146"><a href="#cite_ref-146">^</a> Bit 0 of <code>XCR0</code> is hardwired to 1, so that the XSAVE instructions will always support save/restore of x87 state. </li> <li id="cite_note-147"><a href="#cite_ref-147">^</a> For the <code>XCR0</code> and <code>IA32_XSS</code> registers, bit 63 is reserved specifically for bit vector expansion - this precludes the existence of a state-component 63. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=12h:_SGX_Capabilities">EAX=12h: SGX Capabilities</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=15" title="Edit section: EAX=12h: SGX Capabilities">edit</a>]</div> This leaf provides information about the supported capabilities of the Intel <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">Software Guard Extensions</a> (SGX) feature. The leaf provides multiple sub-leaves, selected with ECX. Sub-leaf 0 provides information about supported SGX leaf functions in EAX and maximum supported SGX enclave sizes in EDX; ECX is reserved. EBX provides a bitmap of bits that can be set in the MISCSELECT field in the SECS (SGX Enclave Control Structure) - this field is used to control information written to the MISC region of the SSA (SGX Save State Area) when an AEX (SGX Asynchronous Enclave Exit) occurs. <table class="wikitable"> <caption>CPUID EAX=12h,ECX=0: <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> leaf functions, MISCSELECT and maximum-sizes </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="19"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="19"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>sgx1</td> <td>SGX1 leaf functions </td> <td>EXINFO</td> <td>MISCSELECT: report information about page fault and general protection exception that occurred inside enclave </td> <td rowspan="8">MaxEnclaveSize_Not64</td> <td rowspan="8">Log2 of maximum enclave size supported in non-64-bit mode </td> <th>0 </th></tr> <tr> <th>1 </th> <td>sgx2</td> <td>SGX2 leaf functions </td> <td>CPINFO</td> <td>MISCSELECT: report information about control protection exception that occurred inside enclave </td> <th>1 </th></tr> <tr> <th>2 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>2 </th></tr> <tr> <th>3 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>4 </th></tr> <tr> <th>5 </th> <td>oss</td> <td><code>ENCLV</code> leaves: <code>EINCVIRTCHILD</code>, <code>EDECVIRTCHILD</code>, and <code>ESETCONTEXT</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>5 </th></tr> <tr> <th>6 </th> <td></td> <td><code>ENCLS</code> leaves: <code>ETRACKC</code>, <code>ERDINFO</code>, <code>ELDBC</code>, <code>ELDUC</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>6 </th></tr> <tr> <th>7 </th> <td></td> <td><code>ENCLU</code> leaf: <code>EVERIFYREPORT2</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7 </th></tr> <tr> <th>8 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td rowspan="8">MaxEnclaveSize_64</td> <td rowspan="8">Log2 of maximum enclave size supported in 64-bit mode </td> <th>8 </th></tr> <tr> <th>9 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>9 </th></tr> <tr> <th>10 </th> <td></td> <td><code>ENCLS</code> leaf: <code>EUPDATESVN</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>10 </th></tr> <tr> <th>11 </th> <td></td> <td><code>ENCLU</code> leaf: <code>EDECSSA</code> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>11 </th></tr> <tr> <th>12 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>12 </th></tr> <tr> <th>13 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>13 </th></tr> <tr> <th>14 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>14 </th></tr> <tr> <th>15 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>15 </th></tr> <tr> <th> 31:16   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:16   </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> Sub-leaf 1 provides a bitmap of which bits can be set in the 128-bit ATTRIBUTES field of SECS in EDX:ECX:EBX:EAX (this applies to the SECS copy used as input to the <code>ENCLS[ECREATE]</code> leaf function). The top 64 bits (given in EDX:ECX) are a bitmap of which bits can be set in the XFRM (X-feature request mask) - this mask is a bitmask of which CPU state-components (see leaf 0Dh) will be saved to the SSA in case of an AEX; this has the same layout as the <code>XCR0</code> control register. The other bits are given in EAX and EBX, as follows: <table class="wikitable"> <caption>CPUID EAX=12h,ECX=1: <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> settable bits in SECS.ATTRIBUTES </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="14"> </th> <th colspan="2">EBX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td style="background:lightgrey">(INIT)</td> <td style="text-align:center; background:lightgrey;">(must be 0)<a href="#cite_note-148">[a]</a> </td> <td rowspan="12" colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>0 </th></tr> <tr> <th>1 </th> <td>DEBUG</td> <td>Permit debugger to read and write enclave data using <code>EDBGRD</code> and <code>EDBGWR</code> </td> <th>1 </th></tr> <tr> <th>2 </th> <td>MODE64BIT</td> <td>64-bit-mode enclave </td> <th>2 </th></tr> <tr> <th>3 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td>PROVISIONKEY</td> <td>Provisioning key available from <code>EGETKEY</code> </td> <th>4 </th></tr> <tr> <th>5 </th> <td>EINITTOKEN_KEY</td> <td><code>EINIT</code> token key available from <code>EGETKEY</code> </td> <th>5 </th></tr> <tr> <th>6 </th> <td>CET</td> <td>CET (Control-Flow Enforcement Technology) attributes enable </td> <th>6 </th></tr> <tr> <th>7 </th> <td>KSS</td> <td>Key Separation and Sharing </td> <th>7 </th></tr> <tr> <th>8 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>8 </th></tr> <tr> <th>9 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>9 </th></tr> <tr> <th>10 </th> <td>AEXNOTIFY</td> <td>Threads inside enclave may receive AEX notifications<a href="#cite_note-149">[107]</a> </td> <th>10 </th></tr> <tr> <th> 31:11   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:11   </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-148"><a href="#cite_ref-148">^</a> For the copy of the SECS that exists inside an exclave, bit 0 (INIT) of SECS.ATTRIBUTES is used to indicate that the enclave has been initialized with <code>ENCLS[EINIT]</code>. This bit must be 0 in the SECS copy that is given as input to <code>ENCLS[CREATE]</code>. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> Sub-leaves 2 and up are used to provide information about which physical memory regions are available for use as EPC (Enclave Page Cache) sections under SGX. <table class="wikitable"> <caption>CPUID EAX=12h,ECX≥2: <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> Enclave Page Cache section information </caption> <tbody><tr> <th>Bits </th> <th>EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th>ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th>EDX </th> <th>Bits </th></tr> <tr> <th>3:0 </th> <td>Sub-leaf type: <ul><li>0000: Invalid</li> <li>0001: EPC section</li> <li>other: reserved</li></ul> </td> <td rowspan="3">Bits 51:32 of physical base address of EPC section </td> <td>EPC Section properties: <ul><li>0000: Invalid</li> <li>0001: Has confidentiality, integrity, and replay protection</li> <li>0010: Has confidentiality protection only</li> <li>0011: Has confidentiality and integrity protection</li> <li>other: reserved</li></ul> </td> <td rowspan="3">Bits 51:32 of size of EPC section </td> <th>3:0 </th></tr> <tr> <th> 11:4   </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th> 11:4   </th></tr> <tr> <th> 19:12   </th> <td rowspan="2">Bits 31:12 of physical base address of EPC section </td> <td rowspan="2">Bits 31:12 of size of EPC section </td> <th> 19:12   </th></tr> <tr> <th> 31:20   </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:20   </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=14h,_ECX=0:_Processor_Trace">EAX=14h, ECX=0: Processor Trace</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=16" title="Edit section: EAX=14h, ECX=0: Processor Trace">edit</a>]</div> This sub-leaf provides feature information for Intel <a href="/wiki/Branch_trace" title="Branch trace">Processor Trace</a> (also known as Real Time Instruction Trace). The value returned in EAX is the index of the highest sub-leaf supported for CPUID with EAX=14h. EBX and ECX provide feature flags, EDX is reserved. <table class="wikitable"> <caption>CPUID EAX=14h,ECX=0: Processor Trace feature bits in EBX and ECX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EBX </th> <th rowspan="14"> </th> <th colspan="2">ECX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td></td> <td><a href="/wiki/Control_register#CR3" title="Control register">CR3</a> filtering supported </td> <td>topaout</td> <td>ToPA (Table of Physical Addresses) output mechanism for trace packets supported </td> <th>0 </th></tr> <tr> <th>1 </th> <td></td> <td>Configurable PSB (Packet Stream Boundary) packet rate and Cycle-Accurate Mode (CYC packets) supported </td> <td>mentry</td> <td>ToPA tables can contain hold multiple output entries </td> <th>1 </th></tr> <tr> <th>2 </th> <td></td> <td>IP filtering, TraceStop filtering and preservation of PT MSRs across warm reset supported </td> <td>snglrngout</td> <td>Single-Range Output scheme supported </td> <th>2 </th></tr> <tr> <th>3 </th> <td></td> <td>MTC (Mini Time Counter) timing packets supported, and suppression of COFI (Change of Flow Instructions) packets supported. </td> <td></td> <td>Output to Trace Transport subsystem supported </td> <th>3 </th></tr> <tr> <th>4 </th> <td>ptwrite</td> <td><code>PTWRITE</code> instruction supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>4 </th></tr> <tr> <th>5 </th> <td></td> <td>Power Event Trace supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>5 </th></tr> <tr> <th>6 </th> <td></td> <td>Preservation of PSB and PMI (performance monitoring interrupt) supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>6 </th></tr> <tr> <th>7 </th> <td></td> <td>Event Trace packet generation supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7 </th></tr> <tr> <th>8 </th> <td></td> <td>TNT (Branch Taken-Not-Taken) packet generation disable supported. </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>8 </th></tr> <tr> <th>9 </th> <td></td> <td>PTTT (Processor Trace Trigger Tracing) supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>9 </th></tr> <tr> <th> 30:10   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th> 30:10   </th></tr> <tr> <th>31 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td> </td> <td>IP (Instruction Pointer) format for trace packets that contain IP payloads: <ul><li>0=RIP (effective-address IP)</li> <li>1=LIP (linear-address IP, with CS base address added)</li></ul> </td> <th>31 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=15h_and_EAX=16h:_CPU,_TSC,_Bus_and_Core_Crystal_Clock_Frequencies">EAX=15h and EAX=16h: CPU, TSC, Bus and Core Crystal Clock Frequencies</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=17" title="Edit section: EAX=15h and EAX=16h: CPU, TSC, Bus and Core Crystal Clock Frequencies">edit</a>]</div> These two leaves provide information about various frequencies in the CPU in EAX, EBX and ECX (EDX is reserved in both leaves). <table class="wikitable"> <caption>CPUID EAX=15h: TSC and Core <a href="/wiki/Crystal_oscillator" title="Crystal oscillator">Crystal</a> frequency information </caption> <tbody><tr> <th>EAX</th> <th>EBX</th> <th>ECX </th></tr> <tr> <td>Ratio of TSC frequency to Core Crystal Clock frequency, denominator </td> <td>Ratio of TSC frequency to Core Crystal Clock frequency, numerator<a href="#cite_note-unsupp_1516-150">[a]</a> </td> <td>Core Crystal Clock frequency, in units of <a href="/wiki/Hertz" title="Hertz">Hz</a><a href="#cite_note-unsupp_1516-150">[a]</a> </td></tr></tbody></table> <table class="wikitable"> <caption>CPUID EAX=16h: Processor and Bus specification frequencies<a href="#cite_note-151">[b]</a> </caption> <tbody><tr> <th>Bits</th> <th>EAX</th> <th>EBX</th> <th>ECX</th> <th>Bits </th></tr> <tr> <th>15:0 </th> <td>Processor Base Frequency (in MHz)<a href="#cite_note-unsupp_1516-150">[a]</a> </td> <td>Processor Maximum Frequency (in MHz)<a href="#cite_note-unsupp_1516-150">[a]</a> </td> <td>Bus/Reference frequency (in MHz)<a href="#cite_note-unsupp_1516-150">[a]</a> </td> <th>15:0 </th></tr> <tr> <th>31:16 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:16 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-unsupp_1516-150">^ <a href="#cite_ref-unsupp_1516_150-0">a</a> <a href="#cite_ref-unsupp_1516_150-1">b</a> <a href="#cite_ref-unsupp_1516_150-2">c</a> <a href="#cite_ref-unsupp_1516_150-3">d</a> <a href="#cite_ref-unsupp_1516_150-4">e</a> Field not enumerated if zero. </li> <li id="cite_note-151"><a href="#cite_ref-151">^</a> The frequency values reported by leaf 16h are the processor's specification frequencies - they are constant for the given processor and do not necessarily reflect the actual CPU clock speed at the time CPUID is called. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> If the returned values in EBX and ECX of leaf 15h are both nonzero, then the TSC (<a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a>) frequency in Hz is given by <code>TSCFreq = ECX*(EBX/EAX)</code>. On some processors (e.g. Intel <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>), CPUID_15h_ECX is zero but CPUID_16h_EAX is present and not zero. On all known processors where this is the case,<a href="#cite_note-152">[108]</a> the TSC frequency is equal to the Processor Base Frequency, and the Core Crystal Clock Frequency in Hz can be computed as <code>CoreCrystalFreq = (CPUID_16h_EAX * 10000000) * (CPUID_15h_EAX/CPUID_15h_EBX)</code>. On processors that enumerate the TSC/Core Crystal Clock ratio in CPUID leaf 15h, the <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">APIC</a> timer frequency will be the Core Crystal Clock frequency divided by the divisor specified by the APIC's Divide Configuration Register.<a href="#cite_note-153">[109]</a> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=17h:_SoC_Vendor_Attribute_Enumeration">EAX=17h: SoC Vendor Attribute Enumeration</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=18" title="Edit section: EAX=17h: SoC Vendor Attribute Enumeration">edit</a>]</div> This leaf is present in systems where an x86 CPU <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP core</a> is implemented in an SoC (<a href="/wiki/System_on_chip" class="mw-redirect" title="System on chip">System on chip</a>) from another vendor - whereas the other leaves of <code>CPUID</code> provide information about the x86 CPU core, this leaf provides information about the SoC. This leaf takes a sub-leaf index in ECX. Sub-leaf 0 returns a maximum sub-leaf index in EAX (at least 3), and SoC identification information in EBX/ECX/EDX: <table class="wikitable"> <caption>CPUID EAX=17h,ECX=0: SoC identification information </caption> <tbody><tr> <th>Bit </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th>ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th>EDX </th> <th>Bit </th></tr> <tr> <th>15:0 </th> <td>SoC Vendor ID </td> <td rowspan="3">SoC Project ID </td> <td rowspan="3">SoC Stepping ID within an SoC project </td> <th>15:0 </th></tr> <tr> <th>16 </th> <td>SoC Vendor ID scheme <ul><li>0 : Vendor IDs assigned by Intel<a href="#cite_note-155">[a]</a></li> <li>1 : Industry standard enumeration scheme<a href="#cite_note-156">[b]</a></li></ul> </td> <th>16 </th></tr> <tr> <th>31:17 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:17 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-155"><a href="#cite_ref-155">^</a> As of May 2024, the following Vendor IDs are known to have been assigned by Intel: <table class="wikitable sortable"> <tbody><tr> <th>ID</th> <th>Vendor </th></tr> <tr> <td>1</td> <td><a href="/wiki/Spreadtrum" class="mw-redirect" title="Spreadtrum">Spreadtrum</a><a href="#cite_note-154">[110]</a> </td></tr></tbody></table> </li> <li id="cite_note-156"><a href="#cite_ref-156">^</a> As of May 2024, Intel documentation does not specify which "Industry Standard" enumeration scheme to use for the Vendor ID in EBX[15:0] if EBX[16] is set. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> Sub-leaves 1 to 3 return a 48-byte SoC vendor brand string in <a href="/wiki/UTF-8" title="UTF-8">UTF-8</a> format. Sub-leaf 1 returns the first 16 bytes in EAX,EBX,ECX,EDX (in that order); sub-leaf 2 returns the next 16 bytes and sub-leaf 3 returns the last 16 bytes. The string is allowed but not required to be <a href="/wiki/Null-terminated_string" title="Null-terminated string">null-terminated</a>. <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=19h:_Intel_Key_Locker_Features">EAX=19h: Intel Key Locker Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=19" title="Edit section: EAX=19h: Intel Key Locker Features">edit</a>]</div> This leaf provides feature information for Intel Key Locker in EAX, EBX and ECX. EDX is reserved. <table class="wikitable"> <caption>CPUID EAX=19h: Key Locker feature bits in EAX, EBX and ECX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="8"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="8"> </th> <th colspan="2">ECX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td></td> <td>Key Locker restriction of CPL0-only supported </td> <td>aes_kle</td> <td><a href="/wiki/Advanced_Encryption_Standard" title="Advanced Encryption Standard">AES</a> "Key Locker" Instructions enabled </td> <td></td> <td>No-backup parameter to <code>LOADIWKEY</code> supported </td> <th>0 </th></tr> <tr> <th>1 </th> <td></td> <td>Key Locker restriction of no-encrypt supported </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td></td> <td>KeySource encoding of 1 (randomization of internal wrapping key) supported </td> <th>1 </th></tr> <tr> <th>2 </th> <td></td> <td>Key Locker restriction of no-decrypt supported </td> <td>aes_wide_kl</td> <td><a href="/wiki/Advanced_Encryption_Standard" title="Advanced Encryption Standard">AES</a> "Wide Key Locker" Instructions </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>2 </th></tr> <tr> <th>3 </th> <td></td> <td>(Process Restriction)<a href="#cite_note-157">[a]</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>kl_msrs</td> <td>"Key Locker" MSRs </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>4 </th></tr> <tr> <th> 31:5   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:5   </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-157"><a href="#cite_ref-157">^</a> As of April 2024, the "Process Restriction" bit is listed only in Intel <a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> documentation<a href="#cite_note-intel_tdx_2020-132">[95]</a> and is not set in any known processor. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=1Dh:_Tile_Information">EAX=1Dh: Tile Information</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=20" title="Edit section: EAX=1Dh: Tile Information">edit</a>]</div> When <code>ECX=0</code>, the highest supported "palette" subleaf is enumerated in EAX. When <code>ECX≥1</code>, information on palette n is returned. <table class="wikitable"> <caption>CPUID EAX=1Dh,ECX≥1: Tile Palette n Information </caption> <tbody><tr> <th rowspan="2">Bits </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bits </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>15:0 </th> <td>total_tile_bytes</td> <td>Size of all tile registers, in bytes (8192) </td> <td>bytes_per_row</td> <td>(64) </td> <td>max_rows</td> <td>(16) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>15:0 </th></tr> <tr> <th>31:16 </th> <td>bytes_per_tile</td> <td>Size of one tile, in bytes (1024) </td> <td>max_names</td> <td>Number of tile registers (8) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:16 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=1Eh,_ECX=0:_TMUL_Information">EAX=1Eh, ECX=0: <code>TMUL</code> Information</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=21" title="Edit section: EAX=1Eh, ECX=0: TMUL Information">edit</a>]</div> This leaf returns information on the <code>TMUL</code> (tile multiplier) unit. <table class="wikitable"> <caption>CPUID EAX=1Eh,ECX=0: <code>TMUL</code> Information </caption> <tbody><tr> <th rowspan="2">Bits </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="6"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="6"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="6"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bits </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>7:0 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>tmul_maxk</td> <td>Maximum number of rows or columns (16) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7:0 </th></tr> <tr> <th>15:8 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>tmul_maxn</td> <td>Maximum number of bytes per column (64) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>15:8 </th></tr> <tr> <th>23:16 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>23:16 </th></tr> <tr> <th>31:24 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:24 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=1Eh,_ECX=1:_TMUL_Information">EAX=1Eh, ECX=1: <code>TMUL</code> Information</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=22" title="Edit section: EAX=1Eh, ECX=1: TMUL Information">edit</a>]</div> This leaf returns feature flags on the <code>TMUL</code> (tile multiplier) unit. <table class="wikitable"> <caption>CPUID EAX=1Eh,ECX=0: <code>TMUL</code> Information </caption> <tbody><tr> <th rowspan="2">Bits </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bits </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>amx-int8</td> <td>8-bit integer support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>0 </th></tr> <tr> <th>1 </th> <td>amx-bf16</td> <td><a href="/wiki/Bfloat16" class="mw-redirect" title="Bfloat16">bfloat16</a> support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>1 </th></tr> <tr> <th>2 </th> <td>amx-complex</td> <td>Complex number support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>2 </th></tr> <tr> <th>3 </th> <td>amx-fp16</td> <td><a href="/w/index.php?title=Half-precision_floating_point&action=edit&redlink=1" class="new" title="Half-precision floating point (page does not exist)">float16</a> support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3 </th></tr> <tr> <th>4 </th> <td>amx-fp8</td> <td>float8 support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>4 </th></tr> <tr> <th>5 </th> <td>amx-transpose</td> <td>Transposition instruction support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>5 </th></tr> <tr> <th>6 </th> <td>amx-tf32</td> <td>tf32/fp19 support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>6 </th></tr> <tr> <th>7 </th> <td>amx-avx512</td> <td>AMX-AVX512 support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7 </th></tr> <tr> <th>8 </th> <td>amx-movrs</td> <td>AMX-MOVRS support </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>8 </th></tr> <tr> <th>31:9 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:9 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=21h:_Reserved_for_TDX_enumeration">EAX=21h: Reserved for TDX enumeration</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=23" title="Edit section: EAX=21h: Reserved for TDX enumeration">edit</a>]</div> When Intel TDX (<a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">Trust Domain Extensions</a>) is active, attempts to execute the <code>CPUID</code> instruction by a TD (Trust Domain) guest will be intercepted by the TDX module. This module will, when <code>CPUID</code> is invoked with <code>EAX=21h</code> and <code>ECX=0</code> (leaf <code>21h</code>, sub-leaf 0), return the index of the highest supported sub-leaf for leaf <code>21h</code> in <code>EAX</code> and a TDX module vendor ID string as a 12-byte ASCII string in EBX,EDX,ECX (in that order). Intel's own module implementation returns the vendor ID string <code>"IntelTDX    "</code> (with four trailing spaces)<a href="#cite_note-158">[111]</a> - for this module, additional feature information is not available through <code>CPUID</code> and must instead be obtained through the TDX-specific <code>TDCALL</code> instruction. This leaf is reserved in hardware and will (on processors whose highest basic leaf is <code>21h</code> or higher) return 0 in EAX/EBX/ECX/EDX when run directly on the CPU. <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=24h,_ECX=0:_AVX10_Converged_Vector_ISA">EAX=24h, ECX=0: AVX10 Converged Vector ISA</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=24" title="Edit section: EAX=24h, ECX=0: AVX10 Converged Vector ISA">edit</a>]</div> This returns a maximum supported sub-leaf in EAX and AVX10 feature information in EBX.<a href="#cite_note-intel_avx10_1-141">[103]</a> (ECX and EDX are reserved.) <table class="wikitable"> <caption>CPUID EAX=24h, ECX=0: AVX10 feature bits in EBX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EBX </th></tr> <tr> <th>Short </th> <th>Feature </th></tr> <tr> <th>7:0 </th> <td></td> <td>AVX10 Converged Vector ISA version (≥1) </td></tr> <tr> <th>15:8 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>16 </th> <td>avx10-128</td> <td>128-bit vector support is present </td></tr> <tr> <th>17 </th> <td>avx10-256</td> <td>256-bit vector support is present </td></tr> <tr> <th>18 </th> <td>avx10-512</td> <td>512-bit vector support is present </td></tr> <tr> <th>31:19 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=24h,_ECX=1:_Discrete_AVX10_Features">EAX=24h, ECX=1: Discrete AVX10 Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=25" title="Edit section: EAX=24h, ECX=1: Discrete AVX10 Features">edit</a>]</div> Subleaf 1 is reserved for AVX10 features not bound to a version. None are currently defined. <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=2000'0000h:_Highest_Xeon_Phi_Function_Implemented">EAX=2000'0000h: Highest Xeon Phi Function Implemented</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=26" title="Edit section: EAX=2000'0000h: Highest Xeon Phi Function Implemented">edit</a>]</div> The highest function is returned in EAX. This leaf is only present on <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> processors.<a href="#cite_note-intel_knc_cpuid_ref-159">[112]</a> <div class="mw-heading mw-heading3"><h3 id="EAX=2000'0001h:_Xeon_Phi_Feature_Bits">EAX=2000'0001h: Xeon Phi Feature Bits</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=27" title="Edit section: EAX=2000'0001h: Xeon Phi Feature Bits">edit</a>]</div> This function returns feature flags. <table class="wikitable"> <caption>CPUID EAX=2000'0001h: Xeon Phi feature bits </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th colspan="2">ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th></tr> <tr> <th>3:0 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>3:0 </th></tr> <tr> <th>4 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>k1om</td> <td>K1OM<a href="#cite_note-intel_knc_cpuid_ref-159">[112]</a> </td> <th>4 </th></tr> <tr> <th>31:5 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:5 </th></tr> </tbody></table> <div class="mw-heading mw-heading3"><h3 id="EAX=4000'0000h-4FFFF'FFFh:_Reserved_for_Hypervisors">EAX=4000'0000h-4FFFF'FFFh: Reserved for <a href="/wiki/Hypervisor" title="Hypervisor">Hypervisors</a></h3>[<a href="/w/index.php?title=CPUID&action=edit&section=28" title="Edit section: EAX=4000'0000h-4FFFF'FFFh: Reserved for Hypervisors">edit</a>]</div> When the <code>CPUID</code> instruction is executed under <a href="/wiki/X86_virtualization" title="X86 virtualization">Intel VT-x or AMD-v virtualization</a>, it will be intercepted by the hypervisor, enabling the hypervisor to return <code>CPUID</code> feature flags that differ from those of the underlying hardware. <code>CPUID</code> leaves <code>40000000h</code> to <code>4FFFFFFFh</code> are not implemented in hardware, and are reserved for use by hypervisors to provide hypervisor-specific identification and feature information through this interception mechanism. For leaf <code>40000000h</code>, the hypervisor is expected to return the index of the highest supported hypervisor CPUID leaf in EAX, and a 12-character hypervisor ID string in EBX,ECX,EDX (in that order). For leaf <code>40000001h</code>, the hypervisor may return an interface identification signature in EAX - e.g. hypervisors that wish to advertise that they are <a href="/wiki/Hyper-V" title="Hyper-V">Hyper-V</a> compatible may return <code>0x31237648</code>—<code>"Hv#1"</code> in EAX.<a href="#cite_note-microsoft_tlfs-160">[113]</a><a href="#cite_note-161">[114]</a> The formats of leaves <code>40000001h</code> and up to the highest supported leaf are otherwise hypervisor-specific. Hypervisors that implement these leaves will normally also set bit 31 of ECX for CPUID leaf 1 to indicate their presence. Hypervisors that expose more than one hypervisor interface may provide additional sets of CPUID leaves for the additional interfaces, at a spacing of <code>100h</code> leaves per interface. For example, when <a href="/wiki/QEMU" title="QEMU">QEMU</a> is configured to provide both <a href="/wiki/Hyper-V" title="Hyper-V">Hyper-V</a> and <a href="/wiki/Kernel-based_Virtual_Machine" title="Kernel-based Virtual Machine">KVM</a> interfaces, it will provide Hyper-V information starting from CPUID leaf <code>40000000h</code> and KVM information starting from leaf <code>40000100h</code>.<a href="#cite_note-162">[115]</a><a href="#cite_note-163">[116]</a> <div style="width:100%; height:1em; clear:both;"></div> Some hypervisors that are known to return a hypervisor ID string in leaf <code>40000000h</code> include: <table class="wikitable"> <caption>CPUID EAX=40000x00h: 12-character Hypervisor ID string in EBX,ECX,EDX </caption> <tbody><tr> <th>Hypervisor </th> <th>ID String (ASCII) </th> <th>Notes </th></tr> <tr> <td>Microsoft <a href="/wiki/Hyper-V" title="Hyper-V">Hyper-V</a>, <a href="/wiki/Windows_Virtual_PC" class="mw-redirect" title="Windows Virtual PC">Windows Virtual PC</a> </td> <td><code>"Microsoft Hv"</code><a href="#cite_note-microsoft_tlfs-160">[113]</a> </td> <td> </td></tr> <tr> <td rowspan="2">Linux <a href="/wiki/Kernel-based_Virtual_Machine" title="Kernel-based Virtual Machine">KVM</a> </td> <td><code>"KVMKVMKVM\0\0\0"</code><a href="#cite_note-164">[117]</a> </td> <td>\0 denotes an ASCII NUL character. </td></tr> <tr> <td><code>"Linux KVM Hv"</code><a href="#cite_note-165">[118]</a> </td> <td>Hyper-V emulation<a href="#cite_note-166">[119]</a> </td></tr> <tr> <td><a href="/wiki/Bhyve" title="Bhyve">bhyve</a> </td> <td><code>"BHyVE BHyVE "</code>, <code>"bhyve bhyve "</code> </td> <td>ID string changed from mixed-case to lower-case in 2013.<a href="#cite_note-167">[120]</a> Lower-case string also used in bhyve-derived hypervisors such as xhyve and HyperKit.<a href="#cite_note-168">[121]</a> </td></tr> <tr> <td><a href="/wiki/Xen" title="Xen">Xen</a> </td> <td><code>"XenVMMXenVMM"</code><a href="#cite_note-169">[122]</a> </td> <td>Only when using HVM (hardware virtual machine) mode. </td></tr> <tr> <td><a href="/wiki/QEMU" title="QEMU">QEMU</a> </td> <td><code>"TCGTCGTCGTCG"</code><a href="#cite_note-170">[123]</a> </td> <td>Only when the TCG (Tiny Code Generator) is enabled. </td></tr> <tr> <td><a href="/wiki/Parallels_(company)" title="Parallels (company)">Parallels</a> </td> <td><code>" lrpepyh  vr"</code> </td> <td>(it possibly should be "prl hyperv", but it is encoded as " lrpepyh vr" due to an <a href="/wiki/Endianness" title="Endianness">endianness</a> mismatch)[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] </td></tr> <tr> <td><a href="/wiki/VMware" title="VMware">VMware</a> </td> <td><code>"VMwareVMware"</code><a href="#cite_note-171">[124]</a> </td> <td> </td></tr> <tr> <td>Project ACRN </td> <td><code>"ACRNACRNACRN"</code><a href="#cite_note-172">[125]</a> </td> <td> </td></tr> <tr> <td><a href="/wiki/VirtualBox" title="VirtualBox">VirtualBox</a> </td> <td><code>"VBoxVBoxVBox"</code><a href="#cite_note-173">[126]</a> </td> <td>Only when configured to use the "hyperv" paravirtualization provider. </td></tr> <tr> <td><a href="/wiki/QNX" title="QNX">QNX</a> Hypervisor </td> <td><code>"QXNQSBMV"</code> </td> <td>The QNX hypervisor detection method provided in the official QNX documentation<a href="#cite_note-174">[127]</a> checks only the first 8 characters of the string, as provided in EBX and ECX (including an endianness swap) - EDX is ignored and may take any value. </td></tr> <tr> <td><a href="/wiki/NetBSD#Virtualization" title="NetBSD">NetBSD NVMM</a> </td> <td><code>"___ NVMM ___"</code><a href="#cite_note-175">[128]</a> </td></tr> <tr> <td><a href="/wiki/OpenBSD" title="OpenBSD">OpenBSD</a> VMM </td> <td><code>"OpenBSDVMM58"</code><a href="#cite_note-176">[129]</a> </td> <td> </td></tr> <tr> <td>Jailhouse </td> <td><code>"Jailhouse\0\0\0"</code><a href="#cite_note-177">[130]</a> </td> <td>\0 denotes an ASCII NUL character. </td></tr> <tr> <td>Intel HAXM </td> <td><code>"HAXMHAXMHAXM"</code><a href="#cite_note-178">[131]</a> </td> <td>Project discontinued. </td></tr> <tr> <td>Intel KGT (Trusty) </td> <td><code>"EVMMEVMMEVMM"</code><a href="#cite_note-ikgt-source-179">[132]</a> </td> <td>On "trusty" branch of KGT only, which is used for the <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html">Intel x86 Architecture Distribution of Trusty OS</a> (<a rel="nofollow" class="external text" href="https://web.archive.org/web/20230821024540/https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html">archive</a>) (KGT also returns a signature in <code>CPUID</code> leaf 3: ECX=<code>0x4D4D5645 "EVMM"</code> and EDX=<code>0x43544E49 "INTC"</code>) </td></tr> <tr> <td><a href="/wiki/Unisys" title="Unisys">Unisys</a> s-Par </td> <td><code>"UnisysSpar64"</code><a href="#cite_note-180">[133]</a> </td> <td> </td></tr> <tr> <td><a href="/wiki/Lockheed_Martin" title="Lockheed Martin">Lockheed Martin</a> LMHS </td> <td><code>"SRESRESRESRE"</code><a href="#cite_note-181">[134]</a> </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0000h:_Highest_Extended_Function_Implemented">EAX=8000'0000h: Highest Extended Function Implemented</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=29" title="Edit section: EAX=8000'0000h: Highest Extended Function Implemented">edit</a>]</div> The highest calling parameter is returned in EAX. EBX/ECX/EDX return the manufacturer ID string (same as EAX=0) on AMD but not Intel CPUs. <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0001h:_Extended_Processor_Info_and_Feature_Bits">EAX=8000'0001h: Extended Processor Info and Feature Bits</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=30" title="Edit section: EAX=8000'0001h: Extended Processor Info and Feature Bits">edit</a>]</div> This returns extended feature flags in EDX and ECX. Many of the bits in <code>EDX</code> (bits 0 through 9, 12 through 17, 23, and 24) are duplicates of <code>EDX</code> from the <code>EAX=1</code> leaf - these bits are highlighted in light yellow. (These duplicated bits are present on AMD but not Intel CPUs.) AMD feature flags are as follows:<a href="#cite_note-182">[135]</a><a href="#cite_note-183">[136]</a> <table class="wikitable"> <caption>CPUID EAX=80000001h: Feature bits in EDX and ECX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EDX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34"> </th> <th colspan="2">ECX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short </th> <th>Feature </th> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>fpu</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Onboard <a href="/wiki/X87" title="X87">x87</a> FPU </td> <td>lahf_lm</td> <td><code>LAHF</code>/<code>SAHF</code> in long mode </td> <th>0 </th></tr> <tr> <th>1 </th> <td>vme</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Virtual mode extensions (VIF) </td> <td>cmp_legacy</td> <td><a href="/wiki/Hyperthreading" class="mw-redirect" title="Hyperthreading">Hyperthreading</a> not valid </td> <th>1 </th></tr> <tr> <th>2 </th> <td>de</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Debugging extensions (<a href="/wiki/Control_register#CR4" title="Control register">CR4</a> bit 3) </td> <td>svm</td> <td><a href="/wiki/Secure_Virtual_Machine" class="mw-redirect" title="Secure Virtual Machine">Secure Virtual Machine</a> </td> <th>2 </th></tr> <tr> <th>3 </th> <td>pse</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Page_Size_Extension" title="Page Size Extension">Page Size Extension</a> </td> <td>extapic</td> <td>Extended <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">APIC</a> space </td> <th>3 </th></tr> <tr> <th>4 </th> <td>tsc</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> </td> <td>cr8_legacy</td> <td><a href="/wiki/Control_register#CR8" title="Control register">CR8</a> in 32-bit mode </td> <th>4 </th></tr> <tr> <th>5 </th> <td>msr</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific registers</a> </td> <td>abm/lzcnt</td> <td><a href="/wiki/Advanced_Bit_Manipulation" class="mw-redirect" title="Advanced Bit Manipulation">Advanced bit manipulation</a> <code>(<a href="/wiki/Lzcnt" class="mw-redirect" title="Lzcnt">LZCNT</a></code> and <code><a href="/wiki/Popcnt" class="mw-redirect" title="Popcnt">POPCNT</a></code>) </td> <th>5 </th></tr> <tr> <th>6 </th> <td>pae</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">Physical Address Extension</a> </td> <td>sse4a</td> <td><a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a> </td> <th>6 </th></tr> <tr> <th>7 </th> <td>mce</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Machine_Check_Exception" class="mw-redirect" title="Machine Check Exception">Machine Check Exception</a> </td> <td>misalignsse</td> <td>Misaligned <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> mode </td> <th>7 </th></tr> <tr> <th>8 </th> <td>cx8</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><code>CMPXCHG8B</code> (<a href="/wiki/Compare-and-swap" title="Compare-and-swap">compare-and-swap</a>) instruction </td> <td>3dnowprefetch</td> <td><code>PREFETCH</code> and <code>PREFETCHW</code> instructions </td> <th>8 </th></tr> <tr> <th>9 </th> <td>apic</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Onboard <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">Advanced Programmable Interrupt Controller</a> </td> <td>osvw</td> <td>OS Visible Workaround </td> <th>9 </th></tr> <tr> <th>10 </th> <td>(syscall)<a href="#cite_note-186">[a]</a> </td> <td>(<code>SYSCALL</code>/<code>SYSRET</code>, K6 only) </td> <td>ibs</td> <td><a href="/wiki/Hardware_performance_counter#Instruction_based_sampling" title="Hardware performance counter">Instruction Based Sampling</a> </td> <th>10 </th></tr> <tr> <th>11 </th> <td>syscall<a href="#cite_note-188">[b]</a></td> <td><code>SYSCALL</code> and <code>SYSRET</code> instructions </td> <td>xop</td> <td><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP instruction set</a> </td> <th>11 </th></tr> <tr> <th>12 </th> <td>mtrr</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Memory_Type_Range_Registers" class="mw-redirect" title="Memory Type Range Registers">Memory Type Range Registers</a> </td> <td>skinit</td> <td><code>SKINIT</code>/<code>STGI</code> instructions </td> <th>12 </th></tr> <tr> <th>13 </th> <td>pge</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Page Global Enable bit in <a href="/wiki/Control_register#CR4" title="Control register">CR4</a> </td> <td>wdt</td> <td><a href="/wiki/Watchdog_timer" title="Watchdog timer">Watchdog timer</a> </td> <th>13 </th></tr> <tr> <th>14 </th> <td>mca</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Machine_check_architecture" class="mw-redirect" title="Machine check architecture">Machine check architecture</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>14 </th></tr> <tr> <th>15 </th> <td>cmov</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial">Conditional move and <code><a href="/wiki/FCMOV" title="FCMOV">FCMOV</a></code> instructions </td> <td>lwp</td> <td>Light Weight Profiling<a href="#cite_note-189">[140]</a> </td> <th>15 </th></tr> <tr> <th>16 </th> <td>pat<a href="#cite_note-ext1_edx_16_24-193">[c]</a> </td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/Page_Attribute_Table" class="mw-redirect" title="Page Attribute Table">Page Attribute Table</a> </td> <td>fma4</td> <td><a href="/wiki/FMA_instruction_set#FMA4_instruction_set" title="FMA instruction set">4-operand fused multiply-add instructions</a> </td> <th>16 </th></tr> <tr> <th>17 </th> <td>pse36</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/PSE-36" title="PSE-36">36-bit page size extension</a> </td> <td>tce</td> <td>Translation Cache Extension </td> <th>17 </th></tr> <tr> <th>18 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>18 </th></tr> <tr> <th>19 </th> <td>ecc</td> <td>"<a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon MP</a>" / "<a href="/wiki/Sempron" title="Sempron">Sempron</a>" CPU brand identification<a href="#cite_note-195">[d]</a> </td> <td>nodeid_msr</td> <td>NodeID MSR (<code>C001_100C</code>)<a href="#cite_note-196">[145]</a> </td> <th>19 </th></tr> <tr> <th>20 </th> <td>nx</td> <td><a href="/wiki/NX_bit" title="NX bit">NX bit</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>20 </th></tr> <tr> <th>21 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>tbm</td> <td><a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM" class="mw-redirect" title="Bit Manipulation Instruction Sets">Trailing Bit Manipulation</a> </td> <th>21 </th></tr> <tr> <th>22 </th> <td>mmxext</td> <td><a href="/wiki/3DNow!#3DNow_extensions" title="3DNow!">Extended MMX</a> </td> <td>topoext</td> <td>Topology Extensions </td> <th>22 </th></tr> <tr> <th>23 </th> <td>mmx</td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> instructions </td> <td>perfctr_core</td> <td>Core performance counter extensions </td> <th>23 </th></tr> <tr> <th>24 </th> <td>fxsr<a href="#cite_note-ext1_edx_16_24-193">[c]</a></td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><code>FXSAVE</code>, <code>FXRSTOR</code> instructions, <a href="/wiki/Control_register#CR4" title="Control register">CR4</a> bit 9 </td> <td>perfctr_nb</td> <td><a href="/wiki/Northbridge_(computing)" title="Northbridge (computing)">Northbridge</a> performance counter extensions </td> <th>24 </th></tr> <tr> <th>25 </th> <td>fxsr_opt</td> <td><code>FXSAVE</code>/<code>FXRSTOR</code> optimizations </td> <td>(StreamPerfMon)</td> <td>(Streaming performance monitor architecture)<a href="#cite_note-198">[e]</a> </td> <th>25 </th></tr> <tr> <th>26 </th> <td>pdpe1gb</td> <td><a href="/wiki/Gigabyte" title="Gigabyte">Gigabyte</a> pages </td> <td>dbx</td> <td>Data breakpoint extensions </td> <th>26 </th></tr> <tr> <th>27 </th> <td>rdtscp</td> <td><code>RDTSCP</code> instruction </td> <td>perftsc</td> <td>Performance timestamp counter (PTSC) </td> <th>27 </th></tr> <tr> <th>28 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>pcx_l2i</td> <td>L2I perf counter extensions </td> <th>28 </th></tr> <tr> <th>29 </th> <td>lm</td> <td><a href="/wiki/Long_mode" title="Long mode">Long mode</a> </td> <td>monitorx</td> <td><code>MONITORX</code> and <code>MWAITX</code> instructions </td> <th>29 </th></tr> <tr> <th>30 </th> <td>3dnowext</td> <td><a href="/wiki/3DNow!#3DNow_extensions" title="3DNow!">Extended 3DNow!</a> </td> <td>addr_mask_ext</td> <td>Address mask extension to 32 bits for instruction breakpoints </td> <th>30 </th></tr> <tr> <th>31 </th> <td>3dnow</td> <td><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>31 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-186"><a href="#cite_ref-186">^</a> The use of EDX bit 10 to indicate support for <code>SYSCALL</code>/<code>SYSRET</code> is only valid on <code>AuthenticAMD</code> <a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">Family 5</a> Model 7 CPUs (<a href="/wiki/AMD_K6" title="AMD K6">AMD K6</a>, 250nm "Little Foot") - for all other processors, EDX bit 11 should be used instead.These instructions were first introduced on Model 7<a href="#cite_note-184">[137]</a> - the CPUID bit to indicate their support was moved<a href="#cite_note-185">[138]</a> to EDX bit 11 from Model 8 (<a href="/wiki/AMD_K6-2" title="AMD K6-2">AMD K6-2</a>) onwards. </li> <li id="cite_note-188"><a href="#cite_ref-188">^</a> On Intel CPUs, the CPUID bit for <code>SYSCALL</code>/<code>SYSRET</code> is only set if the <code>CPUID</code> instruction is executed in 64-bit mode.<a href="#cite_note-187">[139]</a> </li> <li id="cite_note-ext1_edx_16_24-193">^ <a href="#cite_ref-ext1_edx_16_24_193-0">a</a> <a href="#cite_ref-ext1_edx_16_24_193-1">b</a> On some processors - Cyrix <a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>,<a href="#cite_note-190">[141]</a> several <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geodes</a> (NatSemi Geode GXm, GXLV, GX1; AMD Geode GX1<a href="#cite_note-191">[142]</a>) and <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Transmeta Crusoe</a><a href="#cite_note-192">[143]</a> - EDX bits 16 and 24 have a different meaning: <ul><li>Bit 16: Floating-point Conditional Move (<code><a href="/wiki/FCMOV" title="FCMOV">FCMOV</a></code>) supported</li> <li>Bit 24: 6x86MX <a href="/wiki/Extended_MMX" title="Extended MMX">Extended MMX</a> instructions supported</li></ul> </li> <li id="cite_note-195"><a href="#cite_ref-195">^</a> EDX bit 19 is used for CPU brand identification on <code>AuthenticAMD</code> <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">Family 6</a> processors only - the bit is, combined with processor signature and <a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speed, used to identify processors as either multiprocessor-capable or carrying the <a href="/wiki/Sempron" title="Sempron">Sempron</a> brand name.<a href="#cite_note-amd_20734_313-194">[144]</a> </li> <li id="cite_note-198"><a href="#cite_ref-198">^</a> ECX bit 25 is listed as StreamPerfMon in revision 3.20 of AMD APM<a href="#cite_note-197">[146]</a> only - it is listed as reserved in later revisions. The bit is set on Excavator and Steamroller CPUs only. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0002h,8000'0003h,8000'0004h:_Processor_Brand_String">EAX=8000'0002h,8000'0003h,8000'0004h: Processor Brand String</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=31" title="Edit section: EAX=8000'0002h,8000'0003h,8000'0004h: Processor Brand String">edit</a>]</div> These return the processor brand string in EAX, EBX, ECX and EDX. <code>CPUID</code> must be issued with each parameter in sequence to get the entire 48-byte ASCII processor brand string.<a href="#cite_note-intel1-199">[147]</a> It is necessary to check whether the feature is present in the CPU by issuing <code>CPUID</code> with <code>EAX = 80000000h</code> first and checking if the returned value is not less than <code>80000004h</code>. The string is specified in Intel/AMD documentation to be <a href="/wiki/Null-terminated_string" title="Null-terminated string">null-terminated</a>, however this is not always the case (e.g. DM&P <a href="/wiki/Vortex86#Vortex86DX3" title="Vortex86">Vortex86DX3</a> and AMD <a href="/wiki/List_of_AMD_Ryzen_processors#Ryzen_6000_series" title="List of AMD Ryzen processors">Ryzen 7 6800HS</a> are known to return non-null-terminated brand strings in leaves <code>80000002h</code>-<code>80000004h</code><a href="#cite_note-200">[148]</a><a href="#cite_note-201">[149]</a>), and software should not rely on it. <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #include <string.h> #include <cpuid.h> int main() { unsigned int regs[12]; char str[sizeof(regs)+1]; __cpuid(0x80000000, regs[0], regs[1], regs[2], regs[3]); if (regs[0] < 0x80000004) return 1; __cpuid(0x80000002, regs[0], regs[1], regs[2], regs[3]); __cpuid(0x80000003, regs[4], regs[5], regs[6], regs[7]); __cpuid(0x80000004, regs[8], regs[9], regs[10], regs[11]); memcpy(str, regs, sizeof(regs)); str[sizeof(regs)] = '\0'; printf("%s\n", str); return 0; } </pre></div> On AMD processors, from <a href="/wiki/List_of_AMD_Athlon_processors#Athlon_(Model_2,_K75_"Pluto/Orion",_180_nm)" title="List of AMD Athlon processors">180nm Athlon</a> onwards (<code>AuthenticAMD</code> Family 6 Model 2 and later), it is possible to modify the processor brand string returned by CPUID leaves <code>80000002h</code>-<code>80000004h</code> by using the <code>WRMSR</code> instruction to write a 48-byte replacement string to MSRs <code>C0010030h</code>-<code>C0010035h</code>.<a href="#cite_note-amd_20734_313-194">[144]</a><a href="#cite_note-202">[150]</a> This can also be done on AMD Geode GX/LX, albeit using MSRs <code>300Ah</code>-<code>300Fh</code>.<a href="#cite_note-203">[151]</a> <div style="width:100%; height:1em; clear:both;"></div> In some cases, determining the CPU vendor requires examining not just the Vendor ID in CPUID leaf 0 and the CPU signature in leaf 1, but also the Processor Brand String in leaves <code>80000002h</code>-<code>80000004h</code>. Known cases include: <ul><li>Montage Jintide CPUs can be distinguished from the Intel Xeon CPU models they're based on by the presence of the substring <code>Montage</code> in the brand string of the Montage CPUs (e.g. Montage Jintide C2460<a href="#cite_note-204">[152]</a> and Intel Xeon Platinum 8160<a href="#cite_note-205">[153]</a> - both of which identify themselves as <code>GenuineIntel</code> Family 6 Model 55h Stepping 4 - can be distinguished in this manner.)</li> <li><code>CentaurHauls</code> Family 6 CPUs may be either VIA or Zhaoxin CPUs - these can be distinguished by the presence of the substring <code>ZHAOXIN</code> in the brand string of the Zhaoxin CPUs (e.g. Zhaoxin KaiXian ZX-C+ C4580<a href="#cite_note-206">[154]</a> and VIA Eden X4 C4250<a href="#cite_note-207">[155]</a> - both of which identify themselves as <code>CentaurHauls</code> Family 6 Model 0Fh Stepping 0Eh - can be distinguished in this manner.)</li></ul> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0005h:_L1_Cache_and_TLB_Identifiers">EAX=8000'0005h: L1 Cache and TLB Identifiers</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=32" title="Edit section: EAX=8000'0005h: L1 Cache and TLB Identifiers">edit</a>]</div> This provides information about the processor's level-1 cache and <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a> characteristics in EAX, EBX, ECX and EDX as follows:<a href="#cite_note-209">[a]</a> <ul><li>EAX: information about L1 hugepage TLBs (TLBs that hold entries corresponding to 2M/4M pages)<a href="#cite_note-211">[b]</a></li> <li>EBX: information about L1 small-page TLBs (TLBs that hold entries corresponding to 4K pages)</li> <li>ECX: information about L1 data cache</li> <li>EDX: information about L1 instruction cache</li></ul> <table class="wikitable"> <caption>CPUID EAX=80000002h: L1 Cache/TLB information in EAX,EBX,ECX,EDX </caption> <tbody><tr> <th>Bits </th> <th>EAX</th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th>ECX</th> <th>EDX </th> <th>Bits </th></tr> <tr> <th>7:0 </th> <td colspan="2">Number of instruction TLB entries<a href="#cite_note-tmta_tlbsize-212">[c]</a> </td> <td colspan="2">Cache line size in bytes </td> <th>7:0 </th></tr> <tr> <th>15:8 </th> <td colspan="2">instruction TLB associativity<a href="#cite_note-ex2_assoc-213">[d]</a> </td> <td colspan="2">Number of cache lines per tag </td> <th>15:8 </th></tr> <tr> <th>23:16 </th> <td colspan="2">Number of data TLB entries<a href="#cite_note-tmta_tlbsize-212">[c]</a> </td> <td colspan="2">Cache associativity<a href="#cite_note-ex2_assoc-213">[d]</a> </td> <th>23:16 </th></tr> <tr> <th>31:24 </th> <td colspan="2">Data TLB associativity<a href="#cite_note-ex2_assoc-213">[d]</a> </td> <td colspan="2">Cache size in kilobytes </td> <th>31:24 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-209"><a href="#cite_ref-209">^</a> On some older Cyrix and Geode CPUs (specifically, <code>CyrixInstead</code>/<code>Geode by NSC</code> Family 5 Model 4 CPUs only), leaf <code>80000005h</code> exists but has a completely different format, similar to that of leaf 2.<a href="#cite_note-208">[156]</a> </li> <li id="cite_note-211"><a href="#cite_ref-211">^</a> On processors that can only handle small-pages in their TLBs, this leaf will return 0 in EAX. (On such processors, which include e.g. AMD K6 and Transmeta Crusoe, hugepage entries in the page-tables are broken up into 4K pages as needed upon entry into the TLB.) On some processors, e.g. VIA <a href="/wiki/Cyrix_III" title="Cyrix III">Cyrix III</a> "Samuel",<a href="#cite_note-210">[157]</a> this leaf returns <code>0x80000005</code> in EAX. This has the same meaning as EAX=0, i.e. no hugepage TLBs. </li> <li id="cite_note-tmta_tlbsize-212">^ <a href="#cite_ref-tmta_tlbsize_212-0">a</a> <a href="#cite_ref-tmta_tlbsize_212-1">b</a> On Transmeta CPUs, the value <code>FFh</code> is used to indicate a 256-entry TLB. </li> <li id="cite_note-ex2_assoc-213">^ <a href="#cite_ref-ex2_assoc_213-0">a</a> <a href="#cite_ref-ex2_assoc_213-1">b</a> <a href="#cite_ref-ex2_assoc_213-2">c</a> For the associativity fields of leaf <code>80000005h</code>, the following values are used: <table class="wikitable sortable"> <tbody><tr> <th>Value</th> <th>Meaning </th></tr> <tr> <td>0</td> <td>(reserved) </td></tr> <tr> <td>1</td> <td>Direct-mapped </td></tr> <tr> <td>2 to <code>FEh</code></td> <td>N-way set-associative (field encodes N) </td></tr> <tr> <td><code>FFh</code></td> <td>Fully-associative </td></tr></tbody></table> </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0006h:_Extended_L2_Cache_Features">EAX=8000'0006h: Extended L2 Cache Features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=33" title="Edit section: EAX=8000'0006h: Extended L2 Cache Features">edit</a>]</div> Returns details of the L2 cache in ECX, including the line size in bytes (Bits 07 - 00), type of associativity (encoded by a 4 bits field; Bits 15 - 12) and the cache size in KB (Bits 31 - 16). <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; unsigned int lsize, assoc, cache; __cpuid(0x80000006, eax, ebx, ecx, edx); lsize = ecx & 0xff; assoc = (ecx >> 12) & 0x07; cache = (ecx >> 16) & 0xffff; printf("Line size: %d B, Assoc. type: %d, Cache size: %d KB.\n", lsize, assoc, cache); return 0; } </pre></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0007h:_Processor_Power_Management_Information_and_RAS_Capabilities">EAX=8000'0007h: Processor Power Management Information and RAS Capabilities</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=34" title="Edit section: EAX=8000'0007h: Processor Power Management Information and RAS Capabilities">edit</a>]</div> This function provides information about power management, power reporting and RAS (<a href="/wiki/Reliability,_availability_and_serviceability" title="Reliability, availability and serviceability">Reliability, availability and serviceability</a>) capabilities of the CPU. <table class="wikitable"> <caption>CPUID EAX=80000007h: RAS features in EBX and power management features in EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="19"> </th> <th colspan="2">EDX </th> <th rowspan="2">Bit </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>MCAOverflowRecov</td> <td>MCA (Machine Check Architecture) overflow recovery support </td> <td>TS</td> <td>Temperature Sensor </td> <th>0 </th></tr> <tr> <th>1 </th> <td>SUCCOR</td> <td>Software uncorrectable error containment and recovery capability </td> <td>FID</td> <td>Frequency ID Control </td> <th>1 </th></tr> <tr> <th>2 </th> <td>HWA</td> <td>Hardware assert support (MSRs <code>C001_10C0</code> to <code>C001_10DF</code> </td> <td>VID</td> <td>Voltage ID Control </td> <th>2 </th></tr> <tr> <th>3 </th> <td>ScalableMca</td> <td>Scalable MCA supported </td> <td>TTP</td> <td>THERMTRIP </td> <th>3 </th></tr> <tr> <th>4 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>TM</td> <td>Hardware thermal control (HTC) supported </td> <th>4 </th></tr> <tr> <th>5 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>STC</td> <td>Software thermal control (STC) supported<a href="#cite_note-214">[158]</a> </td> <th>5 </th></tr> <tr> <th>6 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>100MHzSteps</td> <td>100 MHz multiplier control </td> <th>6 </th></tr> <tr> <th>7 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>HwPstate</td> <td>Hardware P-state control (MSRs <code>C001_0061</code> to <code>C001_0063</code>) </td> <th>7 </th></tr> <tr> <th>8 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>TscInvariant</td> <td>Invariant TSC - TSC (<a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a>) rate is guaranteed to be invariant across all P-states, C-states and sop grant transitions. </td> <th>8 </th></tr> <tr> <th>9 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>CPB</td> <td>Core Performance Boost </td> <th>9 </th></tr> <tr> <th>10 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>EffFreqRO</td> <td>Read-only effective frequency interface (MSRs <code>C000_00E7</code> and <code>C000_00E8</code>) </td> <th>10 </th></tr> <tr> <th>11 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>ProcFeedbackInterface</td> <td>Processor Feedback Interface supported </td> <th>11 </th></tr> <tr> <th>12 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>ProcPowerReporting</td> <td>Processor power reporting interface supported </td> <th>12 </th></tr> <tr> <th>13 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>ConnectedStandby</td> <td>Connected Standby<a href="#cite_note-amd_56713_p99-215">[159]</a> </td> <th>13 </th></tr> <tr> <th>14 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>RAPL</td> <td>Running Average Power Limit<a href="#cite_note-amd_56713_p99-215">[159]</a> </td> <th>14 </th></tr> <tr> <th>15 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td>FastCPPC</td> <td>Fast CPPC (Collaborative Processor Performance Control) supported<a href="#cite_note-amd_56713_p99-215">[159]</a> </td> <th>15 </th></tr> <tr> <th> 31:16   </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th> 31:16   </th></tr></tbody></table> <table class="wikitable"> <caption>CPUID EAX=80000007h: Processor Feedback info in EAX and power monitoring interface info in ECX </caption> <tbody><tr> <th rowspan="2">Bits </th> <th colspan="2">EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5"> </th> <th colspan="2">ECX </th> <th rowspan="2">Bits </th></tr> <tr> <th>Short</th> <th>Feature </th> <th>Short</th> <th>Feature </th></tr> <tr> <th>7:0 </th> <td>NumberOfMonitors</td> <td>Number of Processor Feedback MSR pairs available, starting from MSR <code>C001_0080</code> onwards<a href="#cite_note-216">[160]</a> </td> <td rowspan="3">CpuPwrSampleTimeRatio </td> <td rowspan="3">Ratio of compute unit power accumulator sample period to TSC counter period. </td> <th>7:0 </th></tr> <tr> <th>15:8 </th> <td>Version</td> <td>Processor Feedback Capabilities version </td> <th>15:8 </th></tr> <tr> <th>31:16 </th> <td>MaxWrapTime</td> <td>Maximum time between reads (in milliseconds) that software should use to avoid two wraps. </td> <th>31:16 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0008h:_Virtual_and_Physical_Address_Sizes">EAX=8000'0008h: Virtual and Physical Address Sizes</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=35" title="Edit section: EAX=8000'0008h: Virtual and Physical Address Sizes">edit</a>]</div> <table class="wikitable"> <caption>CPUID EAX=80000008h: Feature bits in EBX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EBX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>clzero</td> <td><code>CLZERO</code> instruction </td></tr> <tr> <th>1 </th> <td>retired_instr</td> <td>Retired instruction count MSR (<code>C000_00E9h</code>) supported </td></tr> <tr> <th>2 </th> <td>xrstor_fp_err</td> <td><code>XRSTOR</code> restores FP errors </td></tr> <tr> <th>3 </th> <td>invlpgb</td> <td><code>INVLPGB</code> and <code>TLBSYNC</code> instructions </td></tr> <tr> <th>4 </th> <td>rdpru</td> <td><code>RDPRU</code> instruction </td></tr> <tr> <th>5 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>6 </th> <td>mbe</td> <td>Memory Bandwidth Enforcement </td></tr> <tr> <th>7 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>8 </th> <td>mcommit</td> <td><code>MCOMMIT</code> instruction </td></tr> <tr> <th>9 </th> <td>wbnoinvd</td> <td><code>WBNOINVD</code> instruction </td></tr> <tr> <th>10 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>11 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>12 </th> <td>IBPB</td> <td>Indirect Branch Prediction Barrier (performed by writing 1 to bit 0 of <code>PRED_CMD</code> (MSR <code>049h</code>)) </td></tr> <tr> <th>13 </th> <td>wbinvd_int</td> <td><code>WBINVD</code> and <code>WBNOINVD</code> are interruptible </td></tr> <tr> <th>14 </th> <td>IBRS</td> <td>Indirect Branch Restricted Speculation </td></tr> <tr> <th>15 </th> <td>STIBP</td> <td>Single Thread Indirect Branch Prediction mode </td></tr> <tr> <th>16 </th> <td>IbrsAlwaysOn</td> <td>IBRS mode has enhanced performance and should be left always on </td></tr> <tr> <th>17 </th> <td>StibpAlwaysOn</td> <td>STIBP mode has enhanced performance and should be left always on </td></tr> <tr> <th>18 </th> <td>ibrs_preferred</td> <td>IBRS preferred over software </td></tr> <tr> <th>19 </th> <td>ibrs_same_mode_protection</td> <td>IBRS provides Same Mode Protection </td></tr> <tr> <th>20 </th> <td>no_efer_lmsle</td> <td><code>EFER.LMSLE</code> is unsupported<a href="#cite_note-218">[a]</a> </td></tr> <tr> <th>21 </th> <td>invlpgb_nested</td> <td><code>INVLPGB</code> support for nested pages </td></tr> <tr> <th>22 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>23 </th> <td>ppin</td> <td>Protected Processor Inventory Number - <code>PPIN_CTL</code> (<code>C001_02F0</code>) and <code>PPIN</code> (<code>C001_02F1</code>) MSRs are present<a href="#cite_note-amd_56713_p99-215">[159]</a> </td></tr> <tr> <th>24 </th> <td>ssbd</td> <td>Speculative Store Bypass Disable </td></tr> <tr> <th>25 </th> <td>ssbd_legacy</td> <td>Speculative Store Bypass Disable Legacy </td></tr> <tr> <th>26 </th> <td>ssbd_no</td> <td>Speculative Store Bypass Disable Not Required </td></tr> <tr> <th>27 </th> <td>cppc</td> <td>Collaborative Processor Performance Control </td></tr> <tr> <th>28 </th> <td>psfd</td> <td>Predictive Store Forward Disable </td></tr> <tr> <th>29 </th> <td>btc_no</td> <td>Branch Type Confusion: Processor not affected </td></tr> <tr> <th>30 </th> <td>IBPB_RET</td> <td>IBPB (see bit 12) also clears return address predictor </td></tr> <tr> <th>31 </th> <td>branch_sampling</td> <td>Branch Sampling Support<a href="#cite_note-219">[162]</a> </td></tr></tbody></table> <table class="wikitable"> <caption>CPUID EAX=80000008h: Size and range fields in EAX, ECX, EDX </caption> <tbody><tr> <th>Bits </th> <th>EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7"> </th> <th>ECX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7"> </th> <th>EDX </th> <th>Bits </th></tr> <tr> <th style="padding-top:1em; padding-bottom:1em">7:0 </th> <td>Number of Physical Address Bits </td> <td>Number of Physical Threads in processor (minus 1) </td> <td rowspan="3" style="max-width:18em">Maximum page count for <code>INVLPGB</code> instruction </td> <th style="padding-top:1em; padding-bottom:1em">7:0 </th></tr> <tr> <th>11:8 </th> <td rowspan="2">Number of Linear Address Bits </td> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>11:8 </th></tr> <tr> <th>15:12 </th> <td>APIC ID Size </td> <th>15:12 </th></tr> <tr> <th>17:16 </th> <td rowspan="2">Guest Physical Address Size<a href="#cite_note-220">[b]</a> </td> <td>Performance Timestamp Counter size </td> <td rowspan="3" style="max-width:18em">Maximum ECX value recognized by <code>RDPRU</code> instruction </td> <th>17:16 </th></tr> <tr> <th>23:18 </th> <td rowspan="2" style="text-align:center; background:lightgrey;">(reserved) </td> <th>23:18 </th></tr> <tr> <th style="padding-top:1em; padding-bottom:1em">31:24 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th style="padding-top:1em; padding-bottom:1em">31:24 </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-218"><a href="#cite_ref-218">^</a> The LMSLE (Long Mode Segment Limit Enable) feature does not have its own CPUID flag and is detected by checking CPU family and model. It was introduced in <code>AuthenticAMD</code> Family 0Fh Model 14h<a href="#cite_note-217">[161]</a> (90nm Athlon64/Opteron) CPUs and is present in all later AMD CPUs - except the ones with the 'no_efer_lmsle' flag set. </li> <li id="cite_note-220"><a href="#cite_ref-220">^</a> A value of 0 indicates that the "Guest Physical Address Size" is the same as the "Number Of Physical Address Bits", specified in EAX[7:0]. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'000Ah:_SVM_features">EAX=8000'000Ah: SVM features</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=36" title="Edit section: EAX=8000'000Ah: SVM features">edit</a>]</div> This leaf returns information about AMD SVM (<a href="/wiki/Secure_Virtual_Machine" class="mw-redirect" title="Secure Virtual Machine">Secure Virtual Machine</a>) features in EAX, EBX and EDX. <table class="wikitable"> <caption>CPUID EAX=8000000Ah: SVM information in EAX, EBX and ECX </caption> <tbody><tr> <th>Bits </th> <th>EAX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th>EBX </th> <th scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4"> </th> <th>ECX </th> <th>Bits </th></tr> <tr> <th>7:0 </th> <td>SVM Revision Number </td> <td rowspan="3">Number of available ASIDs (address space identifiers) </td> <td rowspan="3" style="text-align:center; background:lightgrey;">(reserved) </td> <th>7:0 </th></tr> <tr> <th>8 </th> <td style="text-align:center; background:lightgrey;">(hypervisor)<a href="#cite_note-224">[a]</a> </td> <th>8 </th></tr> <tr> <th>31:9 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:9 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <table class="wikitable"> <caption>CPUID EAX=8000000Ah: SVM feature flags in EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EDX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>NP</td> <td>Rapid Virtualization Indexing (<a href="/wiki/Second_Level_Address_Translation" title="Second Level Address Translation">Nested Paging</a>) </td></tr> <tr> <th>1 </th> <td>LbrVirt</td> <td>LBR (Last Branch Records) virtualization </td></tr> <tr> <th>2 </th> <td>SVML</td> <td>SVM-Lock </td></tr> <tr> <th>3 </th> <td>NRIPS</td> <td>nRIP (next sequential instruction pointer) save on #VMEXIT supported </td></tr> <tr> <th>4 </th> <td>TscRateMsr</td> <td>MSR-based <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">TSC</a> rate control (MSR <code>C000_0104h</code>) </td></tr> <tr> <th>5 </th> <td>VmcbClean</td> <td>VMCB (Virtual Machine Control Block) clean bits supported </td></tr> <tr> <th>6 </th> <td>FlushByAsid</td> <td><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a> flush events (e.g. <a href="/wiki/Control_register#CR3" title="Control register">CR3</a> writes, <a href="/wiki/Control_Register#CR4" class="mw-redirect" title="Control Register">CR4.PGE</a> toggles) only flush the TLB entries of the current ASID (address space ID) </td></tr> <tr> <th>7 </th> <td>DecodeAssist</td> <td>Decode assists supported </td></tr> <tr> <th>8 </th> <td>PmcVirt</td> <td>PMC (Performance Monitoring Counters) virtualization </td></tr> <tr> <th>9 </th> <td style="background:lightgrey;">(SseIsa10Compat)<a href="#cite_note-228">[b]</a> </td> <td style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>10 </th> <td>PauseFilter</td> <td><code>PAUSE</code> intercept filter supported </td></tr> <tr> <th>11 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>12 </th> <td>PauseFilterThreshold</td> <td><code>PAUSE</code> filter cycle count threshold supported </td></tr> <tr> <th>13 </th> <td>AVIC</td> <td>AMD Advanced Virtualized Interrupt Controller supported </td></tr> <tr> <th>14 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>15 </th> <td>VMSAVEvirt</td> <td><code>VMSAVE</code> and <code>VMLOAD</code> virtualization </td></tr> <tr> <th>16 </th> <td>VGIF</td> <td>Global Interrupt Flag (GIF) virtualization </td></tr> <tr> <th>17 </th> <td>GMET</td> <td>Guest Mode Execution Trap </td></tr> <tr> <th>18 </th> <td>x2AVIC</td> <td>x2APIC mode supported for AVIC </td></tr> <tr> <th>19 </th> <td>SSSCheck</td> <td>SVM Supervisor <a href="/wiki/Shadow_stack" title="Shadow stack">shadow stack</a> restrictions </td></tr> <tr> <th>20 </th> <td>SpecCtrl</td> <td><code>SPEC_CTRL</code> (MSR <code>2E0h</code>) virtualization </td></tr> <tr> <th>21 </th> <td>ROGPT</td> <td>Read-Only Guest Page Table supported </td></tr> <tr> <th>22 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>23 </th> <td>HOST_MCE_OVERRIDE</td> <td>Guest mode <a href="/wiki/Machine-check_exception" title="Machine-check exception">Machine-check exceptions</a> when host <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.MCE</a>=1</code> and guest <code>CR4.MCE=0</code> cause intercepts instead of shutdowns </td></tr> <tr> <th>24 </th> <td>TlbiCtl</td> <td><code>INVLPGB</code>/<code>TLBSYNC</code> hypervisor enable in VMCB and <code>TLBSYNC</code> intercept support </td></tr> <tr> <th>25 </th> <td>VNMI</td> <td>NMI (<a href="/wiki/Non-Maskable_interrupt" class="mw-redirect" title="Non-Maskable interrupt">Non-Maskable interrupt</a>) virtualization </td></tr> <tr> <th>26 </th> <td>IbsVirt</td> <td>IBS (Instruction-Based Sampling) virtualization </td></tr> <tr> <th>27 </th> <td>ExtLvtOffsetFaultChg</td> <td>Read/Write fault behavior for extended LVT offsets (APIC addresses <code>0x500-0x530</code>) changed to Read Allowed, Write #VMEXIT<a href="#cite_note-amd_56713-229">[169]</a> </td></tr> <tr> <th>28 </th> <td>VmcbAddrChkChg</td> <td>VMCB address check change<a href="#cite_note-amd_56713-229">[169]</a> </td></tr> <tr> <th>29 </th> <td>BusLockThreshold</td> <td>Bus Lock Threshold </td></tr> <tr> <th>30 </th> <td>IdleHltIntercept</td> <td>Idle HLT (<code>HLT</code> instruction executed while no virtual interrupt is pending) intercept </td></tr> <tr> <th>31 </th> <td>EnhancedShutdownIntercept</td> <td>Support for EXITINFO1 on shutdown intercept, and nested shutdown intercepts will result in a non-interceptible shutdown.<a href="#cite_note-amd_zen5_ppr-230">[170]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-224"><a href="#cite_ref-224">^</a> Early revisions of AMD's "Pacifica" documentation listed EAX bit 8 as an always-zero bit reserved for hypervisor use.<a href="#cite_note-221">[163]</a>Later AMD documentation, such as #25481 "CPUID specification" rev 2.18<a href="#cite_note-222">[164]</a> and later, only lists the bit as reserved.In rev 2.30<a href="#cite_note-223">[165]</a> and later, a different bit is listed as reserved for hypervisor use: CPUID.(EAX=1):ECX[bit 31]. </li> <li id="cite_note-228"><a href="#cite_ref-228">^</a> EDX bit 9 is briefly listed in some older revisions of AMD's document #25481 "CPUID Specification", and is set only in some AMD <a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat</a> CPUs.<a href="#cite_note-225">[166]</a>Rev 2.28 of #25481 lists the bit as "Ssse3Sse5Dis"<a href="#cite_note-226">[167]</a> - in rev 2.34, it is listed as having been removed from the spec at rev 2.32 under the name "SseIsa10Compat".<a href="#cite_note-227">[168]</a> </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'001Fh:_Encrypted_Memory_Capabilities">EAX=8000'001Fh: Encrypted Memory Capabilities</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=37" title="Edit section: EAX=8000'001Fh: Encrypted Memory Capabilities">edit</a>]</div> <table class="wikitable"> <caption>CPUID EAX=8000001Fh: Encrypted Memory feature bits in EAX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>0 </th> <td>SME</td> <td>Secure Memory Encryption </td></tr> <tr> <th>1 </th> <td>SEV</td> <td>Secure Encrypted Virtualization </td></tr> <tr> <th>2 </th> <td>PageFlushMSR</td> <td>Page flush MSR (<code>C001_011Eh</code>) supported </td></tr> <tr> <th>3 </th> <td>SEV-ES</td> <td>SEV Encrypted State </td></tr> <tr> <th>4 </th> <td>SEV-SNP</td> <td>SEV Secure Nested Paging </td></tr> <tr> <th>5 </th> <td>VMPL</td> <td>VM Privilege Levels </td></tr> <tr> <th>6 </th> <td>RMPQUERY</td> <td><code>RMPQUERY</code> instruction supported </td></tr> <tr> <th>7 </th> <td>VmplSSS</td> <td>VMPL Supervisor <a href="/wiki/Shadow_stack" title="Shadow stack">shadow stack</a> supported </td></tr> <tr> <th>8 </th> <td>SecureTSC</td> <td>Secure <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">TSC</a> supported </td></tr> <tr> <th>9 </th> <td>TscAuxVirtualization</td> <td>Virtualization of <code>TSC_AUX</code> MSR (<code>C000_0103</code>) supported </td></tr> <tr> <th>10 </th> <td>HwEnfCacheCoh</td> <td>Hardware cache coherency across encryption domains enforced </td></tr> <tr> <th>11 </th> <td>64BitHost</td> <td>SEV Guest execution only allowed from 64-bit host </td></tr> <tr> <th>12 </th> <td>RestrictedInjection</td> <td>SEV-ES guests can refuse all event-injections except #HV (Hypervisor Injection Exception) </td></tr> <tr> <th>13 </th> <td>AlternateInjection</td> <td>SEV-ES guests can use an encrypted VMCB field for event-injection </td></tr> <tr> <th>14 </th> <td>DebugVirt</td> <td>Full debug state virtualization supported for SEV-ES and SEV-SNP guests </td></tr> <tr> <th>15 </th> <td>PreventHostIBS</td> <td>Prevent host IBS for a SEV-ES guest </td></tr> <tr> <th>16 </th> <td>VTE</td> <td>Virtual Transparent Encryption for SEV </td></tr> <tr> <th>17 </th> <td>VmgexitParameter</td> <td><code>VMGEXIT</code> parameter is supported (using the RAX register) </td></tr> <tr> <th>18 </th> <td>VirtualTomMsr</td> <td>Virtual TOM (top-of-memory) MSR (<code>C001_0135</code>) supported </td></tr> <tr> <th>19 </th> <td>IbsVirtGuestCtl</td> <td>IBS virtualization is supported for SEV-ES and SEV-SNP guests </td></tr> <tr> <th>20 </th> <td>PmcVirtGuestCtl</td> <td>PMC virtualization is supported for SEV-ES and SEV-SNP guests </td></tr> <tr> <th>21 </th> <td>RMPREAD</td> <td><code>RMPREAD</code> instruction supported </td></tr> <tr> <th>22 </th> <td>GuestInterceptControl</td> <td>Guest Intercept control supported for SEV-ES guests </td></tr> <tr> <th>23 </th> <td>SegmentedRmp</td> <td>Segmented RMP (Reverse-Map Table) supported </td></tr> <tr> <th>24 </th> <td>VmsaRegProt</td> <td>VMSA (VM Save Area) register protection supported </td></tr> <tr> <th>25 </th> <td>SmtProtection</td> <td><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a> Protection supported </td></tr> <tr> <th>26 </th> <td>SecureAvic</td> <td>Secure AVIC supported </td></tr> <tr> <th>27 </th> <td>AllowedSEVfeatures</td> <td>ALLOWED_SEV_FEATURES_MASK field in VMCB (offset <code>138h</code>) supported </td></tr> <tr> <th>28 </th> <td>SVSMCommPageMSR</td> <td>SVSM (Secure VM Service Module<a href="#cite_note-231">[171]</a>) communication page MSR (<code>C001_F000h</code>) supported </td></tr> <tr> <th>29 </th> <td>NestedVirtSnpMsr</td> <td><code>VIRT_RMPUPDATE</code> (<code>C001_F001h</code>) and <code>VIRT_PSMASH</code> (<code>C001_F002h</code>) MSRs supported </td></tr> <tr> <th>30 </th> <td>HvInUseWrAllowed</td> <td>Writes to Hypervisor-owned paged allowed when marked in-use </td></tr> <tr> <th>31 </th> <td>IbpbOnEntry</td> <td>IBPB on entry to virtual machine supported </td></tr></tbody></table> <table class="wikitable"> <caption>CPUID EAX=8000001Fh: Encrypted Memory feature information in EBX, ECX and EDX </caption> <tbody><tr> <th>Bits </th> <th>EBX </th> <th>ECX </th> <th>EDX </th> <th>Bits </th></tr> <tr> <th>5:0 </th> <td>C-bit (encryption enable bit) location in page table entry </td> <td rowspan="4" style="max-width:18em">Maximum ASID value that can be used for a SEV-enabled guest (maximum number of encrypted guests that can be supported simultaneously) </td> <td rowspan="4" style="max-width:18em">Minimum ASID value for a guest that is SEV-enabled but not SEV-ES-enabled </td> <th>5:0 </th></tr> <tr> <th>11:6 </th> <td>Physical address width reduction when memory encryption is enabled </td> <th>11:6 </th></tr> <tr> <th>15:12 </th> <td>Number of VMPLs (VM Privilege Levels) supported </td> <th>15:12 </th></tr> <tr> <th>31:16 </th> <td style="text-align:center; background:lightgrey;">(reserved) </td> <th>31:16 </th></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8000'0021h:_Extended_Feature_Identification">EAX=8000'0021h: Extended Feature Identification</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=38" title="Edit section: EAX=8000'0021h: Extended Feature Identification">edit</a>]</div> <table class="wikitable"> <caption>CPUID EAX=80000021h: Extended feature bits in EAX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EAX </th></tr> <tr> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>NoNestedDataBp</td> <td>Processor ignores nested data breakpoints </td></tr> <tr> <th>1 </th> <td>FsGsKernelGsBaseNonSerializing</td> <td><code>WRMSR</code> to the <code>FS_BASE</code>, <code>GS_BASE</code> and <code>KernelGSBase</code> MSRs is non-serializing<a href="#cite_note-amd_56713_p116-232">[172]</a> </td></tr> <tr> <th>2 </th> <td>LFenceAlwaysSerializing</td> <td><code>LFENCE</code> is always dispatch serializing </td></tr> <tr> <th>3 </th> <td>SmmPgCfgLock</td> <td>SMM paging configuration lock supported </td></tr> <tr> <th>4 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>5 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>6 </th> <td>NullSelectClearsBase</td> <td>Null segment selector loads also clear the destination segment register base and limit </td></tr> <tr> <th>7 </th> <td>UpperAddressIgnore</td> <td>Upper Address Ignore is supported </td></tr> <tr> <th>8 </th> <td>AutomaticIBRS</td> <td>Automatic IBRS </td></tr> <tr> <th>9 </th> <td>NoSmmCtlMSR</td> <td><code>SMM_CTL</code> MSR (<code>C0010116h</code>) is not supported </td></tr> <tr> <th>10 </th> <td>FSRS</td> <td>Fast short <code>REP STOSB</code> supported </td></tr> <tr> <th>11 </th> <td>FSRC</td> <td>Fast short <code>REPE CMPSB</code> supported </td></tr> <tr> <th>12 </th> <td>PMC2PreciseRetire</td> <td>PreciseRetire performance counter control bit (MSR <code>C0010002h</code> bit 43) supported<a href="#cite_note-amd_zen5_ppr-230">[170]</a> </td></tr> <tr> <th>13 </th> <td>PrefetchCtlMsr</td> <td>PrefetchControl MSR (<code>C0000108h</code>) is supported </td></tr> <tr> <th>14 </th> <td>L2TlbSIzeX32</td> <td>If set, L2 TLB sizes (leaf <code>80000006h</code>) are encoded as multiples of 32 </td></tr> <tr> <th>15 </th> <td>AMD_ERMSB</td> <td>Processor supports AMD implementation of Enhanced <code>REP MOVSB</code> and <code>REP STOSB</code> </td></tr> <tr> <th>16 </th> <td>OPCODE_0F017_RECLAIM</td> <td>Reserves opcode <code>0F 01 /7</code> for AMD use, returning #UD.<a href="#cite_note-amd_zen5_ppr-230">[170]</a> </td></tr> <tr> <th>17 </th> <td>CpuidUserDis</td> <td><code>CPUID</code> disable for non-privileged software (#GP) </td></tr> <tr> <th>18 </th> <td>EPSF</td> <td>Enhanced Predictive Store Forwarding supported<a href="#cite_note-amd_56713_p116-232">[172]</a> </td></tr> <tr> <th>19 </th> <td>FAST_REP_SCASB</td> <td>Fast Short <code>REP SCASB</code> supported </td></tr> <tr> <th>20 </th> <td>PREFETCHI</td> <td>Instruction Cache prefetch instructions supported </td></tr> <tr> <th>21 </th> <td>FP512_DOWNGRADE</td> <td>Downgrade of 512-bit datapath to 256-bit supported.<a href="#cite_note-234">[a]</a> </td></tr> <tr> <th>22 </th> <td>WL_CLASS_SUPPORT</td> <td>Support for workload-based heuristic feedback to OS for scheduling decisions </td></tr> <tr> <th>23 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>24 </th> <td>ERAPS</td> <td>Enhanced Return Address Predictor Security (see also EBX[23:16] "RapSize") </td></tr> <tr> <th>25 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>26 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>27 </th> <td>SBPB</td> <td>Selective Branch Predictor Barrier supported<a href="#cite_note-amd_srso-235">[174]</a> </td></tr> <tr> <th>28 </th> <td>IBPB_BRTYPE</td> <td>IBPB flushes all branch type predictions<a href="#cite_note-amd_srso-235">[174]</a> </td></tr> <tr> <th>29 </th> <td>SRSO_NO</td> <td>CPU is not subject to SRSO (Speculative Return Stack Overflow) vulnerability<a href="#cite_note-amd_srso-235">[174]</a> </td></tr> <tr> <th>30 </th> <td>SRSO_USER_KERNEL_NO</td> <td>CPU is not subject to SRSO vulnerability across user/kernel boundary<a href="#cite_note-amd_srso-235">[174]</a> </td></tr> <tr> <th>31 </th> <td>SRSO_MSR_FIX</td> <td>SRSO can be mitigated by setting bit 4 of BP_CFG (<code>MSR C001_102E</code>)<a href="#cite_note-amd_srso-235">[174]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-234"><a href="#cite_ref-234">^</a> If the downgrade from 512-bit to 256-bit datapath is enabled, then AVX-512 instructions that work on 512-bit data items will be split into two 256-bit parts that will be issued over two consecutive cycles. This datapath downgrade can help improve power efficiency for some workloads.<a href="#cite_note-233">[173]</a> </li> </ol></div></div> <table class="wikitable"> <caption>CPUID EAX=80000021h: Extended feature information in EBX </caption> <tbody><tr> <th rowspan="2">Bit</th> <th colspan="2">EBX </th></tr> <tr> <th>Short</th> <th>Feature </th></tr> <tr> <th>15:0 </th> <td>MicrocodePatchSize</td> <td>The size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes </td></tr> <tr> <th>23:16 </th> <td>RapSize</td> <td>Return Address Predictor Size. RapSize * 8 is the minimum number of <code>CALL</code> instructions without matching <code>RET</code> instructions that are needed to flush the Return Address Predictor. </td></tr> <tr> <th>31:24 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading3"><h3 id="EAX=8FFF'FFFFh:_AMD_Easter_Egg">EAX=8FFF'FFFFh: AMD Easter Egg</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=39" title="Edit section: EAX=8FFF'FFFFh: AMD Easter Egg">edit</a>]</div> Several AMD CPU models will, for CPUID with <code>EAX=8FFFFFFFh</code>, return an Easter Egg string in EAX, EBX, ECX and EDX.<a href="#cite_note-236">[175]</a><a href="#cite_note-237">[176]</a> Known Easter Egg strings include: <table class="wikitable"> <tbody><tr> <th>Processor</th> <th>String </th></tr> <tr> <td><a href="/wiki/AMD_K6" title="AMD K6">AMD K6</a></td> <td><code><a href="/wiki/NexGen" title="NexGen">NexGen</a>‍erationAMD</code> </td></tr> <tr> <td><a href="/wiki/AMD_K8" title="AMD K8">AMD K8</a></td> <td><code>IT'S <a href="/wiki/U_Can%27t_Touch_This" title="U Can't Touch This">HAMMER TIME</a></code> </td></tr> <tr> <td><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">AMD Jaguar</a><a href="#cite_note-238">[177]</a></td> <td><code><a href="/wiki/Hello_Kitty" title="Hello Kitty">HELLO KITTY</a>! ^-^</code> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="EAX=C000'0000h:_Highest_Centaur_Extended_Function">EAX=C000'0000h: Highest <a href="/wiki/Centaur_Technology" title="Centaur Technology">Centaur</a> Extended Function</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=40" title="Edit section: EAX=C000'0000h: Highest Centaur Extended Function">edit</a>]</div> Returns index of highest Centaur leaf in EAX. If the returned value in EAX is less than <code>C0000001h</code>, then Centaur extended leaves are not supported. Present in CPUs from <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA</a> and <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a>. On IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> CPUs (<code>CentaurHauls</code> Family 5), the extended leaves <code>C0000001h-C0000005h</code> do not encode any Centaur-specific functionality but are instead aliases of leaves <code>80000001h-80000005h</code>.<a href="#cite_note-239">[178]</a> <div class="mw-heading mw-heading3"><h3 id="EAX=C000'0001h:_Centaur_Feature_Information">EAX=C000'0001h: Centaur Feature Information</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=41" title="Edit section: EAX=C000'0001h: Centaur Feature Information">edit</a>]</div> This leaf returns Centaur feature information (mainly <a href="/wiki/VIA_PadLock" title="VIA PadLock">VIA PadLock</a>) in EDX.<a href="#cite_note-240">[179]</a><a href="#cite_note-241">[180]</a> (EAX, EBX and ECX are reserved.) <table class="wikitable"> <caption>CPUID EAX=C0000001h: Centaur feature bits in EDX </caption> <tbody><tr> <th rowspan="2">Bit </th> <th colspan="2">EDX </th></tr> <tr> <th>Short </th> <th>Feature </th></tr> <tr> <th>0 </th> <td>sm2<a href="#cite_note-nehemiah_special-243">[a]</a> </td> <td><a href="/wiki/SM9_(cryptography_standard)" title="SM9 (cryptography standard)">SM2</a> present </td></tr> <tr> <th>1 </th> <td>sm2_en<a href="#cite_note-nehemiah_special-243">[a]</a></td> <td>SM2 enabled </td></tr> <tr> <th>2 </th> <td>rng</td> <td>PadLock <a href="/wiki/Random_number_generation" title="Random number generation">RNG</a> present: <code>XSTORE</code> and <code>REP XSTORE</code> instructions </td></tr> <tr> <th>3 </th> <td>rng_en</td> <td>RNG enabled </td></tr> <tr> <th>4 </th> <td>ccs<a href="#cite_note-nehemiah_special-243">[a]</a></td> <td>PadLock <a href="/wiki/SM3_(hash_function)" title="SM3 (hash function)">SM3</a>/<a href="/wiki/SM4_(cipher)" title="SM4 (cipher)">SM4</a> instructions present: <code>CCS_HASH</code> and <code>CCS_ENCRYPT</code> </td></tr> <tr> <th>5 </th> <td>ccs_en<a href="#cite_note-nehemiah_special-243">[a]</a></td> <td>SM3/SM4 instructions enabled </td></tr> <tr> <th>6 </th> <td>xcrypt</td> <td>PadLock Advanced Cryptographic Engine (ACE, using <a href="/wiki/Advanced_Encryption_Standard" title="Advanced Encryption Standard">AES</a> cipher) present: <code>REP XCRYPT(ECB,CBC,CFB,OFB)</code> instructions </td></tr> <tr> <th>7 </th> <td>xcrypt_en</td> <td>ACE enabled </td></tr> <tr> <th>8 </th> <td>ace2</td> <td>ACE v2 present: <code>REP XCRYPTCTR</code> instruction, as well as support for digest mode and misaligned data for ACE's <code>REP XCRYPT*</code> instructions. </td></tr> <tr> <th>9 </th> <td>ace2_en</td> <td>ACE v2 enabled </td></tr> <tr> <th>10 </th> <td>phe</td> <td>PadLock Hash Engine (PHE): <code>REP XSHA1</code> and <code>REP XSHA256</code> instructions </td></tr> <tr> <th>11 </th> <td>phe_en</td> <td>PHE enabled </td></tr> <tr> <th>12 </th> <td>pmm</td> <td>PadLock <a href="/wiki/Montgomery_modular_multiplication" title="Montgomery modular multiplication">Montgomery Multiplier</a> (PMM): <code>REP MONTMUL</code> instruction </td></tr> <tr> <th>13 </th> <td>pmm_en</td> <td>PMM enabled </td></tr> <tr> <th>14 </th> <td colspan="2" style="text-align:center; background:lightgrey;">(reserved) </td></tr> <tr> <th>15 </th> <td>zx_fma</td> <td>FMA supported </td></tr> <tr> <th>16 </th> <td>parallax</td> <td>Adaptive <a href="/wiki/ACPI#Performance_state" title="ACPI">P-state</a> control present </td></tr> <tr> <th>17 </th> <td>parallax_en</td> <td>Adaptive P-state control enabled </td></tr> <tr> <th>18 </th> <td>overstress</td> <td>Overstress feature for auto overclock present </td></tr> <tr> <th>19 </th> <td>overstress_en</td> <td>Overstress feature for auto overclock enabled </td></tr> <tr> <th>20 </th> <td>tm3</td> <td>Thermal Monitor 3 present </td></tr> <tr> <th>21 </th> <td>tm3_en</td> <td>Thermal Monitor 3 enabled </td></tr> <tr> <th>22 </th> <td>rng2</td> <td>RNG v2: Second generation RNG present </td></tr> <tr> <th>23 </th> <td>rng2_en</td> <td>RNG v2 enabled </td></tr> <tr> <th>24 </th> <td>sem</td> <td>SME feature present </td></tr> <tr> <th>25 </th> <td>phe2</td> <td>PHE v2: SHA384 and SHA512 present </td></tr> <tr> <th>26 </th> <td>phe2_en</td> <td>PHE v2 enabled </td></tr> <tr> <th>27 </th> <td>xmodx</td> <td>RSA instructions present: <code>XMODEXP</code> and <code>MONTMUL2</code> </td></tr> <tr> <th>28 </th> <td>xmodx_en</td> <td>RSA instructions enabled </td></tr> <tr> <th>29 </th> <td>vex</td> <td>VEX instructions present </td></tr> <tr> <th>30 </th> <td>vex_en</td> <td>VEX instructions enabled </td></tr> <tr> <th>31 </th> <td>stk</td> <td>STK is present </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-nehemiah_special-243">^ <a href="#cite_ref-nehemiah_special_243-0">a</a> <a href="#cite_ref-nehemiah_special_243-1">b</a> <a href="#cite_ref-nehemiah_special_243-2">c</a> <a href="#cite_ref-nehemiah_special_243-3">d</a> On VIA <a href="/wiki/VIA_C3#Nehemiah_cores" title="VIA C3">Nehemiah</a> and Antaur CPUs (<code>CentaurHauls</code> Family 6 Model 9 only),<a href="#cite_note-242">[181]</a> bits 0,1,4,5 are used differently: <ul><li>Bit 0: <a href="/wiki/Alternate_Instruction_Set" title="Alternate Instruction Set">Alternate Instruction Set</a> (AIS) present</li> <li>Bit 1: AIS enabled</li> <li>Bit 4: <a href="/wiki/LongHaul" title="LongHaul">LongHaul</a> MSR (MSR <code>0x110A</code>) present</li> <li>Bit 5: <code><a href="/wiki/3DNow!" title="3DNow!">FEMMS</a></code> instruction (opcode <code>0F 0E</code>) present</li></ul> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="CPUID_usage_from_high-level_languages">CPUID usage from high-level languages</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=42" title="Edit section: CPUID usage from high-level languages">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="Inline_assembly">Inline assembly</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=43" title="Edit section: Inline assembly">edit</a>]</div> This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid: <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #include <cpuid.h> int main() { unsigned int i, eax, ebx, ecx, edx; for (i = 0; i < 5; i++) { __cpuid(i, eax, ebx, ecx, edx); printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, eax, ebx, ecx, edx); } return 0; } </pre></div> In MSVC and Borland/Embarcadero C compilers (bcc32) flavored inline assembly, the clobbering information is implicit in the instructions: <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> int main() { unsigned int a, b, c, d, i = 0; __asm { /* Do the call. */ mov EAX, i; cpuid; /* Save results. */ mov a, EAX; mov b, EBX; mov c, ECX; mov d, EDX; } printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, a, b, c, d); return 0; } </pre></div> If either version was written in plain assembly language, the programmer must manually save the results of EAX, EBX, ECX, and EDX elsewhere if they want to keep using the values. <div class="mw-heading mw-heading3"><h3 id="Wrapper_functions">Wrapper functions</h3>[<a href="/w/index.php?title=CPUID&action=edit&section=44" title="Edit section: Wrapper functions">edit</a>]</div> GCC also provides a header called <code><cpuid.h></code> on systems that have CPUID. The <code>__cpuid</code> is a macro expanding to inline assembly. Typical usage would be: <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; __cpuid(0 /* vendor string */, eax, ebx, ecx, edx); printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx); return 0; } </pre></div> But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in <code><cpuid.h></code>. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers. <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #include <cpuid.h> int main() { unsigned int eax, ebx, ecx, edx; /* 0x81234567 is nonexistent, but assume it exists */ if (!__get_cpuid (0x81234567, &eax, &ebx, &ecx, &edx)) { printf("Warning: CPUID request 0x81234567 not valid!\n"); return 1; } printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx); return 0; } </pre></div> Notice the ampersands in <code>&a, &b, &c, &d</code> and the conditional statement. If the <code>__get_cpuid</code> call receives a correct request, it will return a non-zero value, if it fails, zero.<a href="#cite_note-244">[182]</a> Microsoft Visual C compiler has builtin function <code>__cpuid()</code> so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for <a href="/wiki/MSVC" class="mw-redirect" title="MSVC">MSVC</a> would be: <div class="mw-highlight mw-highlight-lang-cpp mw-content-ltr" dir="ltr"><pre>#include <stdio.h> #ifdef __MSVC__ #include <intrin.h> #endif int main() { unsigned int regs[4]; int i; for (i = 0; i < 4; i++) { __cpuid(regs, i); printf("The code %d gives %d, %d, %d, %d", regs[0], regs[1], regs[2], regs[3]); } return 0; } </pre></div> Many interpreted or compiled scripting languages are capable of using CPUID via an <a href="/wiki/Foreign_function_interface" title="Foreign function interface">FFI</a> library. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150429190703/http://www.cstrahan.com/posts/pure-ruby-cpuid-via-ffi.html">One such implementation</a> shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode. <a href="/wiki/.NET" title=".NET">.NET</a> 5 and later versions provide the <code>System.Runtime.Intrinsics.X86.X86base.CpuId</code> method. For instance, the C# code below prints the processor brand if it supports CPUID instruction:<div class="mw-highlight mw-highlight-lang-c# mw-content-ltr" dir="ltr"><pre>using System.Runtime.InteropServices; using System.Runtime.Intrinsics.X86; using System.Text; namespace X86CPUID { class CPUBrandString { public static void Main(string[] args) { if (!X86Base.IsSupported) { Console.WriteLine("Your CPU does not support CPUID instruction."); } else { Span<int> raw = stackalloc int[12]; (raw[0], raw[1], raw[2], raw[3]) = X86Base.CpuId(unchecked((int)0x80000002), 0); (raw[4], raw[5], raw[6], raw[7]) = X86Base.CpuId(unchecked((int)0x80000003), 0); (raw[8], raw[9], raw[10], raw[11]) = X86Base.CpuId(unchecked((int)0x80000004), 0); Span<byte> bytes = MemoryMarshal.AsBytes(raw); string brand = Encoding.UTF8.GetString(bytes).Trim(); Console.WriteLine(brand); } } } } </pre></div> <div class="mw-heading mw-heading2"><h2 id="CPU-specific_information_outside_x86">CPU-specific information outside x86</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=45" title="Edit section: CPU-specific information outside x86">edit</a>]</div> Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers: <ul><li><a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architectures</a> have a <code>CPUID</code> coprocessor register which requires <a href="/wiki/Protection_ring" title="Protection ring">exception level</a> EL1 or above to access.<a href="#cite_note-245">[183]</a></li> <li>The <a href="/wiki/IBM_System_z" class="mw-redirect" title="IBM System z">IBM System z</a> mainframe processors have a Store CPU ID (<code>STIDP</code>) instruction since the 1983 <a href="/wiki/IBM_4300" title="IBM 4300">IBM 4381</a><a href="#cite_note-246">[184]</a> for querying the processor ID.<a href="#cite_note-:0-247">[185]</a></li> <li>The <a href="/wiki/IBM_System_z" class="mw-redirect" title="IBM System z">IBM System z</a> mainframe processors also have a Store Facilities List Extended (<code>STFLE</code>) instruction which lists the installed hardware features.<a href="#cite_note-:0-247">[185]</a></li> <li>The <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS32/64</a> architecture defines a mandatory Processor Identification (<code>PrId</code>) and a series of daisy-chained Configuration Registers.<a href="#cite_note-248">[186]</a></li> <li>The <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> processor has the 32-bit read-only Processor Version Register (<code>PVR</code>) identifying the processor model in use. The instruction requires supervisor access level.<a href="#cite_note-249">[187]</a></li></ul> <a href="/wiki/Digital_signal_processor" title="Digital signal processor">DSP</a> and <a href="/wiki/Transputer" title="Transputer">transputer</a>-like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. Alternate ways of silicon identification might be present; for example, DSPs from <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> contain a memory-based register set for each functional unit that starts with identifiers determining the unit type and model, its <a href="/wiki/ASIC" class="mw-redirect" title="ASIC">ASIC</a> design revision and features selected at the design phase, and continues with unit-specific control and data registers. Access to these areas is performed by simply using the existing load and store instructions; thus, for such devices, there is no need for extending the register set for device identification purposes.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=46" title="Edit section: See also">edit</a>]</div> <ul><li><a rel="nofollow" class="external text" href="https://x86-cpuid.org/">x86-cpuid.org</a>, a complete x86 architecture CPUID database plus related code generation tools, to be used by both the <a href="/wiki/Linux_kernel" title="Linux kernel">Linux Kernel</a> and the <a href="/wiki/Xen_hypervisor" class="mw-redirect" title="Xen hypervisor">Xen hypervisor</a>. <a href="#cite_note-250">[188]</a></li> <li><a href="/wiki/CPU-Z" title="CPU-Z">CPU-Z</a>, a Windows utility that uses <code>CPUID</code> to identify various system settings</li> <li><a rel="nofollow" class="external text" href="https://thetumultuousunicornofdarkness.github.io/CPU-X/">CPU-X</a>, an alternative of CPU-Z for Linux and FreeBSD</li> <li><a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre (security vulnerability)</a></li> <li><a href="/wiki/Speculative_Store_Bypass" title="Speculative Store Bypass">Speculative Store Bypass</a> (SSB)</li> <li><a href="/wiki/Cpuinfo" class="mw-redirect" title="Cpuinfo"><style data-mw-deduplicate="TemplateStyles:r886049734">'"`UNIQ--templatestyles-0000018B-QINU`"'</style>/proc/cpuinfo</a>, a text file generated by certain systems containing some of the CPUID information</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=47" title="Edit section: References">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/design/processor/manuals/253668.pdf">"Intel 64 and IA-32 Architectures Software Developer's Manual"</a> (PDF). Intel.com. Retrieved 2013-04-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+64+and+IA-32+Architectures+Software+Developer%27s+Manual&rft.pub=Intel.com&rft_id=http%3A%2F%2Fwww.intel.com%2Fdesign%2Fprocessor%2Fmanuals%2F253668.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-2"><a href="#cite_ref-2">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.rcollins.org/ddj/Sep96/Sep96.html">"Detecting Intel Processors - Knowing the generation of a system CPU"</a>. Rcollins.org. Retrieved 2013-04-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Detecting+Intel+Processors+-+Knowing+the+generation+of+a+system+CPU&rft.pub=Rcollins.org&rft_id=http%3A%2F%2Fwww.rcollins.org%2Fddj%2FSep96%2FSep96.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-3"><a href="#cite_ref-3">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://archive.today/20120713012856/http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13%23L92">"LXR linux-old/arch/i386/kernel/head.S"</a>. Lxr.linux.no. Archived from <a rel="nofollow" class="external text" href="http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13#L92">the original</a> on 2012-07-13. Retrieved 2013-04-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=LXR+linux-old%2Farch%2Fi386%2Fkernel%2Fhead.S&rft.pub=Lxr.linux.no&rft_id=http%3A%2F%2Flxr.linux.no%2Fsource%2Farch%2Fi386%2Fkernel%2Fhead.S%3Fv%3D1.2.13%23L92&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-debs_cpuident-4">^ <a href="#cite_ref-debs_cpuident_4-0">a</a> <a href="#cite_ref-debs_cpuident_4-1">b</a> <a href="#cite_ref-debs_cpuident_4-2">c</a> Debbie Wiles, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt">CPU Identification</a>, archived on 2006-06-04 </li> <li id="cite_note-5"><a href="#cite_ref-5">^</a> B-CoolWare, <a rel="nofollow" class="external text" href="https://www.sac.sk/download/utildiag/cpu215.zip">TMi0SDGL</a> x86 CPU/FPU detection library with source code, v2.15, June 2000 - see /SOURCE/REALCODE.ASM for a large collection of pre-CPUID x86 CPU detection routines. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230314185852/https://www.sac.sk/download/utildiag/cpu215.zip">Archived</a> on 14 Mar 2023. </li> <li id="cite_note-6"><a href="#cite_ref-6">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://software.intel.com/en-us/forums/topic/306523?language=en#comment-1590394">"CPUID, EAX=4 - Strange results (Solved)"</a>. Software.intel.com. Retrieved 2014-07-10.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CPUID%2C+EAX%3D4+-+Strange+results+%28Solved%29&rft.pub=Software.intel.com&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fen-us%2Fforums%2Ftopic%2F306523%3Flanguage%3Den%23comment-1590394&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-7"><a href="#cite_ref-7">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFInstLatX642019" class="citation web cs1">@InstLatX64 (February 28, 2019). <a rel="nofollow" class="external text" href="https://x.com/InstLatX64/status/1101230794364862464">"First encounter with "GenuineIotel" (o after I, instead of n)"</a> (<a href="/wiki/Tweet_(social_media)" title="Tweet (social media)">Tweet</a>) – via <a href="/wiki/Twitter" title="Twitter">Twitter</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=First+encounter+with+%22GenuineIotel%22+%28o+after+I%2C+instead+of+n%29&rft.date=2019-02-28&rft.au=InstLatX64&rft_id=https%3A%2F%2Fx.com%2FInstLatX64%2Fstatus%2F1101230794364862464&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-8"><a href="#cite_ref-8">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/GenuineIotel/GenuineIotel00306C3_Haswell_CPUID5.txt">"GenuineIotel CPUID dump for Intel Xeon E3-1231"</a>. instlatx64.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=instlatx64&rft.atitle=GenuineIotel+CPUID+dump+for+Intel+Xeon+E3-1231&rft_id=http%3A%2F%2Fusers.atw.hu%2Finstlatx64%2FGenuineIotel%2FGenuineIotel00306C3_Haswell_CPUID5.txt&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-9"><a href="#cite_ref-9">^</a> instlatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/Genuine__RDC/Genuine%20%20RDC0000586_RDC_CPUID.txt">CPUID dump for RDC IAD 100</a>. Retrieved 22 December 2022. </li> <li id="cite_note-inxi197_elbrus-10">^ <a href="#cite_ref-inxi197_elbrus_10-0">a</a> <a href="#cite_ref-inxi197_elbrus_10-1">b</a> <a href="#cite_ref-inxi197_elbrus_10-2">c</a> <a href="#cite_ref-inxi197_elbrus_10-3">d</a> smxi, <a rel="nofollow" class="external text" href="https://codeberg.org/smxi/inxi/issues/197">Inxi issue 197: Elbrus CPU support data and implementation</a>. Retrieved 23 October 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231023190035/https://codeberg.org/smxi/inxi/issues/197">Archived</a> on 23 October 2023. </li> <li id="cite_note-11"><a href="#cite_ref-11">^</a> Grzegorz Mazur, <a rel="nofollow" class="external text" href="https://web.archive.org/web/19970524043213/http://grafi.ii.pw.edu.pl:80/gbm/x86/cpuid.html">Identification of x86 CPUs with CPUID support</a>, 5 May 1997. Archived from the <a rel="nofollow" class="external text" href="http://grafi.ii.pw.edu.pl:80/gbm/x86/cpuid.html">original</a> on 24 May 1997. </li> <li id="cite_note-12"><a href="#cite_ref-12">^</a> Ingo Böttcher, <a rel="nofollow" class="external text" href="https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ">CPUDET.PAS v1.61</a>, 23 Oct 1996 - CPU identification program that tests for "AMD ISBETTER" string. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240426153142/https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ">Archived</a> on 26 Apr 2024. </li> <li id="cite_note-13"><a href="#cite_ref-13">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFsorgelig2017" class="citation web cs1">sorgelig (Aug 3, 2017). <a rel="nofollow" class="external text" href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt">"ao486 CPUID instruction (in commit 43a2004)"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231204102715/https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt">Archived</a> from the original on 2023-12-04. Retrieved 2023-12-04.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=ao486+CPUID+instruction+%28in+commit+43a2004%29&rft.date=2017-08-03&rft.au=sorgelig&rft_id=https%3A%2F%2Fgithub.com%2FMiSTer-devel%2Fao486_MiSTer%2Fblob%2F43a20047d5e2e99f1264dadbdab777733ccbb61a%2Frtl%2Fao486%2Fcommands%2FCMD_CPUID.txt&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-:1-14">^ <a href="#cite_ref-:1_14-0">a</a> <a href="#cite_ref-:1_14-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFsorgelig2020" class="citation web cs1">sorgelig (Aug 30, 2020). <a rel="nofollow" class="external text" href="https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1">"Update cpuid. · MiSTer-devel/ao486_MiSTer@82f5014"</a>. GitHub. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231204102456/https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1">Archived</a> from the original on 2023-12-04. Retrieved 2023-12-04.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=Update+cpuid.+%C2%B7+MiSTer-devel%2Fao486_MiSTer%4082f5014&rft.date=2020-08-30&rft.au=sorgelig&rft_id=https%3A%2F%2Fgithub.com%2FMiSTer-devel%2Fao486_MiSTer%2Fcommit%2F82f5014bb44356e256a9c5454e8810d43a9990f1&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-15"><a href="#cite_ref-15">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFsorgelig2020" class="citation web cs1">sorgelig (Aug 30, 2020). <a rel="nofollow" class="external text" href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt">"ao486 CPUID instruction"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231023063725/https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt">Archived</a> from the original on October 23, 2023. Retrieved 4 Dec 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=ao486+CPUID+instruction&rft.date=2020-08-30&rft.au=sorgelig&rft_id=https%3A%2F%2Fgithub.com%2FMiSTer-devel%2Fao486_MiSTer%2Fblob%2Fmaster%2Frtl%2Fao486%2Fcommands%2FCMD_CPUID.txt&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-16"><a href="#cite_ref-16">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/valptek/v586">"v586: 586 compatible soft core for FPGA"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>. 6 December 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=v586%3A+586+compatible+soft+core+for+FPGA&rft.date=2021-12-06&rft_id=https%3A%2F%2Fgithub.com%2Fvalptek%2Fv586&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-17"><a href="#cite_ref-17">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://store.steampowered.com/hwsurvey/processormfg?sort=chg">"Steam Hardware & Software Survey"</a>. store.steampowered.com. Retrieved 2022-07-26.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=store.steampowered.com&rft.atitle=Steam+Hardware+%26+Software+Survey&rft_id=https%3A%2F%2Fstore.steampowered.com%2Fhwsurvey%2Fprocessormfg%3Fsort%3Dchg&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-18"><a href="#cite_ref-18">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://cpufun.substack.com/p/fun-with-timers-and-cpuid">"Fun with Timers and cpuid - by Jim Cownie - CPU fun"</a>. 3 March 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Fun+with+Timers+and+cpuid+-+by+Jim+Cownie+-+CPU+fun&rft.date=2021-03-03&rft_id=https%3A%2F%2Fcpufun.substack.com%2Fp%2Ffun-with-timers-and-cpuid&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-19"><a href="#cite_ref-19">^</a> virt-what source tree, <a rel="nofollow" class="external text" href="http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a">tests/lx86/proc/cpuinfo</a> - PowerVM Lx86 cpuinfo dump. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20241110183018/http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a">Archived</a> on 10 Nov 2024. </li> <li id="cite_note-20"><a href="#cite_ref-20">^</a> iXBT Labs, <a rel="nofollow" class="external text" href="http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html">VIA Nano CPUID Tricks</a>, Aug 26, 2010. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100829072405/http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html">Archived</a> on Aug 29, 2010. </li> <li id="cite_note-21"><a href="#cite_ref-21">^</a> IDT, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/wc_2_datasheet_a2.pdf">WinChip 2A data sheet</a>, v1.0, Jan 1999, page A-3. </li> <li id="cite_note-22"><a href="#cite_ref-22">^</a> VIA, <a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf">C3 Nehemiah Datasheet</a>, rev 1.13, Sep 29, 2004, page A-3. </li> <li id="cite_note-23"><a href="#cite_ref-23">^</a> Agner Fog, <a rel="nofollow" class="external text" href="http://www.agner.org/optimize/cpuidfake.zip">CpuIDFake, v1.00</a>, Jan 22, 2010, see "Instructions.txt". <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100709200509/http://www.agner.org/optimize/cpuidfake.zip">Archived</a> on Jul 9, 2010. </li> <li id="cite_note-transmeta_msr-24">^ <a href="#cite_ref-transmeta_msr_24-0">a</a> <a href="#cite_ref-transmeta_msr_24-1">b</a> Transmeta, <a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Transmeta/Crusoe/TM5900/tm5900_bisoguide_040123.pdf">Crusoe BIOS Programmer's Guide</a>, Jan 23, 2004, pages 63-65. </li> <li id="cite_note-25"><a href="#cite_ref-25">^</a> Transmeta, Efficeon BIOS Programmers Guide, Aug 19, 2003, section 8.3, page 148. </li> <li id="cite_note-26"><a href="#cite_ref-26">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf">Geode LX Data Book</a>, pub.id. 33234H, Feb. 2009, page 107. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231203113022/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf">Archived</a> on Dec 3, 2023. </li> <li id="cite_note-27"><a href="#cite_ref-27">^</a> DM&P, <a rel="nofollow" class="external text" href="https://www.vortex86.com/downloads/Vortex86EX2">Vortex86EX2_A9133_Master_Data_Sheet_V11_BF</a>, May 8, 2019, page 72. </li> <li id="cite_note-28"><a href="#cite_ref-28">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">"Chapter 3 Instruction Set Reference, A-L"</a> (PDF). Intel 64 and IA-32 Architectures Software Developer's Manual. Intel Corporation. 2018-12-20. Retrieved 2018-12-20.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Chapter+3+Instruction+Set+Reference%2C+A-L&rft.btitle=Intel+64+and+IA-32+Architectures+Software+Developer%27s+Manual&rft.pub=Intel+Corporation&rft.date=2018-12-20&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fen-us%2Fdownload%2Fintel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-29"><a href="#cite_ref-29">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241428-005.pdf">Pentium Processor Family Developer's Manual</a>, 1997, order no. 241428-005, sections 3.4.1.2 (page 91), 17.5.1 (page 489) and appendix A (page 522) provide more detail on how the "processor type" field and the "dual processor" designation work. </li> <li id="cite_note-30"><a href="#cite_ref-30">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/">x86, x64 Instruction Latency, Memory Latency and CPUID dumps</a>, 30 Sep 2023. </li> <li id="cite_note-32"><a href="#cite_ref-32">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf">Enhanced Am486DX Microprocessor Family</a>, pub.no. 20736 rev B, March 1997, section 9.2.2, page 55. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231018093730/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf">Archived</a> on 18 Oct 2023. </li> <li id="cite_note-33"><a href="#cite_ref-33">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf">ÉlanSC400 and ÉlanSC410 Microcontrollers User's Manual</a>, pub.no. 21030, 1997, section 3.6.2, page 73. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231018093705/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf">Archived</a> on 18 Oct 2023. </li> <li id="cite_note-34"><a href="#cite_ref-34">^</a> Cyrix, <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/cyrix/94246-00_5x86_CPU_BIOS_Writers_Guide_199510.pdf">5x86 BIOS Writers Guide</a>, rev 1.12, order no. 92426-00, 1995, page 7 </li> <li id="cite_note-cyrix_detguide-35">^ <a href="#cite_ref-cyrix_detguide_35-0">a</a> <a href="#cite_ref-cyrix_detguide_35-1">b</a> Cyrix, <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf">CPU Detection Guide</a>, rev 1.01, 2 Oct 1997, page 6. </li> <li id="cite_note-36"><a href="#cite_ref-36">^</a> MiSTer ao486 source code, <a rel="nofollow" class="external text" href="https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v">rtl/ao486/defines.v</a>, line 70. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231023193346/https://raw.githubusercontent.com/MiSTer-devel/ao486_MiSTer/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v">Archived</a> on 23 Oct 2023. </li> <li id="cite_note-37"><a href="#cite_ref-37">^</a> CPU-World, <a rel="nofollow" class="external text" href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102">CPUID for Vortex86DX2 933 MHz</a>. <a rel="nofollow" class="external text" href="https://archive.today/20231017222230/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102">Archived</a> on 17 Oct 2023. </li> <li id="cite_note-38"><a href="#cite_ref-38">^</a> CPU-World, <a rel="nofollow" class="external text" href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324">CPUID for Vortex86EX2</a>. <a rel="nofollow" class="external text" href="https://archive.today/20231018100523/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324">Archived</a> on 18 Oct 2023. </li> <li id="cite_note-39"><a href="#cite_ref-39">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt">Centaur CNS CPUID dump</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230530122012/http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt">Archived</a> on 30 May 2023. </li> <li id="cite_note-40"><a href="#cite_ref-40">^</a> Jeff Atwood, <a rel="nofollow" class="external text" href="https://blog.codinghorror.com/nasty-software-hacks-and-intels-cpuid/">Nasty Software Hacks and Intel's CPUID</a>. Coding Horror, 16 Aug 2005. </li> <li id="cite_note-intel_knc_ref-42">^ <a href="#cite_ref-intel_knc_ref_42-0">a</a> <a href="#cite_ref-intel_knc_ref_42-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf">Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual</a>, sep 2012, order no. 327364-001, appendix B.8, pages 673-674. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210804022347/https://software.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf">Archived</a> on 4 Aug 2021. </li> <li id="cite_note-43"><a href="#cite_ref-43">^</a> CPU-World, <a rel="nofollow" class="external text" href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724">CPUID for Intel Itanium 2 1.50 GHz</a>. <a rel="nofollow" class="external text" href="https://archive.today/20231017221310/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724">Archived</a> on 17 Oct 2023. </li> <li id="cite_note-44"><a href="#cite_ref-44">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/20240923173750.16874-1-tony.luck@intel.com/">"[PATCH] x86/cpu: Add two Intel CPU model numbers - Tony Luck"</a>. lore.kernel.org. Retrieved 2024-09-24.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=lore.kernel.org&rft.atitle=%5BPATCH%5D+x86%2Fcpu%3A+Add+two+Intel+CPU+model+numbers+-+Tony+Luck&rft_id=https%3A%2F%2Flore.kernel.org%2Flkml%2F20240923173750.16874-1-tony.luck%40intel.com%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-45"><a href="#cite_ref-45">^</a> InstLatX64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050671_KnightsLanding_CPUID2.txt">72-Core Intel Xeon Phi 7290 CPUID dump</a> </li> <li id="cite_note-46"><a href="#cite_ref-46">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A10F81_K19_StormPeak_01_CPUID.txt">96-Core AMD Ryzen Threadripper Pro 7995WX CPUID dump</a> </li> <li id="cite_note-48"><a href="#cite_ref-48">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20210417041749/https://bochs.sourceforge.io/techspec/24161821.pdf">Intel Processor Identification and the CPUID Instruction</a> (PDF), Intel, May 2002, archived from <a rel="nofollow" class="external text" href="http://bochs.sourceforge.net/techspec/24161821.pdf">the original</a> (PDF) on 2021-04-17</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Intel+Processor+Identification+and+the+CPUID+Instruction&rft.pub=Intel&rft.date=2002-05&rft_id=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2F24161821.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-50"><a href="#cite_ref-50">^</a> Linux 6.3 kernel sources, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v6.3/source/arch/x86/include/asm/cpuid.h">/arch/x86/include/asm/cpuid.h</a>, line 69 </li> <li id="cite_note-51"><a href="#cite_ref-51">^</a> gcc-patches mailing list, <a rel="nofollow" class="external text" href="https://gcc.gnu.org/pipermail/gcc-patches/2019-May/522177.html">CPUID Patch for IDT Winchip</a>, May 21, 2019 </li> <li id="cite_note-53"><a href="#cite_ref-53">^</a> Geoff Chappell, <a rel="nofollow" class="external text" href="https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm">CMPXCHG8B Support in the 32-Bit Windows Kernel</a>, Jan 23, 2008. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230130233150/https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm">Archived</a> on Jan 30, 2023. </li> <li id="cite_note-55"><a href="#cite_ref-55">^</a> AMD, <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/amd/x86/K86/20734D_AMD_Processor_Recognition_Application_Notes_Jan97.pdf">AMD Processor Recognition Application Note</a>, publication #20734, rev D, Jan 1997, page 13 </li> <li id="cite_note-57"><a href="#cite_ref-57">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-006.pdf">AP-485 Application Note - Intel Processor Identification and the CPUID Instruction</a>, order no. 241618-006, march 1997, table 5 on page 10, see bit 10. </li> <li id="cite_note-59"><a href="#cite_ref-59">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/sysenter-where-are-you/">SYSENTER, Where Are You?</a>, OS/2 Museum, July 20, 2017 </li> <li id="cite_note-62"><a href="#cite_ref-62">^</a> Geoff Chappell, <a rel="nofollow" class="external text" href="https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm">ECX From CPUID Leaf 1</a>, Jan 26, 2020. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200509082346/https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm">Archived</a> on May 9, 2020. </li> <li id="cite_note-65"><a href="#cite_ref-65">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHuggahalliIyerTetrick2005" class="citation journal cs1">Huggahalli, Ram; Iyer, Ravi; Tetrick, Scott (2005). "Direct Cache Access for High Bandwidth Network I/O". <a href="/w/index.php?title=ACM_SIGARCH_Computer_Architecture_News&action=edit&redlink=1" class="new" title="ACM SIGARCH Computer Architecture News (page does not exist)">ACM SIGARCH Computer Architecture News</a>. 33 (2): 50–59. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.85.3862">10.1.1.85.3862</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F1080695.1069976">10.1145/1080695.1069976</a>. <a href="/wiki/CiteSeerX" title="CiteSeerX">CiteSeerX</a>:<a rel="nofollow" class="external text" href="http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957">10.1.1.91.957</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=Direct+Cache+Access+for+High+Bandwidth+Network+I%2FO&rft.volume=33&rft.issue=2&rft.pages=50-59&rft.date=2005&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.85.3862%23id-name%3DCiteSeerX&rft_id=info%3Adoi%2F10.1145%2F1080695.1069976&rft.aulast=Huggahalli&rft.aufirst=Ram&rft.au=Iyer%2C+Ravi&rft.au=Tetrick%2C+Scott&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-66"><a href="#cite_ref-66">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDrepper2007" class="citation cs2">Drepper, Ulrich (2007), What Every Programmer Should Know About Memory, <a href="/wiki/CiteSeerX" title="CiteSeerX">CiteSeerX</a>:<a rel="nofollow" class="external text" href="http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957">10.1.1.91.957</a></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=What+Every+Programmer+Should+Know+About+Memory&rft.date=2007&rft.aulast=Drepper&rft.aufirst=Ulrich&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-ia64_sdm-67">^ <a href="#cite_ref-ia64_sdm_67-0">a</a> <a href="#cite_ref-ia64_sdm_67-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf">Itanium Architecture Software Developer's Manual, rev 2.3, volume 4: IA-32 Instruction Set</a>, may 2010, document number: 323208, table 2-5, page 4:81, see bits 20 and 30. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120215121932/https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf">Archived</a> on Feb 15, 2012. </li> <li id="cite_note-69"><a href="#cite_ref-69">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-030.pdf">AP-485, Processor Identification and the CPUID Instruction flag</a>, rev 30, jan 2006, page 26 </li> <li id="cite_note-70"><a href="#cite_ref-70">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/htt-means-hyper-threading-right/">HTT Means Hyper-Threading, Right?</a>, OS/2 Museum, dec 11, 2017 </li> <li id="cite_note-VMware_KB_1009458-72"><a href="#cite_ref-VMware_KB_1009458_72-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://kb.vmware.com/s/article/1009458">"Mechanisms to determine if software is running in a VMware virtual machine"</a>. VMware Knowledge Base. <a href="/wiki/VMWare" class="mw-redirect" title="VMWare">VMWare</a>. 2015-05-01. <q>Intel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VMware+Knowledge+Base&rft.atitle=Mechanisms+to+determine+if+software+is+running+in+a+VMware+virtual+machine&rft.date=2015-05-01&rft_id=https%3A%2F%2Fkb.vmware.com%2Fs%2Farticle%2F1009458&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-73"><a href="#cite_ref-73">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKatariaHecht2008" class="citation web cs1">Kataria, Alok; Hecht, Dan (2008-10-01). <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/">"Hypervisor CPUID Interface Proposal"</a>. <a href="/wiki/LKML" class="mw-redirect" title="LKML">LKML</a> Archive on lore.kernel.org. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190315105121/https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/">Archived</a> from the original on 2019-03-15. <q>Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future CPU's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Hypervisor+CPUID+Interface+Proposal&rft.pub=LKML+Archive+on+lore.kernel.org&rft.date=2008-10-01&rft.aulast=Kataria&rft.aufirst=Alok&rft.au=Hecht%2C+Dan&rft_id=https%3A%2F%2Flore.kernel.org%2Flkml%2F1222881242.9381.17.camel%40alok-dev1%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-74"><a href="#cite_ref-74">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230930084941/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf">"AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming"</a> (PDF) (3.41 ed.). Advanced Micro Devices, Inc. p. 498. 24593. Archived from <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf">the original</a> (PDF) on 30 Sep 2023. Retrieved 9 September 2023. <q>15.2.2 Guest Mode This new processor mode is entered through the VMRUN instruction. When in guest mode, the behavior of some x86 instructions changes to facilitate virtualization. The CPUID function numbers 4000_0000h-4000_00FFh have been reserved for software use. Hypervisors can use these function numbers to provide an interface to pass information from the hypervisor to the guest. This is similar to extracting information about a physical CPU by using CPUID. Hypervisors use the CPUID Fn 400000[FF:00] bit to denote a virtual platform. Feature bit CPUID Fn0000_0001_ECX[31] has been reserved for use by hypervisors to indicate the presence of a hypervisor. Hypervisors set this bit to 1 and physical CPU's set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD64+Technology+AMD64+Architecture+Programmer%27s+Manual+Volume+2%3A+System+Programming&rft.pages=498&rft.edition=3.41&rft.pub=Advanced+Micro+Devices%2C+Inc.&rft_id=https%3A%2F%2Fwww.amd.com%2Fcontent%2Fdam%2Famd%2Fen%2Fdocuments%2Fprocessor-tech-docs%2Fprogrammer-references%2F24593.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-75"><a href="#cite_ref-75">^</a> Intel <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253666-053.pdf">SDM vol 2A</a>, order no. 253666-053, Jan 2015, p. 244 </li> <li id="cite_note-ap485_rev037-77">^ <a href="#cite_ref-ap485_rev037_77-0">a</a> <a href="#cite_ref-ap485_rev037_77-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-037.pdf">Processor Identification and the CPUID Instruction Application Note 485</a>, order no. 241618-037, Jan 2011, pages 31-32. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231017194149/https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-037.pdf">Archived</a> on 17 Oct 2023. </li> <li id="cite_note-79"><a href="#cite_ref-79">^</a> Intel, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20040218001603/http://www.intel.com/design/itanium/downloads/24532003.pdf">Itanium Processor Reference Manual for Software Development</a>, rev 2.0, order no. 245320-003, December 2001, page 110. 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Retrieved 2018-05-26.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Speculative+Execution+Side+Channel+Mitigations&rft.series=Revision+2.0&rft.pub=Intel&rft.date=2018-05&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fsites%2Fdefault%2Ffiles%2Fmanaged%2Fc5%2F63%2F336996-Speculative-Execution-Side-Channel-Mitigations.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-136"><a href="#cite_ref-136">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://lwn.net/Articles/743019/">"IBRS patch series [LWN.net]"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=IBRS+patch+series+%5BLWN.net%5D&rft_id=https%3A%2F%2Flwn.net%2FArticles%2F743019%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-intel_fred_spec-138">^ <a href="#cite_ref-intel_fred_spec_138-0">a</a> <a href="#cite_ref-intel_fred_spec_138-1">b</a> <a href="#cite_ref-intel_fred_spec_138-2">c</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf">Flexible Return and Event Delivery (FRED) Specification</a>, rev 6.1, December 2023, order no. 346446-007, page 14. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231222195250/https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf">Archived</a> on Dec 22, 2023. </li> <li id="cite_note-139"><a href="#cite_ref-139">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/325462-080.pdf">Software Developer's Manual</a>, order no. 325462-080, June 2023 - information about prematurely busy shadow stacks provided in Volume 1, section 17.2.3 on page 410; Volume 2A, table 3.8 (CPUID EAX=7,ECX=2) on page 820; Volume 3C, table 25-14 on page 3958 and section 26.4.3 on page 3984. </li> <li id="cite_note-140"><a href="#cite_ref-140">^</a> LKML, <a rel="nofollow" class="external text" href="https://lkml.org/lkml/2023/6/16/1194">Re: (PATCH v3 00/21) Enable CET Virtualization</a>, Jun 16, 2023 - provides additional discussion of how the CET-SSS prematurely-busy stack issue interacts with virtualization. </li> <li id="cite_note-intel_avx10_1-141">^ <a href="#cite_ref-intel_avx10_1_141-0">a</a> <a href="#cite_ref-intel_avx10_1_141-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf">Advanced Vector Extensions 10</a>, rev 1.0, July 2023, order no. 355989-001. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230724201235/https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf">Archived</a> on Jul 24, 2023. </li> <li id="cite_note-intel_apx20-142">^ <a href="#cite_ref-intel_apx20_142-0">a</a> <a href="#cite_ref-intel_apx20_142-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf">Advanced Performance Extensions - Architecture Specification</a>, rev 2.0, Aug 2023, order no. 355828-002, page 37. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230910083914/https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf">Archived</a> on Sep 10, 2023. </li> <li id="cite_note-intel_bhi-144">^ <a href="#cite_ref-intel_bhi_144-0">a</a> <a href="#cite_ref-intel_bhi_144-1">b</a> <a href="#cite_ref-intel_bhi_144-2">c</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html">Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598</a>, 4 Aug 2022. <a rel="nofollow" class="external text" href="https://archive.today/20230505163802/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html">Archived</a> on 5 May 2023. </li> <li id="cite_note-145"><a href="#cite_ref-145">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html">Return Stack Buffer Underflow / CVE-2022-29901, CVE-2022-28693 / INTEL-SA-00702</a>, 12 Jul 2022. <a rel="nofollow" class="external text" href="https://archive.today/20220713102638/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html">Archived</a> on 13 Jul 2022. </li> <li id="cite_note-149"><a href="#cite_ref-149">^</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf">Asynchronous Enclave Exit Notify and the EDECCSSA User Leaf Function</a>, 30 Jun 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20221121073302/https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf">Archived</a> on 21 Nov 2022. </li> <li id="cite_note-152"><a href="#cite_ref-152">^</a> Linux kernel git commit 604dc91, <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/commit/604dc9170f2435d27da5039a3efd757dceadc684">x86/tsc: Use CPUID.0x16 to calculate missing crystal frequency</a>, 9 May 2019 - contains notes on computing the Core Crystal Clock frequency on CPUs that don't specify it, and corresponding C code. </li> <li id="cite_note-153"><a href="#cite_ref-153">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253668-083.pdf">SDM Volume 3A</a>, order no 253668-083, March 2024, chapter 11.5.4, page 408 </li> <li id="cite_note-154"><a href="#cite_ref-154">^</a> instlatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel007065A_Spreadtrum_CPUID.txt">Spreadtrum SC9853I-IA CPUID dump</a> </li> <li id="cite_note-158"><a href="#cite_ref-158">^</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf">Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module</a>, order no. 344425-005, page 93, Feb 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230720220842/https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf">Archived</a> on 20 Jul 2023. </li> <li id="cite_note-intel_knc_cpuid_ref-159">^ <a href="#cite_ref-intel_knc_cpuid_ref_159-0">a</a> <a href="#cite_ref-intel_knc_cpuid_ref_159-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf">Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual</a>, Sep 2012, order no. 327364-001, appendix B.8, pages 677. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210804022347/https://software.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf">Archived</a> on 4 Aug 2021. </li> <li id="cite_note-microsoft_tlfs-160">^ <a href="#cite_ref-microsoft_tlfs_160-0">a</a> <a href="#cite_ref-microsoft_tlfs_160-1">b</a> Microsoft, <a rel="nofollow" class="external text" href="https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery">Hyper-V Feature and Interface Discovery</a>, 8 Jul 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231118222643/https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery">Archived</a> on 18 Nov 2023. </li> <li id="cite_note-161"><a href="#cite_ref-161">^</a> Geoff Chappell, <a rel="nofollow" class="external text" href="https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm">HV_HYPERVISOR_INTERFACE</a>, 10 Dec 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230201083111/https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm">Archived</a> on 1 Feb 2023. </li> <li id="cite_note-162"><a href="#cite_ref-162">^</a> QEMU documentation, <a rel="nofollow" class="external text" href="https://www.qemu.org/docs/master/system/i386/hyperv.html">Hyper-V Enlightenments</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240417230400/https://www.qemu.org/docs/master/system/i386/hyperv.html">Archived</a> on 17 Apr 2024. </li> <li id="cite_note-163"><a href="#cite_ref-163">^</a> Linux 6.8.7 kernel source, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/cpuid.c">/source/arch/x86/kvm/cpuid.c</a>, lines 1482-1488 </li> <li id="cite_note-164"><a href="#cite_ref-164">^</a> Linux kernel documentation, <a rel="nofollow" class="external text" href="https://docs.kernel.org/virt/kvm/x86/cpuid.html">KVM CPUID bits</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220822051320/https://docs.kernel.org/virt/kvm/x86/cpuid.html">Archived</a> on 22 Aug 2022. </li> <li id="cite_note-165"><a href="#cite_ref-165">^</a> Linux 6.8.7 kernel source, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/hyperv.c#L2793">/arch/x86/kvm/hyperv.c, line 2793</a> </li> <li id="cite_note-166"><a href="#cite_ref-166">^</a> Linux kernel documentation, <a rel="nofollow" class="external text" href="https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid">Virtualization support: 4.118 KVM_GET_SUPPORTED_HV_CPUID</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240316062357/https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid">Archived</a> on 26 Mar 2024. </li> <li id="cite_note-167"><a href="#cite_ref-167">^</a> FreeBSD <a rel="nofollow" class="external text" href="https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5">commit 560d5ed</a>, 28 Jun 2013, see file /sys/amd64/vmm/x86.c, line 48. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240422224954/https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5">Archived</a> on 22 Apr 2024. </li> <li id="cite_note-168"><a href="#cite_ref-168">^</a> HyperKit source code, <a rel="nofollow" class="external text" href="https://github.com/moby/hyperkit/blob/45c0ba15f100871ba29d0bd227ca58e5426a4a50/src/lib/vmm/x86.c#L42">/src/lib/vmm/x86.c line 42</a>, 8 May 2021. </li> <li id="cite_note-169"><a href="#cite_ref-169">^</a> Xen, <a rel="nofollow" class="external text" href="https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html">CPUID Interface to Xen</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240422225902/https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html">Archived</a> on 22 Apr 2024. </li> <li id="cite_note-170"><a href="#cite_ref-170">^</a> QEMU source code, <a rel="nofollow" class="external text" href="https://github.com/qemu/qemu/blob/2cc68629a6fc198f4a972698bdd6477f883aedfb/target/i386/cpu.c#L6475">fb/target/i386/cpu.c, line 6475</a>, 18 Mar 2024. </li> <li id="cite_note-171"><a href="#cite_ref-171">^</a> VMWare, <a rel="nofollow" class="external text" href="https://kb.vmware.com/s/article/1009458">Mechanisms to determine if software is running in a VMware virtual machine</a>, 1 May 2015. <a rel="nofollow" class="external text" href="https://archive.today/20230618210301/https://kb.vmware.com/s/article/1009458">Archived</a> on 18 Jun 2023. </li> <li id="cite_note-172"><a href="#cite_ref-172">^</a> Project ACRN, <a rel="nofollow" class="external text" href="https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization">CPUID Virtualization</a>, 20 Oct 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230325163003/https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization">Archived</a> on 25 Mar 2023. </li> <li id="cite_note-173"><a href="#cite_ref-173">^</a> VirtualBox documentation, <a rel="nofollow" class="external text" href="https://www.virtualbox.org/manual/ch09.html#gimdebug">9.30 Paravirtualized Debugging</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240422140649/https://www.virtualbox.org/manual/ch09.html#gimdebug">Archived</a> on 22 Apr 2024. </li> <li id="cite_note-174"><a href="#cite_ref-174">^</a> QNX, <a rel="nofollow" class="external text" href="https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html">Hypervisor - Checking the guest's environment</a>, 25 Mar 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240422005549/https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html">Archived</a> on 22 Apr 2024. </li> <li id="cite_note-175"><a href="#cite_ref-175">^</a> NetBSD source code, <a rel="nofollow" class="external text" href="https://github.com/NetBSD/src/blob/90116d8fc2f0c32a7863c868afa8d77e9a865cc7/sys/dev/nvmm/x86/nvmm_x86_vmx.c#L1430">/sys/dev/nvmm/x86/nvmm_x86_vmx.c, line 1430</a>, 6 Nov 2023. </li> <li id="cite_note-176"><a href="#cite_ref-176">^</a> OpenBSD source code, <a rel="nofollow" class="external text" href="https://github.com/openbsd/src/blob/1ebbcee88fd42e4612c9e2e6d12b4aad159f7741/sys/arch/amd64/include/vmmvar.h#L24">/sys/arch/amd64/include/vmmvar.h, line 24</a>, 9 Apr 2024. </li> <li id="cite_note-177"><a href="#cite_ref-177">^</a> Siemens Jailhouse hypervisor documentation, <a rel="nofollow" class="external text" href="https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt">hypervisor-interfaces.txt, line 39</a>, 27 Jan 2020. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240705104235/https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt">Archived</a> on Jul 5, 2024. </li> <li id="cite_note-178"><a href="#cite_ref-178">^</a> Intel HAXM source code, <a rel="nofollow" class="external text" href="https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c#L979">/core/cpuid.c, line 979</a>, 20 Jan 2023. <a rel="nofollow" class="external text" href="https://archive.today/20240422234829/https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c%23L979">Archived</a> on 22 Apr 2024. </li> <li id="cite_note-ikgt-source-179"><a href="#cite_ref-ikgt-source_179-0">^</a> Intel KGT source code (trusty branch), <a rel="nofollow" class="external text" href="https://github.com/intel/ikgt-core/blob/7dfd4d1614d788ec43b02602cce7a272ef8d5931/vmm/vmexit/vmexit_cpuid.c">/vmm/vmexit/vmexit_cpuid.c, lines 17-75</a>, 15 May 2019 </li> <li id="cite_note-180"><a href="#cite_ref-180">^</a> Linux kernel v5.18.19 source code, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v5.18.19/source/drivers/visorbus/visorchipset.c">/source/drivers/visorbus/visorchipset.c, line 28</a> </li> <li id="cite_note-181"><a href="#cite_ref-181">^</a> N. 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Section 2.2.2 (p.20) and Section 3 (pages 33 to 40) provide details on how CPUID.(EAX=8000_0001):EDX[bit 19] should be used to identify processors. Section 3 also provides information on AMD's brand name string MSRs. Archived from the <a rel="nofollow" class="external text" href="http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf">original</a> on Jun 26, 2006. </li> <li id="cite_note-196"><a href="#cite_ref-196">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/31116.pdf">Family 10h BKDG</a>, document no. 31116, rev 3.62, jan 11, 2013, p. 388 - lists the NodeId bit. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf">Archived</a> on 16 Jan 2019. </li> <li id="cite_note-197"><a href="#cite_ref-197">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.20.pdf">AMD64 Architecture Programmer's Manual Volume 3</a>, pub. no. 24594, rev 3.20, may 2013, page 579 - lists the StreamPerfMon bit </li> <li id="cite_note-intel1-199"><a href="#cite_ref-intel1_199-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://download.intel.com/design/processor/applnots/24161832.pdf">"Intel Processor Identification and the CPUID Instruction"</a> (PDF). Download.intel.com. 2012-03-06. Retrieved 2013-04-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Processor+Identification+and+the+CPUID+Instruction&rft.pub=Download.intel.com&rft.date=2012-03-06&rft_id=http%3A%2F%2Fdownload.intel.com%2Fdesign%2Fprocessor%2Fapplnots%2F24161832.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-200"><a href="#cite_ref-200">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt">Vortex86DX3 CPUID dump</a>, 27 Sep 2021. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211021212842/http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt">Archived</a> on 21 Oct 2021. </li> <li id="cite_note-201"><a href="#cite_ref-201">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt">AMD Ryzen 7 6800HS CPUID dump</a>, 21 Feb 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230324010348/http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt">Archived</a> on 24 Mar 2023. </li> <li id="cite_note-202"><a href="#cite_ref-202">^</a> Chips and Cheese, <a rel="nofollow" class="external text" href="https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/">Why you can't trust CPUID</a>, 27 Oct 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20221103061909/https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/">Archived</a> on 3 Nov 2022. </li> <li id="cite_note-203"><a href="#cite_ref-203">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf">Geode LX Databook</a>, pub.id. 33234H, Feb 2009, page 207. </li> <li id="cite_note-204"><a href="#cite_ref-204">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_Jintide_CPUID1.txt">2x 24-core Montage Jintide C2460</a> CPUID dump </li> <li id="cite_note-205"><a href="#cite_ref-205">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_20_CPUID.txt">2x 24-core Intel Xeon Platinum 8160</a> CPUID dump </li> <li id="cite_note-206"><a href="#cite_ref-206">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID3.txt">Zhaoxin KaiXian ZX-C+ C4580</a> CPUID dump </li> <li id="cite_note-207"><a href="#cite_ref-207">^</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID.txt">VIA Eden X4 C4250</a> CPUID dump </li> <li id="cite_note-208"><a href="#cite_ref-208">^</a> Cyrix, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Cyrix/112.pdf">Application Note 112: Cyrix CPU Detection Guide</a>, page 17, 21 July 1998. </li> <li id="cite_note-210"><a href="#cite_ref-210">^</a> Instlatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0000663_C5A_Samuel_CPUID.txt">VIA Cyrix III "Samuel" CPUID dump</a> </li> <li id="cite_note-214"><a href="#cite_ref-214">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/31116.pdf">BKDG for AMD Family 10h Processors</a>, pub.no. 31116, rev 3.62, jan 11, 2013, page 392. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf">Archived</a> on 16 Jan 2019. </li> <li id="cite_note-amd_56713_p99-215">^ <a href="#cite_ref-amd_56713_p99_215-0">a</a> <a href="#cite_ref-amd_56713_p99_215-1">b</a> <a href="#cite_ref-amd_56713_p99_215-2">c</a> <a href="#cite_ref-amd_56713_p99_215-3">d</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">PPR For AMD Family 19h Model 61h rev B1 procesors</a>, pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">Archived</a> on 25 Apr 2023. </li> <li id="cite_note-216"><a href="#cite_ref-216">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf">BKDG for AMD Family 16h Models 00-0Fh processors</a>, pub.no. 48571, rev 3.03, Feb 19, 2015, page 482. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190116230055/https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf">Archived</a> on 16 Jan 2019. </li> <li id="cite_note-217"><a href="#cite_ref-217">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/26094.PDF">BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors</a>, publication #26094, rev 3.30, feb 2006, pages 29-30 (lists Athlon 64 revision differences, including LMSLE) (<a rel="nofollow" class="external text" href="https://web.archive.org/web/20190116230059/https://www.amd.com/system/files/TechDocs/26094.PDF">archived</a> on 16 Jan 2019), and <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/25759.pdf">Revision Guide for AMD Athlon 64 and AMD Opteron Processors</a>, publication #25759, rev 3.79, july 2009, pages 7-8 (lists Athlon 64 revision IDs) (<a rel="nofollow" class="external text" href="https://web.archive.org/web/20190118074904/https://www.amd.com/system/files/TechDocs/25759.pdf">archived</a> on 18 Jan 2019). </li> <li id="cite_note-219"><a href="#cite_ref-219">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip">PPR for AMD Family 19h Model 01h, Revision B1 Processors, Volume 1 of 2</a>, document no. 55898, rev 0.50, may 27, 2021, page 98 - lists branch-sampling bit. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220724144832/https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip">Archived</a> on Jul 24, 2022 </li> <li id="cite_note-221"><a href="#cite_ref-221">^</a> AMD, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110613111809/http://www.mimuw.edu.pl/~vincent/lecture6/sources/amd-pacifica-specification.pdf">AMD64 Virtualization Codenamed "Pacifica" Technology</a>, publication no. 33047, rev 3.01, May 2005, appendix B, page 81. Archived on Jun 13, 2011. </li> <li id="cite_note-222"><a href="#cite_ref-222">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.18.pdf">CPUID specification</a>, publication #25481, revision 2.18, jan 2006, page 18. </li> <li id="cite_note-223"><a href="#cite_ref-223">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf">CPUID specification</a>, publication #25481, revision 2.34, sep 2010, pages 5 and 11. </li> <li id="cite_note-225"><a href="#cite_ref-225">^</a> Instlatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0500F10_K14_Bobcat_CPUID.txt">AMD E-350 CPUID dump</a> - has CPUID.(EAX=8000000A):EDX[9] set. </li> <li id="cite_note-226"><a href="#cite_ref-226">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.28.pdf">CPUID specification</a>, publication #25481, revision 2.28, apr 2008, page 21. </li> <li id="cite_note-227"><a href="#cite_ref-227">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf">CPUID specification</a>, publication #25481, revision 2.34, sep 2010, page 5 - lists "SseIsa10Compat" as having been dropped in November 2009. </li> <li id="cite_note-amd_56713-229">^ <a href="#cite_ref-amd_56713_229-0">a</a> <a href="#cite_ref-amd_56713_229-1">b</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">PPR for AMD Family 19h Model 61h, Revision B1 processors</a>, document no. 56713, rev 3.05, mar 8 2023, page 102. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">Archived</a> on Apr 25, 2023. </li> <li id="cite_note-amd_zen5_ppr-230">^ <a href="#cite_ref-amd_zen5_ppr_230-0">a</a> <a href="#cite_ref-amd_zen5_ppr_230-1">b</a> <a href="#cite_ref-amd_zen5_ppr_230-2">c</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip">Processor Programming Reference (PPR) for AMD Family 1Ah Model 24h, Revision B0 Processors</a>, order no. 57254, rev 3.00, Sep 26, 2024, pages 102, 118, 119 and 199. </li> <li id="cite_note-231"><a href="#cite_ref-231">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/58019_1.00.pdf">Secure VM Service Module for SEV-SNP Guests</a>, pub.no #58019, rev 1.00, Jul 2023, page 13. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230805094438/https://www.amd.com/system/files/TechDocs/58019_1.00.pdf">Archived</a> on 5 Aug 2023. </li> <li id="cite_note-amd_56713_p116-232">^ <a href="#cite_ref-amd_56713_p116_232-0">a</a> <a href="#cite_ref-amd_56713_p116_232-1">b</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">PPR for AMD Family 19h Model 61h, Revision B1 processors</a>, document no. 56713, rev 3.05, mar 8 2023, page 116. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">Archived</a> on Apr 25, 2023. </li> <li id="cite_note-233"><a href="#cite_ref-233">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/5th-gen-amd-epyc-processor-architecture-white-paper.pdf">5th Gen AMD EPYC Processor Architecture</a>, First Edition, October 2024, page 9. </li> <li id="cite_note-amd_srso-235">^ <a href="#cite_ref-amd_srso_235-0">a</a> <a href="#cite_ref-amd_srso_235-1">b</a> <a href="#cite_ref-amd_srso_235-2">c</a> <a href="#cite_ref-amd_srso_235-3">d</a> <a href="#cite_ref-amd_srso_235-4">e</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf">Technical Update Regarding Speculative Return Stack Overflow</a>, rev 2.0, feb 2024. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240412225347/https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf">Archived</a> on Apr 12, 2024. </li> <li id="cite_note-236"><a href="#cite_ref-236">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFFerrie" class="citation web cs1">Ferrie, Peter. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070207103157/http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf">"Attacks on Virtual Machine Emulators"</a> (PDF). <a href="/wiki/Broadcom#Symantec_enterprise_security" title="Broadcom">Symantec</a>. Symantec Advanced Threat Research. Archived from <a rel="nofollow" class="external text" href="http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf">the original</a> (PDF) on 2007-02-07. Retrieved 15 March 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Symantec&rft.atitle=Attacks+on+Virtual+Machine+Emulators&rft.aulast=Ferrie&rft.aufirst=Peter&rft_id=http%3A%2F%2Fwww.symantec.com%2Favcenter%2Freference%2FVirtual_Machine_Threats.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-237"><a href="#cite_ref-237">^</a> Sandpile, <a rel="nofollow" class="external text" href="https://sandpile.org/x86/cpuid.htm">x86 architecture CPUID</a>. Retrieved 22 December 2022. </li> <li id="cite_note-238"><a href="#cite_ref-238">^</a> instlatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0700F01_K16_Kabini_CPUID.txt">CPUID dump of AMD A4-5000</a>, lists "HELLO KITTY" string for CPUID leaf <code>8FFFFFFFh</code>. Retrieved 22 December 2022. </li> <li id="cite_note-239"><a href="#cite_ref-239">^</a> IDT, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/w2b_datasheet.pdf">WinChip 2B Processor Data Sheet</a>, v0.9, April 1999, chapter 3.3.3, page 31. </li> <li id="cite_note-240"><a href="#cite_ref-240">^</a> VIA, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261">PadLock Programming Guide</a> rev. 1.66, aug 4, 2005, page 5. Archived from the <a rel="nofollow" class="external text" href="http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261">original</a> on May 26, 2010 </li> <li id="cite_note-241"><a href="#cite_ref-241">^</a> OpenEuler 1.0 LTS kernel sources, <a rel="nofollow" class="external text" href="https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h#L147">/arch/x86/include/asm/cpufeatures.h</a> lines 147-178. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230730113626/https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h">Archived</a> on Jul 30, 2023. </li> <li id="cite_note-242"><a href="#cite_ref-242">^</a> VIA, <a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf">C3 Nehemiah Processor Datasheet</a>, rev 1.13, Sep 29, 2004, page 21 </li> <li id="cite_note-244"><a href="#cite_ref-244">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h">"GCC-mirror/GCC"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>. 13 March 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=GCC-mirror%2FGCC&rft.date=2022-03-13&rft_id=https%3A%2F%2Fgithub.com%2Fgcc-mirror%2Fgcc%2Fblob%2Fmaster%2Fgcc%2Fconfig%2Fi386%2Fcpuid.h&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-245"><a href="#cite_ref-245">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0395b/CIHCAGHH.html">"ARM Information Center"</a>. Infocenter.arm.com. Retrieved 2013-04-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=ARM+Information+Center&rft.pub=Infocenter.arm.com&rft_id=http%3A%2F%2Finfocenter.arm.com%2Fhelp%2Findex.jsp%3Ftopic%3D%2Fcom.arm.doc.dui0395b%2FCIHCAGHH.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-246"><a href="#cite_ref-246">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140908232904/https://www-304.ibm.com/servers/resourcelink/lib03060.nsf/pages/srmindex#Toc1">"Processor version codes and SRM constants"</a>. Archived from <a rel="nofollow" class="external text" href="https://www-304.ibm.com/servers/resourcelink/lib03060.nsf/pages/srmindex#Toc1">the original</a> on 2014-09-08. Retrieved 2014-09-08.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Processor+version+codes+and+SRM+constants&rft_id=https%3A%2F%2Fwww-304.ibm.com%2Fservers%2Fresourcelink%2Flib03060.nsf%2Fpages%2Fsrmindex%23Toc1&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-:0-247">^ <a href="#cite_ref-:0_247-0">a</a> <a href="#cite_ref-:0_247-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.redbooks.ibm.com/redbooks/pdfs/sg247516.pdf">"IBM System z10 Enterprise Class Technical Guide"</a> (PDF).</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=IBM+System+z10+Enterprise+Class+Technical+Guide&rft_id=http%3A%2F%2Fwww.redbooks.ibm.com%2Fredbooks%2Fpdfs%2Fsg247516.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-248"><a href="#cite_ref-248">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf">"MIPS32 Architecture For Programmers, Volume III: The MIPS32 Privileged Resource Architecture"</a> (PDF). MIPS Technologies, Inc. 2001-03-12.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=MIPS32+Architecture+For+Programmers%2C+Volume+III%3A+The+MIPS32+Privileged+Resource+Architecture&rft.pub=MIPS+Technologies%2C+Inc.&rft.date=2001-03-12&rft_id=http%3A%2F%2Fwww.cs.cornell.edu%2Fcourses%2Fcs3410%2F2008fa%2FMIPS_Vol3.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-249"><a href="#cite_ref-249">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://moss.csc.ncsu.edu/~mueller/cluster/ps3/SDK3.0/docs/arch/PPC_Vers202_Book3_public.pdf">"PowerPC Operating Environment Architecture, book III"</a> (PDF).</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PowerPC+Operating+Environment+Architecture%2C+book+III&rft_id=http%3A%2F%2Fmoss.csc.ncsu.edu%2F~mueller%2Fcluster%2Fps3%2FSDK3.0%2Fdocs%2Farch%2FPPC_Vers202_Book3_public.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> <li id="cite_note-250"><a href="#cite_ref-250">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFS._Darwish" class="citation web cs1">S. Darwish, Ahmed. <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/ZpkckA2SHa1r3Bor@lx-t490">"[ANNOUNCE] x86-cpuid.org: A machine-readable CPUID repository"</a>. Linux Kernel Mailing List archive. Retrieved 20 July 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Linux+Kernel+Mailing+List+archive&rft.atitle=%5BANNOUNCE%5D+x86-cpuid.org%3A+A+machine-readable+CPUID+repository&rft.aulast=S.+Darwish&rft.aufirst=Ahmed&rft_id=https%3A%2F%2Flore.kernel.org%2Flkml%2FZpkckA2SHa1r3Bor%40lx-t490&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=48" title="Edit section: Further reading">edit</a>]</div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf">"AMD64 Technology Indirect Branch Control Extension"</a> (PDF) (White paper). Revision 4.10.18. <a href="/wiki/Advanced_Micro_Devices,_Inc." class="mw-redirect" title="Advanced Micro Devices, Inc.">Advanced Micro Devices, Inc.</a> (AMD). 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180509093400/https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf">Archived</a> (PDF) from the original on 2018-05-09. Retrieved 2018-05-09.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD64+Technology+Indirect+Branch+Control+Extension&rft.series=Revision+4.10.18&rft.pub=Advanced+Micro+Devices%2C+Inc.+%28AMD%29&rft.date=2018&rft_id=https%3A%2F%2Fdeveloper.amd.com%2Fwp-content%2Fresources%2FArchitecture_Guidelines_Update_Indirect_Branch_Control.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPUID" class="Z3988"></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=CPUID&action=edit&section=49" title="Edit section: External links">edit</a>]</div> <ul><li>Intel <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120625025623/http://www.intel.com/Assets/PDF/appnote/241618.pdf">Processor Identification and the CPUID Instruction</a> (Application Note 485), last published version. Said to be incorporated into the <a rel="nofollow" class="external text" href="http://www.intel.com/Assets/PDF/appnote/241618.pdf">Intel 64 and IA-32 Architectures Software Developer's Manual</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130626034554/http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/processor-identification-cpuid-instruction-note.pdf">in 2013</a>, but as of July 2014<a class="external text" href="https://en.wikipedia.org/w/index.php?title=CPUID&action=edit">[update]</a> the manual still directs the reader to note 485. <ul><li>Contains some information that can be and was easily misinterpreted though, particularly with respect to <a href="#EAX=4_and_EAX=Bh:_Intel_thread/core_and_cache_topology">processor topology identification</a>.</li> <li>The big Intel manuals tend to lag behind the Intel ISA document, available at the top of <a rel="nofollow" class="external text" href="https://software.intel.com/en-us/intel-isa-extensions">this page</a>, which is updated even for processors not yet publicly available, and thus usually contains more CPUID bits. For example, as of this writing, the ISA book (at revision 19, dated May 2014) documents the CLFLUSHOPT bit in leaf 7, but the big manuals although apparently more up-to-date (at revision 51, dated June 2014) don't mention it.</li></ul></li> <li><a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf">AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions</a></li> <li><a rel="nofollow" class="external text" href="https://www.etallen.com/cpuid.html">cpuid</a> command-line program for Linux</li> <li><a rel="nofollow" class="external text" href="https://skanthak.homepage.t-online.de/cpuid.html">cpuprint.com, cpuprint.exe, cpuprint.raw</a> command-line programs for Windows</li> <li><a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/">instlatx64</a> - collection of x86/x64 Instruction Latency, Memory Latency and CPUID dumps</li></ul> <div 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.navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Instruction_set_extensions" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style 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abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Multimedia_extensions" title="Template:Multimedia extensions"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Multimedia_extensions" title="Template talk:Multimedia extensions"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Multimedia_extensions" title="Special:EditPage/Template:Multimedia extensions"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Instruction_set_extensions" style="font-size:114%;margin:0 4em"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Instruction set</a> <a href="/wiki/Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <ul><li><a href="/wiki/DEC_Alpha#Motion_Video_Instructions_(MVI)" title="DEC Alpha">MVI</a></li></ul></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> <ul><li><a href="/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)" title="ARM architecture family">NEON</a></li> <li><a href="/wiki/AArch64#Scalable_Vector_Extension_(SVE)" title="AArch64">SVE</a></li></ul></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <ul><li><a href="/wiki/MDMX" title="MDMX">MDMX</a></li> <li><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></li> <li><a href="/wiki/Media_Extension_Unit" class="mw-redirect" title="Media Extension Unit">MXU</a></li> <li><a href="/wiki/MIPS_architecture#MIPS_SIMD_architecture" title="MIPS architecture">MIPS SIMD</a></li></ul></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> <ul><li><a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">MAX</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/AltiVec" title="AltiVec">VMX</a></li></ul></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a> <ul><li><a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">VIS</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/X86" title="X86">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (1996)</li> <li><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> (1998)</li> <li><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> (1999)</li> <li><a href="/wiki/SSE2" title="SSE2">SSE2</a> (2001)</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a> (2004)</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (2006)</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a> (2006)</li> <li><a href="/wiki/SSE5" title="SSE5">SSE5</a> <s>(2007)</s></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> (2008)</li> <li><a href="/wiki/F16C" title="F16C">F16C</a> (2009)</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a> (2009)</li> <li><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> (FMA4: 2011, FMA3: 2012)</li> <li><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> (2013)</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (2015)</li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> (2022)</li> <li><a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bit_manipulation" title="Bit manipulation">Bit manipulation</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a> (2014)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS16e ASE</a></li> <li><a href="/wiki/RISC-V#Compressed_subset" title="RISC-V">RVC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li> <li><a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li> <li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> (2012)</li> <li><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA</a> (2013)</li> <li><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> (2015)</li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> (2015)</li> <li><a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> (2021)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> (2013)</li> <li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/X86_virtualization#Intel_virtualization_(VT-x)" title="X86 virtualization">VT-x</a> (2005)</li> <li><a href="/wiki/X86_virtualization#AMD_virtualization_(AMD-V)" title="X86 virtualization">AMD-V</a> (2006)</li> <li><a href="/wiki/X86_virtualization#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" title="X86 virtualization">VT-d</a> (AMD-Vi)</li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck 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