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architectures</title> <meta name="description" content="Search results for: multi-core architectures"> <meta name="keywords" content="multi-core architectures"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="multi-core architectures"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 305</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: multi-core architectures</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">305</span> A Survey on Constraint Solving Approaches Using Parallel Architectures</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nebras%20Gharbi">Nebras Gharbi</a>, <a href="https://publications.waset.org/abstracts/search?q=Itebeddine%20Ghorbel"> Itebeddine Ghorbel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In the latest years and with the advancements of the multicore computing world, the constraint programming community tried to benefit from the capacity of new machines and make the best use of them through several parallel schemes for constraint solving. In this paper, we propose a survey of the different proposed approaches to solve Constraint Satisfaction Problems using parallel architectures. These approaches use in a different way a parallel architecture: the problem itself could be solved differently by several solvers or could be split over solvers. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=constraint%20programming" title="constraint programming">constraint programming</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20programming" title=" parallel programming"> parallel programming</a>, <a href="https://publications.waset.org/abstracts/search?q=constraint%20satisfaction%20problem" title=" constraint satisfaction problem"> constraint satisfaction problem</a>, <a href="https://publications.waset.org/abstracts/search?q=speed-up" title=" speed-up"> speed-up</a> </p> <a href="https://publications.waset.org/abstracts/50394/a-survey-on-constraint-solving-approaches-using-parallel-architectures" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/50394.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">319</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">304</span> A Study of the Trade-off Energy Consumption-Performance-Schedulability for DVFS Multicore Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jalil%20Boudjadar">Jalil Boudjadar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Dynamic Voltage and Frequency Scaling (DVFS) multicore platforms are promising execution platforms that enable high computational performance, less energy consumption and flexibility in scheduling the system processes. However, the resulting interleaving and memory interference together with per-core frequency tuning make real-time guarantees hard to be delivered. Besides, energy consumption represents a strong constraint for the deployment of such systems on energy-limited settings. Identifying the system configurations that would achieve a high performance and consume less energy while guaranteeing the system schedulability is a complex task in the design of modern embedded systems. This work studies the trade-off between energy consumption, cores utilization and memory bottleneck and their impact on the schedulability of DVFS multicore time-critical systems with a hierarchy of shared memories. We build a model-based framework using Parametrized Timed Automata of UPPAAL to analyze the mutual impact of performance, energy consumption and schedulability of DVFS multicore systems, and demonstrate the trade-off on an actual case study. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=time-critical%20systems" title="time-critical systems">time-critical systems</a>, <a href="https://publications.waset.org/abstracts/search?q=multicore%20systems" title=" multicore systems"> multicore systems</a>, <a href="https://publications.waset.org/abstracts/search?q=schedulability%20analysis" title=" schedulability analysis"> schedulability analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=energy%20consumption" title=" energy consumption"> energy consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=performance%20analysis" title=" performance analysis"> performance analysis</a> </p> <a href="https://publications.waset.org/abstracts/117875/a-study-of-the-trade-off-energy-consumption-performance-schedulability-for-dvfs-multicore-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/117875.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">107</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">303</span> Evaluating the Impact of Replacement Policies on the Cache Performance and Energy Consumption in Different Multicore Embedded Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sajjad%20Rostami-Sani">Sajjad Rostami-Sani</a>, <a href="https://publications.waset.org/abstracts/search?q=Mojtaba%20Valinataj"> Mojtaba Valinataj</a>, <a href="https://publications.waset.org/abstracts/search?q=Amir-Hossein%20Khojir-Angasi"> Amir-Hossein Khojir-Angasi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The cache has an important role in the reduction of access delay between a processor and memory in high-performance embedded systems. In these systems, the energy consumption is one of the most important concerns, and it will become more important with smaller processor feature sizes and higher frequencies. Meanwhile, the cache system dissipates a significant portion of energy compared to the other components of a processor. There are some elements that can affect the energy consumption of the cache such as replacement policy and degree of associativity. Due to these points, it can be inferred that selecting an appropriate configuration for the cache is a crucial part of designing a system. In this paper, we investigate the effect of different cache replacement policies on both cache’s performance and energy consumption. Furthermore, the impact of different Instruction Set Architectures (ISAs) on cache’s performance and energy consumption has been investigated. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=energy%20consumption" title="energy consumption">energy consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=replacement%20policy" title=" replacement policy"> replacement policy</a>, <a href="https://publications.waset.org/abstracts/search?q=instruction%20set%20architecture" title=" instruction set architecture"> instruction set architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=multicore%20processor" title=" multicore processor"> multicore processor</a> </p> <a href="https://publications.waset.org/abstracts/122029/evaluating-the-impact-of-replacement-policies-on-the-cache-performance-and-energy-consumption-in-different-multicore-embedded-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/122029.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">154</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">302</span> Study of Heat Conduction in Multicore Chips</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=K.%20N.%20Seetharamu">K. N. Seetharamu</a>, <a href="https://publications.waset.org/abstracts/search?q=Naveen%20Teggi"> Naveen Teggi</a>, <a href="https://publications.waset.org/abstracts/search?q=Kiranakumar%20Dhavalagi"> Kiranakumar Dhavalagi</a>, <a href="https://publications.waset.org/abstracts/search?q=Narayana%20Kamath"> Narayana Kamath</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A method of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore chips. A physical model which has salient features of multicore chips is incorporated for the analysis. The model consists of active and background cell laid out in a checkered pattern, and this pattern repeats itself in each fine grain active cells. The die has three layers i) body ii) buried oxide layer iii) wiring layer, stacked one above the other with heat source placed at the interface between wiring and buried oxide layer. With this model we propose analytical method to calculate the target hotspot temperature, heat flow to top and bottom layers of the die and thermal resistance components at each granularity level, assuming appropriate values of die dimensions and parameters. Finally we attempt to find an easier method for the calculation of the target hotspot temperature using graph. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=checkered%20pattern" title="checkered pattern">checkered pattern</a>, <a href="https://publications.waset.org/abstracts/search?q=granularity%20level" title=" granularity level"> granularity level</a>, <a href="https://publications.waset.org/abstracts/search?q=heat%20conduction" title=" heat conduction"> heat conduction</a>, <a href="https://publications.waset.org/abstracts/search?q=multicore%20chips" title=" multicore chips"> multicore chips</a>, <a href="https://publications.waset.org/abstracts/search?q=target%20hotspot%20temperature" title=" target hotspot temperature"> target hotspot temperature</a> </p> <a href="https://publications.waset.org/abstracts/73987/study-of-heat-conduction-in-multicore-chips" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/73987.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">466</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">301</span> Model-Based Automotive Partitioning and Mapping for Embedded Multicore Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Robert%20H%C3%B6ttger">Robert Höttger</a>, <a href="https://publications.waset.org/abstracts/search?q=Lukas%20Krawczyk"> Lukas Krawczyk</a>, <a href="https://publications.waset.org/abstracts/search?q=Burkhard%20Igel"> Burkhard Igel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper introduces novel approaches to partitioning and mapping in terms of model-based embedded multicore system engineering and further discusses benefits, industrial relevance and features in common with existing approaches. In order to assess and evaluate results, both approaches have been applied to a real industrial application as well as to various prototypical demonstrative applications, that have been developed and implemented for different purposes. Evaluations show, that such applications improve significantly according to performance, energy efficiency, meeting timing constraints and covering maintaining issues by using the AMALTHEA platform and the implemented approaches. Further- more, the model-based design provides an open, expandable, platform independent and scalable exchange format between OEMs, suppliers and developers on different levels. Our proposed mechanisms provide meaningful multicore system utilization since load balancing by means of partitioning and mapping is effectively performed with regard to the modeled systems including hardware, software, operating system, scheduling, constraints, configuration and more data. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=partitioning" title="partitioning">partitioning</a>, <a href="https://publications.waset.org/abstracts/search?q=mapping" title=" mapping"> mapping</a>, <a href="https://publications.waset.org/abstracts/search?q=distributed%20systems" title=" distributed systems"> distributed systems</a>, <a href="https://publications.waset.org/abstracts/search?q=scheduling" title=" scheduling"> scheduling</a>, <a href="https://publications.waset.org/abstracts/search?q=embedded%20multicore%20systems" title=" embedded multicore systems"> embedded multicore systems</a>, <a href="https://publications.waset.org/abstracts/search?q=model-based" title=" model-based"> model-based</a>, <a href="https://publications.waset.org/abstracts/search?q=system%20analysis" title=" system analysis"> system analysis</a> </p> <a href="https://publications.waset.org/abstracts/20747/model-based-automotive-partitioning-and-mapping-for-embedded-multicore-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20747.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">620</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">300</span> Performance Evaluation of Parallel Surface Modeling and Generation on Actual and Virtual Multicore Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nyeng%20P.%20Gyang">Nyeng P. Gyang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Even though past, current and future trends suggest that multicore and cloud computing systems are increasingly prevalent/ubiquitous, this class of parallel systems is nonetheless underutilized, in general, and barely used for research on employing parallel Delaunay triangulation for parallel surface modeling and generation, in particular. The performances, of actual/physical and virtual/cloud multicore systems/machines, at executing various algorithms, which implement various parallelization strategies of the incremental insertion technique of the Delaunay triangulation algorithm, were evaluated. <em>T</em>-tests were run on the data collected, in order to determine whether various performance metrics differences (including execution time, speedup and efficiency) were statistically significant. Results show that the actual machine is approximately twice faster than the virtual machine at executing the same programs for the various parallelization strategies. Results, which furnish the scalability behaviors of the various parallelization strategies, also show that some of the differences between the performances of these systems, during different runs of the algorithms on the systems, were statistically significant. A few pseudo superlinear speedup results, which were computed from the raw data collected, are not true superlinear speedup values. These pseudo superlinear speedup values, which arise as a result of one way of computing speedups, disappear and give way to asymmetric speedups, which are the accurate kind of speedups that occur in the experiments performed. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cloud%20computing%20systems" title="cloud computing systems">cloud computing systems</a>, <a href="https://publications.waset.org/abstracts/search?q=multicore%20systems" title=" multicore systems"> multicore systems</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20Delaunay%20triangulation" title=" parallel Delaunay triangulation"> parallel Delaunay triangulation</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20surface%20modeling%20and%20generation" title=" parallel surface modeling and generation"> parallel surface modeling and generation</a> </p> <a href="https://publications.waset.org/abstracts/80808/performance-evaluation-of-parallel-surface-modeling-and-generation-on-actual-and-virtual-multicore-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/80808.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">206</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">299</span> Analytical Comparison of Conventional Algorithms with Vedic Algorithm for Digital Multiplier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Akhilesh%20G.%20Naik">Akhilesh G. Naik</a>, <a href="https://publications.waset.org/abstracts/search?q=Dipankar%20Pal"> Dipankar Pal</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In today’s scenario, the complexity of digital signal processing (DSP) applications and various microcontroller architectures have been increasing to such an extent that the traditional approaches to multiplier design in most processors are becoming outdated for being comparatively slow. Modern processing applications require suitable pipelined approaches, and therefore, algorithms that are friendlier with pipelined architectures. Traditional algorithms like Wallace Tree, Radix-4 Booth, Radix-8 Booth, Dadda architectures have been proven to be comparatively slow for pipelined architectures. These architectures, therefore, need to be optimized or combined with other architectures amongst them to enhance its performances and to be made suitable for pipelined hardware/architectures. Recently, Vedic algorithm mathematically has proven to be efficient by appearing to be less complex and with fewer steps for its output establishment and have assumed renewed importance. This paper describes and shows how the Vedic algorithm can be better suited for pipelined architectures and also can be combined with traditional architectures and algorithms for enhancing its ability even further. In this paper, we also established that for complex applications on DSP and other microcontroller architectures, using Vedic approach for multiplication proves to be the best available and efficient option. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Wallace%20Tree" title="Wallace Tree">Wallace Tree</a>, <a href="https://publications.waset.org/abstracts/search?q=Radix-4%20Booth" title=" Radix-4 Booth"> Radix-4 Booth</a>, <a href="https://publications.waset.org/abstracts/search?q=Radix-8%20Booth" title=" Radix-8 Booth"> Radix-8 Booth</a>, <a href="https://publications.waset.org/abstracts/search?q=Dadda" title=" Dadda"> Dadda</a>, <a href="https://publications.waset.org/abstracts/search?q=Vedic" title=" Vedic"> Vedic</a>, <a href="https://publications.waset.org/abstracts/search?q=Single-Stage%20Karatsuba%20%28SSK%29" title=" Single-Stage Karatsuba (SSK)"> Single-Stage Karatsuba (SSK)</a>, <a href="https://publications.waset.org/abstracts/search?q=Looped%20Karatsuba%20%28LK%29" title=" Looped Karatsuba (LK)"> Looped Karatsuba (LK)</a> </p> <a href="https://publications.waset.org/abstracts/86906/analytical-comparison-of-conventional-algorithms-with-vedic-algorithm-for-digital-multiplier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/86906.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">169</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">298</span> Simplifying the Migration of Architectures in Embedded Applications Introducing a Pattern Language to Support the Workforce</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Farha%20Lakhani">Farha Lakhani</a>, <a href="https://publications.waset.org/abstracts/search?q=Michael%20J.%20Pont"> Michael J. Pont</a> </p> <p class="card-text"><strong>Abstract:</strong></p> There are two main architectures used to develop software for modern embedded systems: these can be labelled as “event-triggered” (ET) and “time-triggered” (TT). The research presented in this paper is concerned with the issues involved in migration between these two architectures. Although TT architectures are widely used in safety-critical applications they are less familiar to developers of mainstream embedded systems. The research presented in this paper began from the premise that–for a broad class of systems that have been implemented using an ET architecture–migration to a TT architecture would improve reliability. It may be tempting to assume that conversion between ET and TT designs will simply involve converting all event-handling software routines into periodic activities. However, the required changes to the software architecture are, in many cases rather more profound. The main contribution of the work presented in this paper is to identify ways in which the significant effort involved in migrating between existing ET architectures and “equivalent” (and effective) TT architectures could be reduced. The research described in this paper has taken an innovative step in this regard by introducing the use of ‘Design patterns’ for this purpose for the first time. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=embedded%20applications" title="embedded applications">embedded applications</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20architectures" title=" software architectures"> software architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=reliability" title=" reliability"> reliability</a>, <a href="https://publications.waset.org/abstracts/search?q=pattern" title=" pattern"> pattern</a> </p> <a href="https://publications.waset.org/abstracts/57415/simplifying-the-migration-of-architectures-in-embedded-applications-introducing-a-pattern-language-to-support-the-workforce" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/57415.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">329</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">297</span> Convolutional Neural Networks Architecture Analysis for Image Captioning</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jun%20Seung%20Woo">Jun Seung Woo</a>, <a href="https://publications.waset.org/abstracts/search?q=Shin%20Dong%20Ho"> Shin Dong Ho</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Image Captioning models with Attention technology have developed significantly compared to previous models, but it is still unsatisfactory in recognizing images. We perform an extensive search over seven interesting Convolutional Neural Networks(CNN) architectures to analyze the behavior of different models for image captioning. We compared seven different CNN Architectures, according to batch size, using on public benchmarks: MS-COCO datasets. In our experimental results, DenseNet and InceptionV3 got about 14% loss and about 160sec training time per epoch. It was the most satisfactory result among the seven CNN architectures after training 50 epochs on GPU. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=deep%20learning" title="deep learning">deep learning</a>, <a href="https://publications.waset.org/abstracts/search?q=image%20captioning" title=" image captioning"> image captioning</a>, <a href="https://publications.waset.org/abstracts/search?q=CNN%20architectures" title=" CNN architectures"> CNN architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=densenet" title=" densenet"> densenet</a>, <a href="https://publications.waset.org/abstracts/search?q=inceptionV3" title=" inceptionV3"> inceptionV3</a> </p> <a href="https://publications.waset.org/abstracts/148886/convolutional-neural-networks-architecture-analysis-for-image-captioning" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/148886.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">132</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">296</span> Centralizing the Teaching Process in Intelligent Tutoring System Architectures</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nikolaj%20Troels%20Graf%20Von%20Malotky">Nikolaj Troels Graf Von Malotky</a>, <a href="https://publications.waset.org/abstracts/search?q=Robin%20Nicolay"> Robin Nicolay</a>, <a href="https://publications.waset.org/abstracts/search?q=Alke%20Martens"> Alke Martens</a> </p> <p class="card-text"><strong>Abstract:</strong></p> There exist a plethora of architectures for ITSs (Intelligent Tutoring Systems). A thorough analysis and comparison of the architectures revealed, that in most cases the architecture extensions are evolutionary grown, reflecting state of the art trends of each decade. However, from the perspective of software engineering, the main aspect of an ITS has not been reflected in any of these architectures, yet. From the perspective of cognitive research, the construction of the teaching process is what makes an ITS 'intelligent' regarding the spectrum of interaction with the students. Thus, in our approach, we focus on a behavior based architecture, which is based on the main teaching processes. To create a new general architecture for ITS, we have to define the prerequisites. This paper analyzes the current state of the existing architectures and derives rules for the behavior of ITS. It is presenting a teaching process for ITSs to be used together with the architecture. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=intelligent%20tutoring" title="intelligent tutoring">intelligent tutoring</a>, <a href="https://publications.waset.org/abstracts/search?q=ITS" title=" ITS"> ITS</a>, <a href="https://publications.waset.org/abstracts/search?q=tutoring%20process" title=" tutoring process"> tutoring process</a>, <a href="https://publications.waset.org/abstracts/search?q=system%20architecture" title=" system architecture"> system architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=interaction%20process" title=" interaction process"> interaction process</a> </p> <a href="https://publications.waset.org/abstracts/67815/centralizing-the-teaching-process-in-intelligent-tutoring-system-architectures" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/67815.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">384</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">295</span> Automatic Tuning for a Systemic Model of Banking Originated Losses (SYMBOL) Tool on Multicore</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ronal%20Muresano">Ronal Muresano</a>, <a href="https://publications.waset.org/abstracts/search?q=Andrea%20Pagano"> Andrea Pagano</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays, the mathematical/statistical applications are developed with more complexity and accuracy. However, these precisions and complexities have brought as result that applications need more computational power in order to be executed faster. In this sense, the multicore environments are playing an important role to improve and to optimize the execution time of these applications. These environments allow us the inclusion of more parallelism inside the node. However, to take advantage of this parallelism is not an easy task, because we have to deal with some problems such as: cores communications, data locality, memory sizes (cache and RAM), synchronizations, data dependencies on the model, etc. These issues are becoming more important when we wish to improve the application’s performance and scalability. Hence, this paper describes an optimization method developed for Systemic Model of Banking Originated Losses (SYMBOL) tool developed by the European Commission, which is based on analyzing the application's weakness in order to exploit the advantages of the multicore. All these improvements are done in an automatic and transparent manner with the aim of improving the performance metrics of our tool. Finally, experimental evaluations show the effectiveness of our new optimized version, in which we have achieved a considerable improvement on the execution time. The time has been reduced around 96% for the best case tested, between the original serial version and the automatic parallel version. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=algorithm%20optimization" title="algorithm optimization">algorithm optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=bank%20failures" title=" bank failures"> bank failures</a>, <a href="https://publications.waset.org/abstracts/search?q=OpenMP" title=" OpenMP"> OpenMP</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20techniques" title=" parallel techniques"> parallel techniques</a>, <a href="https://publications.waset.org/abstracts/search?q=statistical%20tool" title=" statistical tool"> statistical tool</a> </p> <a href="https://publications.waset.org/abstracts/14489/automatic-tuning-for-a-systemic-model-of-banking-originated-losses-symbol-tool-on-multicore" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/14489.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">369</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">294</span> Normalized Enterprises Architectures: Portugal's Public Procurement System Application</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tiago%20Sampaio">Tiago Sampaio</a>, <a href="https://publications.waset.org/abstracts/search?q=Andr%C3%A9%20Vasconcelos"> André Vasconcelos</a>, <a href="https://publications.waset.org/abstracts/search?q=Bruno%20Fragoso"> Bruno Fragoso</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Normalized Systems Theory, which is designed to be applied to software architectures, provides a set of theorems, elements and rules, with the purpose of enabling evolution in Information Systems, as well as ensuring that they are ready for change. In order to make that possible, this work’s solution is to apply the Normalized Systems Theory to the domain of enterprise architectures, using Archimate. This application is achieved through the adaptation of the elements of this theory, making them artifacts of the modeling language. The theorems are applied through the identification of the viewpoints to be used in the architectures, as well as the transformation of the theory’s encapsulation rules into architectural rules. This way, it is possible to create normalized enterprise architectures, thus fulfilling the needs and requirements of the business. This solution was demonstrated using the Portuguese Public Procurement System. The Portuguese government aims to make this system as fair as possible, allowing every organization to have the same business opportunities. The aim is for every economic operator to have access to all public tenders, which are published in any of the 6 existing platforms, independently of where they are registered. In order to make this possible, we applied our solution to the construction of two different architectures, which are able of fulfilling the requirements of the Portuguese government. One of those architectures, TO-BE A, has a Message Broker that performs the communication between the platforms. The other, TO-BE B, represents the scenario in which the platforms communicate with each other directly. Apart from these 2 architectures, we also represent the AS-IS architecture that demonstrates the current behavior of the Public Procurement Systems. Our evaluation is based on a comparison between the AS-IS and the TO-BE architectures, regarding the fulfillment of the rules and theorems of the Normalized Systems Theory and some quality metrics. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=archimate" title="archimate">archimate</a>, <a href="https://publications.waset.org/abstracts/search?q=architecture" title=" architecture"> architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=broker" title=" broker"> broker</a>, <a href="https://publications.waset.org/abstracts/search?q=enterprise" title=" enterprise"> enterprise</a>, <a href="https://publications.waset.org/abstracts/search?q=evolvable%20systems" title=" evolvable systems"> evolvable systems</a>, <a href="https://publications.waset.org/abstracts/search?q=interoperability" title=" interoperability"> interoperability</a>, <a href="https://publications.waset.org/abstracts/search?q=normalized%20architectures" title=" normalized architectures"> normalized architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=normalized%20systems" title=" normalized systems"> normalized systems</a>, <a href="https://publications.waset.org/abstracts/search?q=normalized%20systems%20theory" title=" normalized systems theory"> normalized systems theory</a>, <a href="https://publications.waset.org/abstracts/search?q=platforms" title=" platforms"> platforms</a> </p> <a href="https://publications.waset.org/abstracts/60170/normalized-enterprises-architectures-portugals-public-procurement-system-application" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/60170.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">357</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">293</span> Efficient DCT Architectures</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mr.%20P.%20Suryaprasad">Mr. P. Suryaprasad</a>, <a href="https://publications.waset.org/abstracts/search?q=R.%20Lalitha"> R. Lalitha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents an efficient area and delay architectures for the implementation of one dimensional and two dimensional discrete cosine transform (DCT). These are supported to different lengths (4, 8, 16, and 32). DCT blocks are used in the different video coding standards for the image compression. The 2D- DCT calculation is made using the 2D-DCT separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Based on the existing 1D-DCT architecture two different types of 2D-DCT architectures, folded and parallel types are implemented. Both of these two structures use the same transpose buffer. Proposed transpose buffer occupies less area and high speed than existing transpose buffer. Hence the area, low power and delay of both the 2D-DCT architectures are reduced. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=transposition%20buffer" title="transposition buffer">transposition buffer</a>, <a href="https://publications.waset.org/abstracts/search?q=video%20compression" title=" video compression"> video compression</a>, <a href="https://publications.waset.org/abstracts/search?q=discrete%20cosine%20transform" title=" discrete cosine transform"> discrete cosine transform</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20efficiency%20video%20coding" title=" high efficiency video coding"> high efficiency video coding</a>, <a href="https://publications.waset.org/abstracts/search?q=two%20dimensional%20picture" title=" two dimensional picture"> two dimensional picture</a> </p> <a href="https://publications.waset.org/abstracts/33624/efficient-dct-architectures" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/33624.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">521</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">292</span> NFResNet: Multi-Scale and U-Shaped Networks for Deblurring</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tanish%20Mittal">Tanish Mittal</a>, <a href="https://publications.waset.org/abstracts/search?q=Preyansh%20Agrawal"> Preyansh Agrawal</a>, <a href="https://publications.waset.org/abstracts/search?q=Esha%20Pahwa"> Esha Pahwa</a>, <a href="https://publications.waset.org/abstracts/search?q=Aarya%20Makwana"> Aarya Makwana</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Multi-Scale and U-shaped Networks are widely used in various image restoration problems, including deblurring. Keeping in mind the wide range of applications, we present a comparison of these architectures and their effects on image deblurring. We also introduce a new block called as NFResblock. It consists of a Fast Fourier Transformation layer and a series of modified Non-Linear Activation Free Blocks. Based on these architectures and additions, we introduce NFResnet and NFResnet+, which are modified multi-scale and U-Net architectures, respectively. We also use three differ-ent loss functions to train these architectures: Charbonnier Loss, Edge Loss, and Frequency Reconstruction Loss. Extensive experiments on the Deep Video Deblurring dataset, along with ablation studies for each component, have been presented in this paper. The proposed architectures achieve a considerable increase in Peak Signal to Noise (PSNR) ratio and Structural Similarity Index (SSIM) value. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=multi-scale" title="multi-scale">multi-scale</a>, <a href="https://publications.waset.org/abstracts/search?q=Unet" title=" Unet"> Unet</a>, <a href="https://publications.waset.org/abstracts/search?q=deblurring" title=" deblurring"> deblurring</a>, <a href="https://publications.waset.org/abstracts/search?q=FFT" title=" FFT"> FFT</a>, <a href="https://publications.waset.org/abstracts/search?q=resblock" title=" resblock"> resblock</a>, <a href="https://publications.waset.org/abstracts/search?q=NAF-block" title=" NAF-block"> NAF-block</a>, <a href="https://publications.waset.org/abstracts/search?q=nfresnet" title=" nfresnet"> nfresnet</a>, <a href="https://publications.waset.org/abstracts/search?q=charbonnier" title=" charbonnier"> charbonnier</a>, <a href="https://publications.waset.org/abstracts/search?q=edge" title=" edge"> edge</a>, <a href="https://publications.waset.org/abstracts/search?q=frequency%20reconstruction" title=" frequency reconstruction"> frequency reconstruction</a> </p> <a href="https://publications.waset.org/abstracts/159306/nfresnet-multi-scale-and-u-shaped-networks-for-deblurring" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/159306.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">136</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">291</span> A Unified Approach for Naval Telecommunication Architectures</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Y.%20Lacroix">Y. Lacroix</a>, <a href="https://publications.waset.org/abstracts/search?q=J.-F.%20Malbranque"> J.-F. Malbranque</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We present a chronological evolution for naval telecommunication networks. We distinguish periods: with or without multiplexers, with switch systems, with federative systems, with medium switching, and with medium switching with wireless networks. This highlights the introduction of new layers and technology in the architecture. These architectures are presented using layer models of transmission, in a unified way, which enables us to integrate pre-existing models. A ship of a naval fleet has internal communications (i.e. applications' networks of the edge) and external communications (i.e. the use of the means of transmission between edges). We propose architectures, deduced from the layer model, which are the point of convergence between the networks on board and the HF, UHF radio, and satellite resources. This modelling allows to consider end-to-end naval communications, and in a more global way, that is from the user on board towards the user on shore, including transmission and networks on the shore side. The new architectures need take care of quality of services for end-to-end communications, the more remote control develops a lot and will do so in the future. Naval telecommunications will be more and more complex and will use more and more advanced technologies, it will thus be necessary to establish clear global communication schemes to grant consistency of the architectures. Our latest model has been implemented in a military naval situation, and serves as the basic architecture for the RIFAN2 network. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=equilibrium%20beach%20profile" title="equilibrium beach profile">equilibrium beach profile</a>, <a href="https://publications.waset.org/abstracts/search?q=eastern%20tombolo%20of%20Giens" title=" eastern tombolo of Giens"> eastern tombolo of Giens</a>, <a href="https://publications.waset.org/abstracts/search?q=potential%20function" title=" potential function"> potential function</a>, <a href="https://publications.waset.org/abstracts/search?q=erosion" title=" erosion"> erosion</a> </p> <a href="https://publications.waset.org/abstracts/68121/a-unified-approach-for-naval-telecommunication-architectures" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68121.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">291</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">290</span> Design of a New Architecture of IDS Called BiIDS (IDS Based on Two Principles of Detection)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yousef%20Farhaoui">Yousef Farhaoui</a> </p> <p class="card-text"><strong>Abstract:</strong></p> An IDS is a tool which is used to improve the level of security.In this paper we present different architectures of IDS. We will also discuss measures that define the effectiveness of IDS and the very recent works of standardization and homogenization of IDS. At the end, we propose a new model of IDS called BiIDS (IDS Based on the two principles of detection). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=intrusion%20detection" title="intrusion detection">intrusion detection</a>, <a href="https://publications.waset.org/abstracts/search?q=architectures" title=" architectures"> architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=characteristic" title=" characteristic"> characteristic</a>, <a href="https://publications.waset.org/abstracts/search?q=tools" title=" tools"> tools</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a> </p> <a href="https://publications.waset.org/abstracts/12298/design-of-a-new-architecture-of-ids-called-biids-ids-based-on-two-principles-of-detection" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/12298.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">462</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">289</span> Multi-Criteria Evaluation of IDS Architectures in Cloud Computing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Elmahdi%20Khalil">Elmahdi Khalil</a>, <a href="https://publications.waset.org/abstracts/search?q=Saad%20Enniari"> Saad Enniari</a>, <a href="https://publications.waset.org/abstracts/search?q=Mostapha%20Zbakh"> Mostapha Zbakh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Cloud computing promises to increase innovation and the velocity with witch applications are deployed, all while helping any enterprise meet most IT service needs at a lower total cost of ownership and higher return investment. As the march of cloud continues, it brings both new opportunities and new security challenges. To take advantages of those opportunities while minimizing risks, we think that Intrusion Detection Systems (IDS) integrated in the cloud is one of the best existing solutions nowadays in the field. The concept of intrusion detection was known since past and was first proposed by a well-known researcher named Anderson in 1980's. Since that time IDS's are evolving. Although, several efforts has been made in the area of Intrusion Detection systems for cloud computing environment, many attacks still prevail. Therefore, the work presented in this paper proposes a multi criteria analysis and a comparative study between several IDS architectures designated to work in a cloud computing environments. To achieve this objective, in the first place we will search in the state of the art of several consistent IDS architectures designed to work in a cloud environment. Whereas, in a second step we will establish the criteria that will be useful for the evaluation of architectures. Later, using the approach of multi criteria decision analysis Mac Beth (Measuring Attractiveness by a Categorical Based Evaluation Technique we will evaluate the criteria and assign to each one the appropriate weight according to their importance in the field of IDS architectures in cloud computing. The last step is to evaluate architectures against the criteria and collecting results of the model constructed in the previous steps. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cloud%20computing" title="cloud computing">cloud computing</a>, <a href="https://publications.waset.org/abstracts/search?q=cloud%20security" title=" cloud security"> cloud security</a>, <a href="https://publications.waset.org/abstracts/search?q=intrusion%20detection%2Fprevention%20system" title=" intrusion detection/prevention system"> intrusion detection/prevention system</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-criteria%20decision%20analysis" title=" multi-criteria decision analysis"> multi-criteria decision analysis</a> </p> <a href="https://publications.waset.org/abstracts/21704/multi-criteria-evaluation-of-ids-architectures-in-cloud-computing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21704.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">471</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">288</span> Quantitative Analysis of Multiprocessor Architectures for Radar Signal Processing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Deepak%20Kumar">Deepak Kumar</a>, <a href="https://publications.waset.org/abstracts/search?q=Debasish%20Deb"> Debasish Deb</a>, <a href="https://publications.waset.org/abstracts/search?q=Reena%20Mamgain"> Reena Mamgain</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Radar signal processing requires high number crunching capability. Most often this is achieved using multiprocessor platform. Though multiprocessor platform provides the capability of meeting the real time computational challenges, the architecture of the same along with mapping of the algorithm on the architecture plays a vital role in efficiently using the platform. Towards this, along with standard performance metrics, few additional metrics are defined which helps in evaluating the multiprocessor platform along with the algorithm mapping. A generic multiprocessor architecture can not suit all the processing requirements. Depending on the system requirement and type of algorithms used, the most suitable architecture for the given problem is decided. In the paper, we study different architectures and quantify the different performance metrics which enables comparison of different architectures for their merit. We also carried out case study of different architectures and their efficiency depending on parallelism exploited on algorithm or data or both. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=radar%20signal%20processing" title="radar signal processing">radar signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=multiprocessor%20architecture" title=" multiprocessor architecture"> multiprocessor architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=efficiency" title=" efficiency"> efficiency</a>, <a href="https://publications.waset.org/abstracts/search?q=load%20imbalance" title=" load imbalance"> load imbalance</a>, <a href="https://publications.waset.org/abstracts/search?q=buffer%20requirement" title=" buffer requirement"> buffer requirement</a>, <a href="https://publications.waset.org/abstracts/search?q=pipeline" title=" pipeline"> pipeline</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel" title=" parallel"> parallel</a>, <a href="https://publications.waset.org/abstracts/search?q=hybrid" title=" hybrid"> hybrid</a>, <a href="https://publications.waset.org/abstracts/search?q=cluster%20of%20processors%20%28COPs%29" title=" cluster of processors (COPs)"> cluster of processors (COPs)</a> </p> <a href="https://publications.waset.org/abstracts/21687/quantitative-analysis-of-multiprocessor-architectures-for-radar-signal-processing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21687.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">412</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">287</span> A Comparison of Convolutional Neural Network Architectures for the Classification of Alzheimer’s Disease Patients Using MRI Scans</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tomas%20Premoli">Tomas Premoli</a>, <a href="https://publications.waset.org/abstracts/search?q=Sareh%20Rowlands"> Sareh Rowlands</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this study, we investigate the impact of various convolutional neural network (CNN) architectures on the accuracy of diagnosing Alzheimer’s disease (AD) using patient MRI scans. Alzheimer’s disease is a debilitating neurodegenerative disorder that affects millions worldwide. Early, accurate, and non-invasive diagnostic methods are required for providing optimal care and symptom management. Deep learning techniques, particularly CNNs, have shown great promise in enhancing this diagnostic process. We aim to contribute to the ongoing research in this field by comparing the effectiveness of different CNN architectures and providing insights for future studies. Our methodology involved preprocessing MRI data, implementing multiple CNN architectures, and evaluating the performance of each model. We employed intensity normalization, linear registration, and skull stripping for our preprocessing. The selected architectures included VGG, ResNet, and DenseNet models, all implemented using the Keras library. We employed transfer learning and trained models from scratch to compare their effectiveness. Our findings demonstrated significant differences in performance among the tested architectures, with DenseNet201 achieving the highest accuracy of 86.4%. Transfer learning proved to be helpful in improving model performance. We also identified potential areas for future research, such as experimenting with other architectures, optimizing hyperparameters, and employing fine-tuning strategies. By providing a comprehensive analysis of the selected CNN architectures, we offer a solid foundation for future research in Alzheimer’s disease diagnosis using deep learning techniques. Our study highlights the potential of CNNs as a valuable diagnostic tool and emphasizes the importance of ongoing research to develop more accurate and effective models. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Alzheimer%E2%80%99s%20disease" title="Alzheimer’s disease">Alzheimer’s disease</a>, <a href="https://publications.waset.org/abstracts/search?q=convolutional%20neural%20networks" title=" convolutional neural networks"> convolutional neural networks</a>, <a href="https://publications.waset.org/abstracts/search?q=deep%20learning" title=" deep learning"> deep learning</a>, <a href="https://publications.waset.org/abstracts/search?q=medical%20imaging" title=" medical imaging"> medical imaging</a>, <a href="https://publications.waset.org/abstracts/search?q=MRI" title=" MRI"> MRI</a> </p> <a href="https://publications.waset.org/abstracts/176580/a-comparison-of-convolutional-neural-network-architectures-for-the-classification-of-alzheimers-disease-patients-using-mri-scans" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/176580.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">73</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">286</span> Securing Web Servers by the Intrusion Detection System (IDS)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yousef%20Farhaoui">Yousef Farhaoui </a> </p> <p class="card-text"><strong>Abstract:</strong></p> An IDS is a tool which is used to improve the level of security. We present in this paper different architectures of IDS. We will also discuss measures that define the effectiveness of IDS and the very recent works of standardization and homogenization of IDS. At the end, we propose a new model of IDS called BiIDS (IDS Based on the two principles of detection) for securing web servers and applications by the Intrusion Detection System (IDS). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=intrusion%20detection" title="intrusion detection">intrusion detection</a>, <a href="https://publications.waset.org/abstracts/search?q=architectures" title=" architectures"> architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=characteristic" title=" characteristic"> characteristic</a>, <a href="https://publications.waset.org/abstracts/search?q=tools" title=" tools"> tools</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=web%20server" title=" web server"> web server</a> </p> <a href="https://publications.waset.org/abstracts/13346/securing-web-servers-by-the-intrusion-detection-system-ids" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/13346.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">418</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">285</span> The Impact of Introspective Models on Software Engineering</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rajneekant%20Bachan">Rajneekant Bachan</a>, <a href="https://publications.waset.org/abstracts/search?q=Dhanush%20Vijay"> Dhanush Vijay</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The visualization of operating systems has refined the Turing machine, and current trends suggest that the emulation of 32 bit architectures will soon emerge. After years of technical research into Web services, we demonstrate the synthesis of gigabit switches, which embodies the robust principles of theory. Loam, our new algorithm for forward-error correction, is the solution to all of these challenges. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=software%20engineering" title="software engineering">software engineering</a>, <a href="https://publications.waset.org/abstracts/search?q=architectures" title=" architectures"> architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=introspective%20models" title=" introspective models"> introspective models</a>, <a href="https://publications.waset.org/abstracts/search?q=operating%20systems" title=" operating systems"> operating systems</a> </p> <a href="https://publications.waset.org/abstracts/26309/the-impact-of-introspective-models-on-software-engineering" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/26309.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">538</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">284</span> Comparative Performance Analysis of Fiber Delay Line Based Buffer Architectures for Contention Resolution in Optical WDM Networks</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Manoj%20Kumar%20Dutta">Manoj Kumar Dutta</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Wavelength division multiplexing (WDM) technology is the most promising technology for the proper utilization of huge raw bandwidth provided by an optical fiber. One of the key problems in implementing the all-optical WDM network is the packet contention. This problem can be solved by several different techniques. In time domain approach the packet contention can be reduced by incorporating fiber delay lines (FDLs) as optical buffer in the switch architecture. Different types of buffering architectures are reported in literatures. In the present paper a comparative performance analysis of three most popular FDL architectures are presented in order to obtain the best contention resolution performance. The analysis is further extended to consider the effect of different fiber non-linearities on the network performance. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=WDM%20network" title="WDM network">WDM network</a>, <a href="https://publications.waset.org/abstracts/search?q=contention%20resolution" title=" contention resolution"> contention resolution</a>, <a href="https://publications.waset.org/abstracts/search?q=optical%20buffering" title=" optical buffering"> optical buffering</a>, <a href="https://publications.waset.org/abstracts/search?q=non-linearity" title=" non-linearity"> non-linearity</a>, <a href="https://publications.waset.org/abstracts/search?q=throughput" title=" throughput"> throughput</a> </p> <a href="https://publications.waset.org/abstracts/38257/comparative-performance-analysis-of-fiber-delay-line-based-buffer-architectures-for-contention-resolution-in-optical-wdm-networks" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38257.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">451</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">283</span> Proposing an Architecture for Drug Response Prediction by Integrating Multiomics Data and Utilizing Graph Transformers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nishank%20Raisinghani">Nishank Raisinghani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Efficiently predicting drug response remains a challenge in the realm of drug discovery. To address this issue, we propose four model architectures that combine graphical representation with varying positions of multiheaded self-attention mechanisms. By leveraging two types of multi-omics data, transcriptomics and genomics, we create a comprehensive representation of target cells and enable drug response prediction in precision medicine. A majority of our architectures utilize multiple transformer models, one with a graph attention mechanism and the other with a multiheaded self-attention mechanism, to generate latent representations of both drug and omics data, respectively. Our model architectures apply an attention mechanism to both drug and multiomics data, with the goal of procuring more comprehensive latent representations. The latent representations are then concatenated and input into a fully connected network to predict the IC-50 score, a measure of cell drug response. We experiment with all four of these architectures and extract results from all of them. Our study greatly contributes to the future of drug discovery and precision medicine by looking to optimize the time and accuracy of drug response prediction. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=drug%20discovery" title="drug discovery">drug discovery</a>, <a href="https://publications.waset.org/abstracts/search?q=transformers" title=" transformers"> transformers</a>, <a href="https://publications.waset.org/abstracts/search?q=graph%20neural%20networks" title=" graph neural networks"> graph neural networks</a>, <a href="https://publications.waset.org/abstracts/search?q=multiomics" title=" multiomics"> multiomics</a> </p> <a href="https://publications.waset.org/abstracts/169926/proposing-an-architecture-for-drug-response-prediction-by-integrating-multiomics-data-and-utilizing-graph-transformers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/169926.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">153</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">282</span> 6G: Emerging Architectures, Technologies and Challenges</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdulrahman%20Yarali">Abdulrahman Yarali</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The advancement of technology never stops because the demands for improved internet and communication connectivity are increasing. Just as 5G networks are rolling out, the world has begun to talk about the sixth-generation networks (6G). The semantics of 6G are more or less the same as 5G networks because they strive to boost speeds, machine-to-machine (M2M) communication, and latency reduction. However, some of the distinctive focuses of 6G include the optimization of networks of machines through super speeds and innovative features. This paper discusses many aspects of the technologies, architectures, challenges, and opportunities of 6G wireless communication systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=6G" title="6G">6G</a>, <a href="https://publications.waset.org/abstracts/search?q=characteristics" title=" characteristics"> characteristics</a>, <a href="https://publications.waset.org/abstracts/search?q=infrastructures" title=" infrastructures"> infrastructures</a>, <a href="https://publications.waset.org/abstracts/search?q=technologies" title=" technologies"> technologies</a>, <a href="https://publications.waset.org/abstracts/search?q=AI" title=" AI"> AI</a>, <a href="https://publications.waset.org/abstracts/search?q=ML" title=" ML"> ML</a>, <a href="https://publications.waset.org/abstracts/search?q=IoT" title=" IoT"> IoT</a>, <a href="https://publications.waset.org/abstracts/search?q=applications" title=" applications"> applications</a> </p> <a href="https://publications.waset.org/abstracts/191246/6g-emerging-architectures-technologies-and-challenges" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/191246.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">25</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">281</span> A Survey of Baseband Architecture for Software Defined Radio</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=M.%20A.%20Fodha">M. A. Fodha</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Benfradj"> H. Benfradj</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Ghazel"> A. Ghazel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed. The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=multi-core%20architectures" title="multi-core architectures">multi-core architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20architectures" title=" reconfigurable architectures"> reconfigurable architectures</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20defined%20radio" title=" software defined radio"> software defined radio</a>, <a href="https://publications.waset.org/abstracts/search?q=baseband%20processor" title=" baseband processor"> baseband processor</a> </p> <a href="https://publications.waset.org/abstracts/18695/a-survey-of-baseband-architecture-for-software-defined-radio" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/18695.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">475</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">280</span> Study on Energy Performance Comparison of Information Centric Network Based on Difference of Network Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Takumi%20Shindo">Takumi Shindo</a>, <a href="https://publications.waset.org/abstracts/search?q=Koji%20Okamura"> Koji Okamura</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The first generation of the wide area network was circuit centric network. How the optimal circuit can be signed was the most important issue to get the best performance. This architecture had succeeded for line based telephone system. The second generation was host centric network and Internet based on this architecture has very succeeded world widely. And Internet became as new social infrastructure. Currently the architecture of the network is based on the location of the information. This future network is called Information centric network (ICN). The information-centric network (ICN) has being researched by many projects and different architectures for implementation of ICN have been proposed. The goal of this study is to compare performances of those ICN architectures. In this paper, the authors propose general ICN model which can represent two typical ICN architectures and compare communication performances using request routing. Finally, simulation results are shown. Also, we assume that this network architecture should be adapt to energy on-demand routing. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ICN" title="ICN">ICN</a>, <a href="https://publications.waset.org/abstracts/search?q=information%20centric%20network" title=" information centric network"> information centric network</a>, <a href="https://publications.waset.org/abstracts/search?q=CCN" title=" CCN"> CCN</a>, <a href="https://publications.waset.org/abstracts/search?q=energy" title=" energy"> energy</a> </p> <a href="https://publications.waset.org/abstracts/68439/study-on-energy-performance-comparison-of-information-centric-network-based-on-difference-of-network-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68439.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">337</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">279</span> High Performance Computing and Big Data Analytics</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Branci%20Sarra">Branci Sarra</a>, <a href="https://publications.waset.org/abstracts/search?q=Branci%20Saadia"> Branci Saadia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Because of the multiplied data growth, many computer science tools have been developed to process and analyze these Big Data. High-performance computing architectures have been designed to meet the treatment needs of Big Data (view transaction processing standpoint, strategic, and tactical analytics). The purpose of this article is to provide a historical and global perspective on the recent trend of high-performance computing architectures especially what has a relation with Analytics and Data Mining. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=high%20performance%20computing" title="high performance computing">high performance computing</a>, <a href="https://publications.waset.org/abstracts/search?q=HPC" title=" HPC"> HPC</a>, <a href="https://publications.waset.org/abstracts/search?q=big%20data" title=" big data"> big data</a>, <a href="https://publications.waset.org/abstracts/search?q=data%20analysis" title=" data analysis"> data analysis</a> </p> <a href="https://publications.waset.org/abstracts/15079/high-performance-computing-and-big-data-analytics" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/15079.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">520</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">278</span> Heuristic of Style Transfer for Real-Time Detection or Classification of Weather Conditions from Camera Images</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hamed%20Ouattara">Hamed Ouattara</a>, <a href="https://publications.waset.org/abstracts/search?q=Pierre%20Duthon"> Pierre Duthon</a>, <a href="https://publications.waset.org/abstracts/search?q=Fr%C3%A9d%C3%A9ric%20Bernardin"> Frédéric Bernardin</a>, <a href="https://publications.waset.org/abstracts/search?q=Omar%20Ait%20Aider"> Omar Ait Aider</a>, <a href="https://publications.waset.org/abstracts/search?q=Pascal%20Salmane"> Pascal Salmane</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this article, we present three neural network architectures for real-time classification of weather conditions (sunny, rainy, snowy, foggy) from images. Inspired by recent advances in style transfer, two of these architectures -Truncated ResNet50 and Truncated ResNet50 with Gram Matrix and Attention- surpass the state of the art and demonstrate re-markable generalization capability on several public databases, including Kaggle (2000 images), Kaggle 850 images, MWI (1996 images) [1], and Image2Weather [2]. Although developed for weather detection, these architectures are also suitable for other appearance-based classification tasks, such as animal species recognition, texture classification, disease detection in medical images, and industrial defect identification. We illustrate these applications in the section “Applications of Our Models to Other Tasks” with the “SIIM-ISIC Melanoma Classification Challenge 2020” [3]. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=weather%20simulation" title="weather simulation">weather simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=weather%20measurement" title=" weather measurement"> weather measurement</a>, <a href="https://publications.waset.org/abstracts/search?q=weather%20classification" title=" weather classification"> weather classification</a>, <a href="https://publications.waset.org/abstracts/search?q=weather%20detection" title=" weather detection"> weather detection</a>, <a href="https://publications.waset.org/abstracts/search?q=style%20transfer" title=" style transfer"> style transfer</a>, <a href="https://publications.waset.org/abstracts/search?q=Pix2Pix" title=" Pix2Pix"> Pix2Pix</a>, <a href="https://publications.waset.org/abstracts/search?q=CycleGAN" title=" CycleGAN"> CycleGAN</a>, <a href="https://publications.waset.org/abstracts/search?q=CUT" title=" CUT"> CUT</a>, <a href="https://publications.waset.org/abstracts/search?q=neural%20style%20transfer" title=" neural style transfer"> neural style transfer</a> </p> <a href="https://publications.waset.org/abstracts/194615/heuristic-of-style-transfer-for-real-time-detection-or-classification-of-weather-conditions-from-camera-images" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/194615.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">0</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">277</span> A Multi-criteria Decision Support System for Migrating Legacies into Open Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nasser%20Almonawer">Nasser Almonawer</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Timely reaction to an evolving global business environment and volatile market conditions necessitates system and process flexibility, which in turn demands agile and adaptable architecture and a steady infusion of affordable new technologies. On the contrary, a large number of organizations utilize systems characterized by inflexible and obsolete legacy architectures. To effectively respond to the dynamic contemporary business environments, such architectures must be migrated to robust and modular open architectures. To this end, this paper proposes an integrated decision support system for a seamless migration to open systems. The proposed decision support system (DSS) integrates three well-established quantitative and qualitative decision-making models—namely, the Delphi method, Analytic Hierarchy Process (AHP) and Goal Programming (GP) to (1) assess risks and establish evaluation criteria; (2) formulate migration strategy and rank candidate systems; and (3) allocate resources among the selected systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=decision%20support%20systems" title="decision support systems">decision support systems</a>, <a href="https://publications.waset.org/abstracts/search?q=open%20systems%20architecture" title=" open systems architecture"> open systems architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=analytic%20hierarchy%20process%20%28AHP%29" title=" analytic hierarchy process (AHP)"> analytic hierarchy process (AHP)</a>, <a href="https://publications.waset.org/abstracts/search?q=goal%20programming%20%28GP%29" title=" goal programming (GP)"> goal programming (GP)</a>, <a href="https://publications.waset.org/abstracts/search?q=delphi%20method" title=" delphi method"> delphi method</a> </p> <a href="https://publications.waset.org/abstracts/187670/a-multi-criteria-decision-support-system-for-migrating-legacies-into-open-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/187670.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">47</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">276</span> Big Data: Concepts, Technologies and Applications in the Public Sector</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.%20Alexandru">A. Alexandru</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20A.%20Alexandru"> C. A. Alexandru</a>, <a href="https://publications.waset.org/abstracts/search?q=D.%20Coardos"> D. Coardos</a>, <a href="https://publications.waset.org/abstracts/search?q=E.%20Tudora"> E. Tudora</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Big Data (BD) is associated with a new generation of technologies and architectures which can harness the value of extremely large volumes of very varied data through real time processing and analysis. It involves changes in (1) data types, (2) accumulation speed, and (3) data volume. This paper presents the main concepts related to the BD paradigm, and introduces architectures and technologies for BD and BD sets. The integration of BD with the Hadoop Framework is also underlined. BD has attracted a lot of attention in the public sector due to the newly emerging technologies that allow the availability of network access. The volume of different types of data has exponentially increased. Some applications of BD in the public sector in Romania are briefly presented. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=big%20data" title="big data">big data</a>, <a href="https://publications.waset.org/abstracts/search?q=big%20data%20analytics" title=" big data analytics"> big data analytics</a>, <a href="https://publications.waset.org/abstracts/search?q=Hadoop" title=" Hadoop"> Hadoop</a>, <a href="https://publications.waset.org/abstracts/search?q=cloud" title=" cloud"> cloud</a> </p> <a href="https://publications.waset.org/abstracts/52265/big-data-concepts-technologies-and-applications-in-the-public-sector" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/52265.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">310</span> </span> </div> </div> <ul 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