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cache</title> <meta name="description" content="Search results for: dram cache"> <meta name="keywords" content="dram cache"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none navbar-toggler ml-auto" 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id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="dram cache"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 28</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: dram cache</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">28</span> Formal Verification of Cache System Using a Novel Cache Memory Model</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Guowei%20Hou">Guowei Hou</a>, <a href="https://publications.waset.org/abstracts/search?q=Lixin%20Yu"> Lixin Yu</a>, <a href="https://publications.waset.org/abstracts/search?q=Wei%20Zhuang"> Wei Zhuang</a>, <a href="https://publications.waset.org/abstracts/search?q=Hui%20Qin"> Hui Qin</a>, <a href="https://publications.waset.org/abstracts/search?q=Xue%20Yang"> Xue Yang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient. As cache plays a vital role in the design of System on Chip (SoC), and cache with Memory Management Unit (MMU) and cache memory unit makes the state space too large for simulation to verify, then a formal verification is presented for such system design. In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called “exhaustive search model” is proposed. Instead of using large size ram to denote the whole cache memory, exhaustive search model employs just two cache blocks. For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism. At last, the novel model is employed to the verification of a cache which is module of a custom-built SoC system that has been applied in practical, and the result shows that the cache system is verified correctly using the exhaustive search model, and it makes the verification much more manageable and flexible. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cache%20system" title="cache system">cache system</a>, <a href="https://publications.waset.org/abstracts/search?q=formal%20verification" title=" formal verification"> formal verification</a>, <a href="https://publications.waset.org/abstracts/search?q=novel%20model" title=" novel model"> novel model</a>, <a href="https://publications.waset.org/abstracts/search?q=system%20on%20chip%20%28SoC%29" title=" system on chip (SoC)"> system on chip (SoC)</a> </p> <a href="https://publications.waset.org/abstracts/26581/formal-verification-of-cache-system-using-a-novel-cache-memory-model" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/26581.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">496</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">27</span> Impact of Stack Caches: Locality Awareness and Cost Effectiveness</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdulrahman%20K.%20Alshegaifi">Abdulrahman K. Alshegaifi</a>, <a href="https://publications.waset.org/abstracts/search?q=Chun-Hsi%20Huang"> Chun-Hsi Huang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Treating data based on its location in memory has received much attention in recent years due to its different properties, which offer important aspects for cache utilization. Stack data and non-stack data may interfere with each other’s locality in the data cache. One of the important aspects of stack data is that it has high spatial and temporal locality. In this work, we simulate non-unified cache design that split data cache into stack and non-stack caches in order to maintain stack data and non-stack data separate in different caches. We observe that the overall hit rate of non-unified cache design is sensitive to the size of non-stack cache. Then, we investigate the appropriate size and associativity for stack cache to achieve high hit ratio especially when over 99% of accesses are directed to stack cache. The result shows that on average more than 99% of stack cache accuracy is achieved by using 2KB of capacity and 1-way associativity. Further, we analyze the improvement in hit rate when adding small, fixed, size of stack cache at level1 to unified cache architecture. The result shows that the overall hit rate of unified cache design with adding 1KB of stack cache is improved by approximately, on average, 3.9% for Rijndael benchmark. The stack cache is simulated by using SimpleScalar toolset. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hit%20rate" title="hit rate">hit rate</a>, <a href="https://publications.waset.org/abstracts/search?q=locality%20of%20program" title=" locality of program"> locality of program</a>, <a href="https://publications.waset.org/abstracts/search?q=stack%20cache" title=" stack cache"> stack cache</a>, <a href="https://publications.waset.org/abstracts/search?q=stack%20data" title=" stack data"> stack data</a> </p> <a href="https://publications.waset.org/abstracts/46309/impact-of-stack-caches-locality-awareness-and-cost-effectiveness" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/46309.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">303</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">26</span> Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yiwei%20Li">Yiwei Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Boyu%20Tian"> Boyu Tian</a>, <a href="https://publications.waset.org/abstracts/search?q=Mingyu%20Gao"> Mingyu Gao</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Hybrid main memory systems combine both performance and capacity advantages from heterogeneous memory technologies. With larger capacities, higher associativities, and finer granularities, hybrid memory systems currently exhibit significant metadata storage and lookup overheads for flexibly remapping data blocks between the two memory tiers. To alleviate the inefficiencies of existing designs, we propose Trimma, the combination of a multi-level metadata structure and an efficient metadata cache design. Trimma uses a multilevel metadata table to only track truly necessary address remap entries. The saved memory space is effectively utilized as extra DRAM cache capacity to improve performance. Trimma also uses separate formats to store the entries with non-identity and identity mappings. This improves the overall remap cache hit rate, further boosting the performance. Trimma is transparent to software and compatible with various types of hybrid memory systems. When evaluated on a representative DDR4 + NVM hybrid memory system, Trimma achieves up to 2.4× and on average 58.1% speedup benefits, compared with a state-of-the-art design that only leverages the unallocated fast memory space for caching. Trimma addresses metadata management overheads and targets future scalable large-scale hybrid memory architectures. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=memory%20system" title="memory system">memory system</a>, <a href="https://publications.waset.org/abstracts/search?q=data%20cache" title=" data cache"> data cache</a>, <a href="https://publications.waset.org/abstracts/search?q=hybrid%20memory" title=" hybrid memory"> hybrid memory</a>, <a href="https://publications.waset.org/abstracts/search?q=non-volatile%20memory" title=" non-volatile memory"> non-volatile memory</a> </p> <a href="https://publications.waset.org/abstracts/183183/trimma-trimming-metadata-storage-and-latency-for-hybrid-memory-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/183183.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">79</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">25</span> Evaluating the Impact of Replacement Policies on the Cache Performance and Energy Consumption in Different Multicore Embedded Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sajjad%20Rostami-Sani">Sajjad Rostami-Sani</a>, <a href="https://publications.waset.org/abstracts/search?q=Mojtaba%20Valinataj"> Mojtaba Valinataj</a>, <a href="https://publications.waset.org/abstracts/search?q=Amir-Hossein%20Khojir-Angasi"> Amir-Hossein Khojir-Angasi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The cache has an important role in the reduction of access delay between a processor and memory in high-performance embedded systems. In these systems, the energy consumption is one of the most important concerns, and it will become more important with smaller processor feature sizes and higher frequencies. Meanwhile, the cache system dissipates a significant portion of energy compared to the other components of a processor. There are some elements that can affect the energy consumption of the cache such as replacement policy and degree of associativity. Due to these points, it can be inferred that selecting an appropriate configuration for the cache is a crucial part of designing a system. In this paper, we investigate the effect of different cache replacement policies on both cache’s performance and energy consumption. Furthermore, the impact of different Instruction Set Architectures (ISAs) on cache’s performance and energy consumption has been investigated. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=energy%20consumption" title="energy consumption">energy consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=replacement%20policy" title=" replacement policy"> replacement policy</a>, <a href="https://publications.waset.org/abstracts/search?q=instruction%20set%20architecture" title=" instruction set architecture"> instruction set architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=multicore%20processor" title=" multicore processor"> multicore processor</a> </p> <a href="https://publications.waset.org/abstracts/122029/evaluating-the-impact-of-replacement-policies-on-the-cache-performance-and-energy-consumption-in-different-multicore-embedded-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/122029.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">154</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">24</span> Analysis of Performance of 3T1D Dynamic Random-Access Memory Cell</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nawang%20Chhunid">Nawang Chhunid</a>, <a href="https://publications.waset.org/abstracts/search?q=Gagnesh%20Kumar"> Gagnesh Kumar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DRAM%20Cell" title="DRAM Cell">DRAM Cell</a>, <a href="https://publications.waset.org/abstracts/search?q=Read%20Access%20Time" title=" Read Access Time"> Read Access Time</a>, <a href="https://publications.waset.org/abstracts/search?q=Retention%20Time" title=" Retention Time"> Retention Time</a>, <a href="https://publications.waset.org/abstracts/search?q=Average%20Power%20dissipation" title=" Average Power dissipation"> Average Power dissipation</a> </p> <a href="https://publications.waset.org/abstracts/52217/analysis-of-performance-of-3t1d-dynamic-random-access-memory-cell" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/52217.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">313</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">23</span> On Performance of Cache Replacement Schemes in NDN-IoT</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rasool%20Sadeghi">Rasool Sadeghi</a>, <a href="https://publications.waset.org/abstracts/search?q=Sayed%20Mahdi%20Faghih%20Imani"> Sayed Mahdi Faghih Imani</a>, <a href="https://publications.waset.org/abstracts/search?q=Negar%20Najafi"> Negar Najafi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The inherent features of Named Data Networking (NDN) provides a robust solution for Internet of Thing (IoT). Therefore, NDN-IoT has emerged as a combined architecture which exploits the benefits of NDN for interconnecting of the heterogeneous objects in IoT. In NDN-IoT, caching schemes are a key role to improve the network performance. In this paper, we consider the effectiveness of cache replacement schemes in NDN-IoT scenarios. We investigate the impact of replacement schemes on average delay, average hop count, and average interest retransmission when replacement schemes are Least Frequently Used (LFU), Least Recently Used (LRU), First-In-First-Out (FIFO) and Random. The simulation results demonstrate that LFU and LRU present a stable performance when the cache size changes. Moreover, the network performance improves when the number of consumers increases. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=NDN-IoT" title="NDN-IoT">NDN-IoT</a>, <a href="https://publications.waset.org/abstracts/search?q=cache%20replacement" title=" cache replacement"> cache replacement</a>, <a href="https://publications.waset.org/abstracts/search?q=performance" title=" performance"> performance</a>, <a href="https://publications.waset.org/abstracts/search?q=ndnSIM" title=" ndnSIM"> ndnSIM</a> </p> <a href="https://publications.waset.org/abstracts/84255/on-performance-of-cache-replacement-schemes-in-ndn-iot" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/84255.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">365</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">22</span> Cache Analysis and Software Optimizations for Faster on-Chip Network Simulations</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Khyamling%20Parane">Khyamling Parane</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20M.%20Prabhu%20Prasad"> B. M. Prabhu Prasad</a>, <a href="https://publications.waset.org/abstracts/search?q=Basavaraj%20Talawar"> Basavaraj Talawar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Fast simulations are critical in reducing time to market in CMPs and SoCs. Several simulators have been used to evaluate the performance and power consumed by Network-on-Chips. Researchers and designers rely upon these simulators for design space exploration of NoC architectures. Our experiments show that simulating large NoC topologies take hours to several days for completion. To speed up the simulations, it is necessary to investigate and optimize the hotspots in simulator source code. Among several simulators available, we choose Booksim2.0, as it is being extensively used in the NoC community. In this paper, we analyze the cache and memory system behaviour of Booksim2.0 to accurately monitor input dependent performance bottlenecks. Our measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having least misses has been identified. To further reduce the cache misses, we use software optimization techniques such as removal of unused functions, loop interchanging and replacing post-increment operator with pre-increment operator for non-primitive data types. The cache misses were reduced by 18.52%, 5.34% and 3.91% by employing above technology respectively. We also employ thread parallelization and vectorization to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93x and 3.97x were observed for the Mesh topology with 30 × 30 network size by employing thread parallelization and vectorization respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cache%20behaviour" title="cache behaviour">cache behaviour</a>, <a href="https://publications.waset.org/abstracts/search?q=network-on-chip" title=" network-on-chip"> network-on-chip</a>, <a href="https://publications.waset.org/abstracts/search?q=performance%20profiling" title=" performance profiling"> performance profiling</a>, <a href="https://publications.waset.org/abstracts/search?q=vectorization" title=" vectorization"> vectorization</a> </p> <a href="https://publications.waset.org/abstracts/56749/cache-analysis-and-software-optimizations-for-faster-on-chip-network-simulations" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/56749.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">197</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">21</span> DCASH: Dynamic Cache Synchronization Algorithm for Heterogeneous Reverse Y Synchronizing Mobile Database Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Gunasekaran%20Raja">Gunasekaran Raja</a>, <a href="https://publications.waset.org/abstracts/search?q=Kottilingam%20Kottursamy"> Kottilingam Kottursamy</a>, <a href="https://publications.waset.org/abstracts/search?q=Rajakumar%20Arul"> Rajakumar Arul</a>, <a href="https://publications.waset.org/abstracts/search?q=Ramkumar%20Jayaraman"> Ramkumar Jayaraman</a>, <a href="https://publications.waset.org/abstracts/search?q=Krithika%20Sairam"> Krithika Sairam</a>, <a href="https://publications.waset.org/abstracts/search?q=Lakshmi%20Ravi"> Lakshmi Ravi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The synchronization server maintains a dynamically changing cache, which contains the data items which were requested and collected by the mobile node from the server. The order and presence of tuples in the cache changes dynamically according to the frequency of updates performed on the data, by the server and client. To synchronize, the data which has been modified by client and the server at an instant are collected, batched together by the type of modification (insert/ update/ delete), and sorted according to their update frequencies. This ensures that the DCASH (Dynamic Cache Synchronization Algorithm for Heterogeneous Reverse Y synchronizing Mobile Database Systems) gives priority to the frequently accessed data with high usage. The optimal memory management algorithm is proposed to manage data items according to their frequency, theorems were written to show the current mobile data activity is reverse Y in nature and the experiments were tested with 2g and 3g networks for various mobile devices to show the reduced response time and energy consumption. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mobile%20databases" title="mobile databases">mobile databases</a>, <a href="https://publications.waset.org/abstracts/search?q=synchronization" title=" synchronization"> synchronization</a>, <a href="https://publications.waset.org/abstracts/search?q=cache" title=" cache"> cache</a>, <a href="https://publications.waset.org/abstracts/search?q=response%20time" title=" response time"> response time</a> </p> <a href="https://publications.waset.org/abstracts/48854/dcash-dynamic-cache-synchronization-algorithm-for-heterogeneous-reverse-y-synchronizing-mobile-database-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/48854.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">405</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">20</span> Hydrogen: Contention-Aware Hybrid Memory Management for Heterogeneous CPU-GPU Architectures</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yiwei%20Li">Yiwei Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Mingyu%20Gao"> Mingyu Gao</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Integrating hybrid memories with heterogeneous processors could leverage heterogeneity in both compute and memory domains for better system efficiency. To ensure performance isolation, we introduce Hydrogen, a hardware architecture to optimize the allocation of hybrid memory resources to heterogeneous CPU-GPU systems. Hydrogen supports efficient capacity and bandwidth partitioning between CPUs and GPUs in both memory tiers. We propose decoupled memory channel mapping and token-based data migration throttling to enable flexible partitioning. We also support epoch-based online search for optimized configurations and lightweight reconfiguration with reduced data movements. Hydrogen significantly outperforms existing designs by 1.21x on average and up to 1.31x. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hybrid%20memory" title="hybrid memory">hybrid memory</a>, <a href="https://publications.waset.org/abstracts/search?q=heterogeneous%20systems" title=" heterogeneous systems"> heterogeneous systems</a>, <a href="https://publications.waset.org/abstracts/search?q=dram%20cache" title=" dram cache"> dram cache</a>, <a href="https://publications.waset.org/abstracts/search?q=graphics%20processing%20units" title=" graphics processing units"> graphics processing units</a> </p> <a href="https://publications.waset.org/abstracts/183187/hydrogen-contention-aware-hybrid-memory-management-for-heterogeneous-cpu-gpu-architectures" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/183187.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">96</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">19</span> A Survey on Countermeasures of Cache-Timing Attack on AES Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Settana%20M.%20Abdulh">Settana M. Abdulh</a>, <a href="https://publications.waset.org/abstracts/search?q=Naila%20A.%20Sadalla"> Naila A. Sadalla</a>, <a href="https://publications.waset.org/abstracts/search?q=Yaseen%20H.%20Taha"> Yaseen H. Taha</a>, <a href="https://publications.waset.org/abstracts/search?q=Howaida%20Elshoush"> Howaida Elshoush</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Side channel attacks are based on side channel information, which is information that is leaked from encryption systems. This includes timing information, power consumption as well as electromagnetic or even sound leaking which can exploited by an attacker. Implementing side channel attacks are possible if and only if an attacker has access to a cryptosystem. In this case, the attacker can exploit bad implementation in software or hardware which is not controlled by encryption implementer. Thus, he/she will represent a real threat to the security system. Several countermeasures have been proposed to eliminate side channel information vulnerability.Cache timing attack is a special type of side channel attack. Here, timing information is collected and analyzed by an attacker to guess sensitive information such as encryption key or plaintext. This paper reviews the technique applied in this attack and surveys the countermeasures against it, evaluating the feasibility and usability of each. Based on this evaluation, finally we pose several recommendations about using these countermeasures. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=AES%20algorithm" title="AES algorithm">AES algorithm</a>, <a href="https://publications.waset.org/abstracts/search?q=side%20channel%20attack" title=" side channel attack"> side channel attack</a>, <a href="https://publications.waset.org/abstracts/search?q=cache%20timing%20attack" title=" cache timing attack"> cache timing attack</a>, <a href="https://publications.waset.org/abstracts/search?q=cache%20timing%20countermeasure" title=" cache timing countermeasure"> cache timing countermeasure</a> </p> <a href="https://publications.waset.org/abstracts/17652/a-survey-on-countermeasures-of-cache-timing-attack-on-aes-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/17652.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">299</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">18</span> Machine Learning Assisted Performance Optimization in Memory Tiering</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Derssie%20Mebratu">Derssie Mebratu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> As a large variety of micro services, web services, social graphic applications, and media applications are continuously developed, it is substantially vital to design and build a reliable, efficient, and faster memory tiering system. Despite limited design, implementation, and deployment in the last few years, several techniques are currently developed to improve a memory tiering system in a cloud. Some of these techniques are to develop an optimal scanning frequency; improve and track pages movement; identify pages that recently accessed; store pages across each tiering, and then identify pages as a hot, warm, and cold so that hot pages can store in the first tiering Dynamic Random Access Memory (DRAM) and warm pages store in the second tiering Compute Express Link(CXL) and cold pages store in the third tiering Non-Volatile Memory (NVM). Apart from the current proposal and implementation, we also develop a new technique based on a machine learning algorithm in that the throughput produced 25% improved performance compared to the performance produced by the baseline as well as the latency produced 95% improved performance compared to the performance produced by the baseline. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=machine%20learning" title="machine learning">machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=bayesian%20optimization" title=" bayesian optimization"> bayesian optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=memory%20tiering" title=" memory tiering"> memory tiering</a>, <a href="https://publications.waset.org/abstracts/search?q=CXL" title=" CXL"> CXL</a>, <a href="https://publications.waset.org/abstracts/search?q=DRAM" title=" DRAM"> DRAM</a> </p> <a href="https://publications.waset.org/abstracts/156985/machine-learning-assisted-performance-optimization-in-memory-tiering" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/156985.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">96</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">17</span> A Privacy Protection Scheme Supporting Fuzzy Search for NDN Routing Cache Data Name</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Feng%20Tao">Feng Tao</a>, <a href="https://publications.waset.org/abstracts/search?q=Ma%20Jing"> Ma Jing</a>, <a href="https://publications.waset.org/abstracts/search?q=Guo%20Xian"> Guo Xian</a>, <a href="https://publications.waset.org/abstracts/search?q=Wang%20Jing"> Wang Jing</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Named Data Networking (NDN) replaces IP address of traditional network with data name, and adopts dynamic cache mechanism. In the existing mechanism, however, only one-to-one search can be achieved because every data has a unique name corresponding to it. There is a certain mapping relationship between data content and data name, so if the data name is intercepted by an adversary, the privacy of the data content and user’s interest can hardly be guaranteed. In order to solve this problem, this paper proposes a one-to-many fuzzy search scheme based on order-preserving encryption to reduce the query overhead by optimizing the caching strategy. In this scheme, we use hash value to ensure the user’s query safe from each node in the process of search, so does the privacy of the requiring data content. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=NDN" title="NDN">NDN</a>, <a href="https://publications.waset.org/abstracts/search?q=order-preserving%20encryption" title=" order-preserving encryption"> order-preserving encryption</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20search" title=" fuzzy search"> fuzzy search</a>, <a href="https://publications.waset.org/abstracts/search?q=privacy" title=" privacy"> privacy</a> </p> <a href="https://publications.waset.org/abstracts/28847/a-privacy-protection-scheme-supporting-fuzzy-search-for-ndn-routing-cache-data-name" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28847.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">484</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">16</span> The Ideal Memory Substitute for Computer Memory Hierarchy</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kayode%20A.%20Olaniyi">Kayode A. Olaniyi</a>, <a href="https://publications.waset.org/abstracts/search?q=Olabanji%20F.%20Omotoye"> Olabanji F. Omotoye</a>, <a href="https://publications.waset.org/abstracts/search?q=Adeola%20A.%20Ogunleye"> Adeola A. Ogunleye</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Computer system components such as the CPU, the Controllers, and the operating system, work together as a team, and storage or memory is the essential parts of this team apart from the processor. The memory and storage system including processor caches, main memory, and storage, form basic storage component of a computer system. The characteristics of the different types of storage are inherent in the design and the technology employed in the manufacturing. These memory characteristics define the speed, compatibility, cost, volatility, and density of the various storage types. Most computers rely on a hierarchy of storage devices for performance. The effective and efficient use of the memory hierarchy of the computer system therefore is the single most important aspect of computer system design and use. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing demands of modern computer applications and the limited performance and energy efficiency provided by traditional memory technologies. With the dramatic development in the computers systems, computer storage has had a difficult time keeping up with the processor speed. Computer architects are therefore facing constant challenges in developing high-speed computer storage with high-performance which is energy-efficient, cost-effective and reliable, to intercept processor requests. It is very clear that substantial advancements in redesigning the existing memory physical and logical structures to meet up with the latest processor potential is crucial. This research work investigates the importance of computer memory (storage) hierarchy in the design of computer systems. The constituent storage types of the hierarchy today were investigated looking at the design technologies and how the technologies affect memory characteristics: speed, density, stability and cost. The investigation considered how these characteristics could best be harnessed for overall efficiency of the computer system. The research revealed that the best single type of storage, which we refer to as ideal memory is that logical single physical memory which would combine the best attributes of each memory type that make up the memory hierarchy. It is a single memory with access speed as high as one found in CPU registers, combined with the highest storage capacity, offering excellent stability in the presence or absence of power as found in the magnetic and optical disks as against volatile DRAM, and yet offers a cost-effective attribute that is far away from the expensive SRAM. The research work suggests that to overcome these barriers it may then mean that memory manufacturing will take a total deviation from the present technologies and adopt one that overcomes the associated challenges with the traditional memory technologies. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cache" title="cache">cache</a>, <a href="https://publications.waset.org/abstracts/search?q=memory-hierarchy" title=" memory-hierarchy"> memory-hierarchy</a>, <a href="https://publications.waset.org/abstracts/search?q=memory" title=" memory"> memory</a>, <a href="https://publications.waset.org/abstracts/search?q=registers" title=" registers"> registers</a>, <a href="https://publications.waset.org/abstracts/search?q=storage" title=" storage"> storage</a> </p> <a href="https://publications.waset.org/abstracts/103396/the-ideal-memory-substitute-for-computer-memory-hierarchy" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/103396.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">164</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">15</span> Low Power CNFET SRAM Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Pejman%20Hosseiniun">Pejman Hosseiniun</a>, <a href="https://publications.waset.org/abstracts/search?q=Rose%20Shayeghi"> Rose Shayeghi</a>, <a href="https://publications.waset.org/abstracts/search?q=Iman%20Rahbari"> Iman Rahbari</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohamad%20Reza%20Kalhor"> Mohamad Reza Kalhor</a> </p> <p class="card-text"><strong>Abstract:</strong></p> CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SRAM%20cell" title="SRAM cell">SRAM cell</a>, <a href="https://publications.waset.org/abstracts/search?q=CNFET" title=" CNFET"> CNFET</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=HSPICE" title=" HSPICE "> HSPICE </a> </p> <a href="https://publications.waset.org/abstracts/7468/low-power-cnfet-sram-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7468.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">414</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">14</span> Speedup Breadth-First Search by Graph Ordering</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Qiuyi%20Lyu">Qiuyi Lyu</a>, <a href="https://publications.waset.org/abstracts/search?q=Bin%20Gong"> Bin Gong</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Breadth-First Search(BFS) is a core graph algorithm that is widely used for graph analysis. As it is frequently used in many graph applications, improve the BFS performance is essential. In this paper, we present a graph ordering method that could reorder the graph nodes to achieve better data locality, thus, improving the BFS performance. Our method is based on an observation that the sibling relationships will dominate the cache access pattern during the BFS traversal. Therefore, we propose a frequency-based model to construct the graph order. First, we optimize the graph order according to the nodes’ visit frequency. Nodes with high visit frequency will be processed in priority. Second, we try to maximize the child nodes overlap layer by layer. As it is proved to be NP-hard, we propose a heuristic method that could greatly reduce the preprocessing overheads. We conduct extensive experiments on 16 real-world datasets. The result shows that our method could achieve comparable performance with the state-of-the-art methods while the graph ordering overheads are only about 1/15. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=breadth-first%20search" title="breadth-first search">breadth-first search</a>, <a href="https://publications.waset.org/abstracts/search?q=BFS" title=" BFS"> BFS</a>, <a href="https://publications.waset.org/abstracts/search?q=graph%20ordering" title=" graph ordering"> graph ordering</a>, <a href="https://publications.waset.org/abstracts/search?q=graph%20algorithm" title=" graph algorithm"> graph algorithm</a> </p> <a href="https://publications.waset.org/abstracts/136790/speedup-breadth-first-search-by-graph-ordering" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/136790.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">138</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">13</span> Reactive and Concurrency-Based Image Resource Management Module for iOS Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shubham%20V.%20Kamdi">Shubham V. Kamdi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper aims to serve as an introduction to image resource caching techniques for iOS mobile applications. It will explain how developers can break down multiple image-downloading tasks concurrently using state-of-the-art iOS frameworks, namely Swift Concurrency and Combine. The paper will explain how developers can leverage SwiftUI to develop reactive view components and use declarative coding patterns. Developers will learn to bypass built-in image caching systems by curating the procedure to implement a swift-based LRU cache system. The paper will provide a full architectural overview of a system, helping readers understand how mobile applications are designed professionally. It will cover technical discussion, helping readers understand the low-level details of threads and how they can switch between them, as well as the significance of the main and background threads for requesting HTTP services via mobile applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=main%20thread" title="main thread">main thread</a>, <a href="https://publications.waset.org/abstracts/search?q=background%20thread" title=" background thread"> background thread</a>, <a href="https://publications.waset.org/abstracts/search?q=reactive%20view%20components" title=" reactive view components"> reactive view components</a>, <a href="https://publications.waset.org/abstracts/search?q=declarative%20coding" title=" declarative coding"> declarative coding</a> </p> <a href="https://publications.waset.org/abstracts/192451/reactive-and-concurrency-based-image-resource-management-module-for-ios-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/192451.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">25</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12</span> Secure Network Coding against Content Pollution Attacks in Named Data Network</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tao%20Feng">Tao Feng</a>, <a href="https://publications.waset.org/abstracts/search?q=Xiaomei%20Ma"> Xiaomei Ma</a>, <a href="https://publications.waset.org/abstracts/search?q=Xian%20Guo"> Xian Guo</a>, <a href="https://publications.waset.org/abstracts/search?q=Jing%20Wang"> Jing Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Named Data Network (NDN) is one of the future Internet architecture, all nodes (i.e., hosts, routers) are allowed to have a local cache, used to satisfy incoming requests for content. However, depending on caching allows an adversary to perform attacks that are very effective and relatively easy to implement, such as content pollution attack. In this paper, we use a method of secure network coding based on homomorphic signature system to solve this problem. Firstly ,we use a dynamic public key technique, our scheme for each generation authentication without updating the initial secret key used. Secondly, employing the homomorphism of hash function, intermediate node and destination node verify the signature of the received message. In addition, when the network topology of NDN is simple and fixed, the code coefficients in our scheme are generated in a pseudorandom number generator in each node, so the distribution of the coefficients is also avoided. In short, our scheme not only can efficiently prevent against Intra/Inter-GPAs, but also can against the content poisoning attack in NDN. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=named%20data%20networking" title="named data networking">named data networking</a>, <a href="https://publications.waset.org/abstracts/search?q=content%20polloution%20attack" title=" content polloution attack"> content polloution attack</a>, <a href="https://publications.waset.org/abstracts/search?q=network%20coding%20signature" title=" network coding signature"> network coding signature</a>, <a href="https://publications.waset.org/abstracts/search?q=internet%20architecture" title=" internet architecture"> internet architecture</a> </p> <a href="https://publications.waset.org/abstracts/28198/secure-network-coding-against-content-pollution-attacks-in-named-data-network" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28198.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">337</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">11</span> The Classical and Hellenistic Architectural Elements of the Temple of Echmun in Sidon</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Amal%20Alatar">Amal Alatar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The paper focuses on the exploration of architectural characteristics and decorative elements of the temple of Echmun, emphasizing the socio-economic significance of Sidon during the Greek and Roman periods to understand the implications of their spread and development on the Phoenician cities, as well as reveal the symbolical and societal connotations that may have been connected with the buildings, in order to allow a well-founded examination of common characteristics. In general, studying Phoenician archaeology posed some problems. The main problem is that most major Phoenician settlements lay beneath modern urban centers. This situation often prevented or largely restricted full archaeological investigations; the publications are frequently not complete enough to determine the basic characteristics of the architectural elements. Another key problem is the political instability of the region, which affected the archaeological research in the Phoenician homeland for many years. Nevertheless, during the past decades, an ever-growing cache of data was acquired from the archaeological surroundings of the Phoenician sites. Both the architectural elements from the Greek and Roman period have never been studied as a group before. Surprisingly, they have been largely ignored, despite their apparent profusion throughout the cities. The Roman period of Sidon has generally been neglected in preference to earlier periods, where it is often difficult to distinguish between Roman, Bronze age, medieval and Ottoman structures. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=archaeology" title="archaeology">archaeology</a>, <a href="https://publications.waset.org/abstracts/search?q=classical" title=" classical"> classical</a>, <a href="https://publications.waset.org/abstracts/search?q=Hellenistic" title=" Hellenistic"> Hellenistic</a>, <a href="https://publications.waset.org/abstracts/search?q=Eshmun%20Temple" title=" Eshmun Temple"> Eshmun Temple</a>, <a href="https://publications.waset.org/abstracts/search?q=architecture" title=" architecture"> architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=Sidon" title=" Sidon"> Sidon</a>, <a href="https://publications.waset.org/abstracts/search?q=Lebanon" title=" Lebanon"> Lebanon</a> </p> <a href="https://publications.waset.org/abstracts/160642/the-classical-and-hellenistic-architectural-elements-of-the-temple-of-echmun-in-sidon" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/160642.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">101</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">10</span> Automatic Tuning for a Systemic Model of Banking Originated Losses (SYMBOL) Tool on Multicore</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ronal%20Muresano">Ronal Muresano</a>, <a href="https://publications.waset.org/abstracts/search?q=Andrea%20Pagano"> Andrea Pagano</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays, the mathematical/statistical applications are developed with more complexity and accuracy. However, these precisions and complexities have brought as result that applications need more computational power in order to be executed faster. In this sense, the multicore environments are playing an important role to improve and to optimize the execution time of these applications. These environments allow us the inclusion of more parallelism inside the node. However, to take advantage of this parallelism is not an easy task, because we have to deal with some problems such as: cores communications, data locality, memory sizes (cache and RAM), synchronizations, data dependencies on the model, etc. These issues are becoming more important when we wish to improve the application’s performance and scalability. Hence, this paper describes an optimization method developed for Systemic Model of Banking Originated Losses (SYMBOL) tool developed by the European Commission, which is based on analyzing the application's weakness in order to exploit the advantages of the multicore. All these improvements are done in an automatic and transparent manner with the aim of improving the performance metrics of our tool. Finally, experimental evaluations show the effectiveness of our new optimized version, in which we have achieved a considerable improvement on the execution time. The time has been reduced around 96% for the best case tested, between the original serial version and the automatic parallel version. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=algorithm%20optimization" title="algorithm optimization">algorithm optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=bank%20failures" title=" bank failures"> bank failures</a>, <a href="https://publications.waset.org/abstracts/search?q=OpenMP" title=" OpenMP"> OpenMP</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20techniques" title=" parallel techniques"> parallel techniques</a>, <a href="https://publications.waset.org/abstracts/search?q=statistical%20tool" title=" statistical tool"> statistical tool</a> </p> <a href="https://publications.waset.org/abstracts/14489/automatic-tuning-for-a-systemic-model-of-banking-originated-losses-symbol-tool-on-multicore" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/14489.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">369</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">9</span> Security Design of Root of Trust Based on RISC-V</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kang%20Huang">Kang Huang</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Shiwei%20Yuan"> Shiwei Yuan</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Since information technology develops rapidly, the security issue has become an increasingly critical for computer system. In particular, as cloud computing and the Internet of Things (IoT) continue to gain widespread adoption, computer systems need to new security threats and attacks. The Root of Trust (RoT) is the foundation for providing basic trusted computing, which is used to verify the security and trustworthiness of other components. Design a reliable Root of Trust and guarantee its own security are essential for improving the overall security and credibility of computer systems. In this paper, we discuss the implementation of self-security technology based on the RISC-V Root of Trust at the hardware level. To effectively safeguard the security of the Root of Trust, researches on security safeguard technology on the Root of Trust have been studied. At first, a lightweight and secure boot framework is proposed as a secure mechanism. Secondly, two kinds of memory protection mechanism are built to against memory attacks. Moreover, hardware implementation of proposed method has been also investigated. A series of experiments and tests have been carried on to verify to effectiveness of the proposed method. The experimental results demonstrated that the proposed approach is effective in verifying the integrity of the Root of Trust’s own boot rom, user instructions, and data, ensuring authenticity and enabling the secure boot of the Root of Trust’s own system. Additionally, our approach provides memory protection against certain types of memory attacks, such as cache leaks and tampering, and ensures the security of root-of-trust sensitive information, including keys. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=root%20of%20trust" title="root of trust">root of trust</a>, <a href="https://publications.waset.org/abstracts/search?q=secure%20boot" title=" secure boot"> secure boot</a>, <a href="https://publications.waset.org/abstracts/search?q=memory%20protection" title=" memory protection"> memory protection</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a> </p> <a href="https://publications.waset.org/abstracts/164581/security-design-of-root-of-trust-based-on-risc-v" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/164581.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">216</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">8</span> Improve B-Tree Index’s Performance Using Lock-Free Hash Table</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zhanfeng%20Ma">Zhanfeng Ma</a>, <a href="https://publications.waset.org/abstracts/search?q=Zhiping%20Xiong"> Zhiping Xiong</a>, <a href="https://publications.waset.org/abstracts/search?q=Hu%20Yin"> Hu Yin</a>, <a href="https://publications.waset.org/abstracts/search?q=Zhengwei%20She"> Zhengwei She</a>, <a href="https://publications.waset.org/abstracts/search?q=Aditya%20P.%20Gurajada"> Aditya P. Gurajada</a>, <a href="https://publications.waset.org/abstracts/search?q=Tianlun%20Chen"> Tianlun Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Ying%20Li"> Ying Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Many RDBMS vendors use B-tree index to achieve high performance for point queries and range queries, and some of them also employ hash index to further enhance the performance as hash table is more efficient for point queries. However, there are extra overheads to maintain a separate hash index, for example, hash mapping for all data records must always be maintained, which results in more memory space consumption; locking, logging and other mechanisms are needed to guarantee ACID, which affects the concurrency and scalability of the system. To relieve the overheads, Hash Cached B-tree (HCB) index is proposed in this paper, which consists of a standard disk-based B-tree index and an additional in-memory lock-free hash table. Initially, only the B-tree index is constructed for all data records, the hash table is built on the fly based on runtime workload, only data records accessed by point queries are indexed using hash table, this helps reduce the memory footprint. Changes to hash table are done using compare-and-swap (CAS) without performing locking and logging, this helps improve the concurrency and avoid contention. The hash table is also optimized to be cache conscious. HCB index is implemented in SAP ASE database, compared with the standard B-tree index, early experiments and customer adoptions show significant performance improvement. This paper provides an overview of the design of HCB index and reports the experimental results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=B-tree" title="B-tree">B-tree</a>, <a href="https://publications.waset.org/abstracts/search?q=compare-and-swap" title=" compare-and-swap"> compare-and-swap</a>, <a href="https://publications.waset.org/abstracts/search?q=lock-free%20hash%20table" title=" lock-free hash table"> lock-free hash table</a>, <a href="https://publications.waset.org/abstracts/search?q=point%20queries" title=" point queries"> point queries</a>, <a href="https://publications.waset.org/abstracts/search?q=range%20queries" title=" range queries"> range queries</a>, <a href="https://publications.waset.org/abstracts/search?q=SAP%20ASE%20database" title=" SAP ASE database"> SAP ASE database</a> </p> <a href="https://publications.waset.org/abstracts/72665/improve-b-tree-indexs-performance-using-lock-free-hash-table" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/72665.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">286</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7</span> Documentation Project on Decorated Wooden Coffins From Luxor, in the Cairo Museum</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hassan%20Mohmed">Hassan Mohmed</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohamed%20Ismail"> Mohamed Ismail</a>, <a href="https://publications.waset.org/abstracts/search?q=Aiman%20Rezk"> Aiman Rezk</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Introduction: This project aims to document and preserve decorated wooden coffins which were discovered in Luxor by Egyptian mission at Luxor, (SR Numbers:2514,2519,2520,2521,5469).These decorated wooden coffins dates back to Egyptian New Kingdom period and has been transferred to the Cairo Museum, to be displayed at the museum. These decorated wooden coffins discovered in the cache-tomb of Bab el-gasus at Deir el-Bahari, Luxor. This site has been dictated for the burials of priests of Amun through 18th Dynasty the coffins owners held these titles, which are as follows: "the embalmer of the beautiful-house (the place of embalming)" and "the servant in the place of truth". Methodology: Methodology: The project objectives making such decorated wooden coffins more visible to visitors through the use of 3D reconstructed coffins and high resolution photos which describe the history of using the wooden coffins during the Ancient Egyptian history Especially, The Cairo Museum is going to exhibit decorated wooden coffins in New kingdom. The project goals is to document decorated wooden coffins and arrange an exhibition, where such decorated wooden coffins going to be displayed next to the Ramses 2nd coffin, This research focuses on the text analyses and the technology. Paleographic information found on these objects. Conclusion: The project shows the importance of using coffins in Ancient Egypt, and connecting their usage through Ancient Egyptian periods; the coffins had a unique Symbolized in ancient Egypt and connect the public with their kings. The Egyptian put coffins in their tombs that they hope to save their bodies’ afterlife. This research will be beneficial and useful for the heritage and ancient civilizations, Indeed this study will open a destination in order to know how to identify these collections and how to exhibit them commensurate with the natural of the ancient Egyptian history and heritage. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=archaeology" title="archaeology">archaeology</a>, <a href="https://publications.waset.org/abstracts/search?q=decorated%20wooden%20coffins" title=" decorated wooden coffins"> decorated wooden coffins</a>, <a href="https://publications.waset.org/abstracts/search?q=3D%20digital%20tools%20for%20heritage%20management" title=" 3D digital tools for heritage management"> 3D digital tools for heritage management</a>, <a href="https://publications.waset.org/abstracts/search?q=museums" title=" museums"> museums</a> </p> <a href="https://publications.waset.org/abstracts/163691/documentation-project-on-decorated-wooden-coffins-from-luxor-in-the-cairo-museum" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/163691.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">77</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">6</span> Evaluating Habitat Manipulation as a Strategy for Rodent Control in Agricultural Ecosystems of Pothwar Region, Pakistan</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nadeem%20Munawar">Nadeem Munawar</a>, <a href="https://publications.waset.org/abstracts/search?q=Tariq%20Mahmood"> Tariq Mahmood</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Habitat manipulation is an important technique that can be used for controlling rodent damage in agricultural ecosystems. It involves intentionally manipulation of vegetation cover in adjacent habitats around the active burrows of rodents to reduce shelter, food availability and to increase predation pressure. The current study was conducted in the Pothwar Plateau during the respective non-crop period of wheat-groundnut (post-harvested and un-ploughed/non-crop fallow lands) with the aim to assess the impact of the reduction in vegetation height of adjacent habitats (field borders) on rodent’s richness and abundance. The study area was divided into two sites viz. treated and non-treated. At the treated sites, habitat manipulation was carried out by removing crop cache, and non-crop vegetation’s over 10 cm in height to a distance of approximately 20 m from the fields. The trapping sessions carried out at both treated and non-treated sites adjacent to wheat-groundnut fields were significantly different (F 2, 6 = 13.2, P = 0.001) from each other, which revealed that a maximum number of rodents were captured from non-treated sites. There was a significant difference in the overall abundance of rodents (P < 0.05) between crop stages and between treatments in both crops. The manipulation effect was significantly observed on damage to crops, and yield production resulted in the reduction of damage within the associated croplands (P < 0.05). The outcomes of this study indicated a significant reduction of rodent population at treated sites due to changes in vegetation height and cover which affect important components, i.e., food, shelter, movements and increased risk sensitivity in their feeding behavior; therefore, they were unable to reach levels where they cause significant crop damage. This method is recommended for being a cost-effective and easy application. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=agricultural%20ecosystems" title="agricultural ecosystems">agricultural ecosystems</a>, <a href="https://publications.waset.org/abstracts/search?q=crop%20damage" title=" crop damage"> crop damage</a>, <a href="https://publications.waset.org/abstracts/search?q=habitat%20manipulation" title=" habitat manipulation"> habitat manipulation</a>, <a href="https://publications.waset.org/abstracts/search?q=rodents" title=" rodents"> rodents</a>, <a href="https://publications.waset.org/abstracts/search?q=trapping" title=" trapping"> trapping</a> </p> <a href="https://publications.waset.org/abstracts/118265/evaluating-habitat-manipulation-as-a-strategy-for-rodent-control-in-agricultural-ecosystems-of-pothwar-region-pakistan" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/118265.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">165</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">5</span> Solid State Drive End to End Reliability Prediction, Characterization and Control</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohd%20Azman%20Abdul%20Latif">Mohd Azman Abdul Latif</a>, <a href="https://publications.waset.org/abstracts/search?q=Erwan%20Basiron"> Erwan Basiron</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A flaw or drift from expected operational performance in one component (NAND, PMIC, controller, DRAM, etc.) may affect the reliability of the entire Solid State Drive (SSD) system. Therefore, it is important to ensure the required quality of each individual component through qualification testing specified using standards or user requirements. Qualification testing is time-consuming and comes at a substantial cost for product manufacturers. A highly technical team, from all the eminent stakeholders is embarking on reliability prediction from beginning of new product development, identify critical to reliability parameters, perform full-blown characterization to embed margin into product reliability and establish control to ensure the product reliability is sustainable in the mass production. The paper will discuss a comprehensive development framework, comprehending SSD end to end from design to assembly, in-line inspection, in-line testing and will be able to predict and to validate the product reliability at the early stage of new product development. During the design stage, the SSD will go through intense reliability margin investigation with focus on assembly process attributes, process equipment control, in-process metrology and also comprehending forward looking product roadmap. Once these pillars are completed, the next step is to perform process characterization and build up reliability prediction modeling. Next, for the design validation process, the reliability prediction specifically solder joint simulator will be established. The SSD will be stratified into Non-Operating and Operating tests with focus on solder joint reliability and connectivity/component latent failures by prevention through design intervention and containment through Temperature Cycle Test (TCT). Some of the SSDs will be subjected to the physical solder joint analysis called Dye and Pry (DP) and Cross Section analysis. The result will be feedbacked to the simulation team for any corrective actions required to further improve the design. Once the SSD is validated and is proven working, it will be subjected to implementation of the monitor phase whereby Design for Assembly (DFA) rules will be updated. At this stage, the design change, process and equipment parameters are in control. Predictable product reliability at early product development will enable on-time sample qualification delivery to customer and will optimize product development validation, effective development resource and will avoid forced late investment to bandage the end-of-life product failures. Understanding the critical to reliability parameters earlier will allow focus on increasing the product margin that will increase customer confidence to product reliability. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=e2e%20reliability%20prediction" title="e2e reliability prediction">e2e reliability prediction</a>, <a href="https://publications.waset.org/abstracts/search?q=SSD" title=" SSD"> SSD</a>, <a href="https://publications.waset.org/abstracts/search?q=TCT" title=" TCT"> TCT</a>, <a href="https://publications.waset.org/abstracts/search?q=solder%20joint%20reliability" title=" solder joint reliability"> solder joint reliability</a>, <a href="https://publications.waset.org/abstracts/search?q=NUDD" title=" NUDD"> NUDD</a>, <a href="https://publications.waset.org/abstracts/search?q=connectivity%20issues" title=" connectivity issues"> connectivity issues</a>, <a href="https://publications.waset.org/abstracts/search?q=qualifications" title=" qualifications"> qualifications</a>, <a href="https://publications.waset.org/abstracts/search?q=characterization%20and%20control" title=" characterization and control "> characterization and control </a> </p> <a href="https://publications.waset.org/abstracts/135316/solid-state-drive-end-to-end-reliability-prediction-characterization-and-control" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/135316.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">174</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">4</span> Enhanced Disk-Based Databases towards Improved Hybrid in-Memory Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Samuel%20Kaspi">Samuel Kaspi</a>, <a href="https://publications.waset.org/abstracts/search?q=Sitalakshmi%20Venkatraman"> Sitalakshmi Venkatraman </a> </p> <p class="card-text"><strong>Abstract:</strong></p> In-memory database systems are becoming popular due to the availability and affordability of sufficiently large RAM and processors in modern high-end servers with the capacity to manage large in-memory database transactions. While fast and reliable in-memory systems are still being developed to overcome cache misses, CPU/IO bottlenecks and distributed transaction costs, disk-based data stores still serve as the primary persistence. In addition, with the recent growth in multi-tenancy cloud applications and associated security concerns, many organisations consider the trade-offs and continue to require fast and reliable transaction processing of disk-based database systems as an available choice. For these organizations, the only way of increasing throughput is by improving the performance of disk-based concurrency control. This warrants a hybrid database system with the ability to selectively apply an enhanced disk-based data management within the context of in-memory systems that would help improve overall throughput. The general view is that in-memory systems substantially outperform disk-based systems. We question this assumption and examine how a modified variation of access invariance that we call enhanced memory access, (EMA) can be used to allow very high levels of concurrency in the pre-fetching of data in disk-based systems. We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems. This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number of processors and their speeds. The results of the experiments conducted clearly substantiate that when used in conjunction with all concurrency control mechanisms, EMA can increase the throughput of disk-based systems to levels quite close to those achieved by in-memory system. The promising results of this work show that enhanced disk-based systems facilitate in improving hybrid data management within the broader context of in-memory systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=in-memory%20database" title="in-memory database">in-memory database</a>, <a href="https://publications.waset.org/abstracts/search?q=disk-based%20system" title=" disk-based system"> disk-based system</a>, <a href="https://publications.waset.org/abstracts/search?q=hybrid%20database" title=" hybrid database"> hybrid database</a>, <a href="https://publications.waset.org/abstracts/search?q=concurrency%20control" title=" concurrency control"> concurrency control</a> </p> <a href="https://publications.waset.org/abstracts/20941/enhanced-disk-based-databases-towards-improved-hybrid-in-memory-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20941.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">417</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">3</span> Enhanced Dielectric and Ferroelectric Properties in Holmium Substituted Stoichiometric and Non-Stoichiometric SBT Ferroelectric Ceramics</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sugandha%20Gupta">Sugandha Gupta</a>, <a href="https://publications.waset.org/abstracts/search?q=Arun%20Kumar%20Jha"> Arun Kumar Jha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A large number of ferroelectric materials have been intensely investigated for applications in non-volatile ferroelectric random access memories (FeRAMs), piezoelectric transducers, actuators, pyroelectric sensors, high dielectric constant capacitors, etc. Bismuth layered ferroelectric materials such as Strontium Bismuth Tantalate (SBT) has attracted a lot of attention due to low leakage current, high remnant polarization and high fatigue endurance up to 1012 switching cycles. However, pure SBT suffers from various major limitations such as high dielectric loss, low remnant polarization values, high processing temperature, bismuth volatilization, etc. Significant efforts have been made to improve the dielectric and ferroelectric properties of this compound. Firstly, it has been reported that electrical properties vary with the Sr/ Bi content ratio in the SrBi2Ta2O9 compsition i.e. non-stoichiometric compositions with Sr-deficient / Bi excess content have higher remnant polarization values than stoichiometic SBT compositions. With the objective to improve structural, dielectric, ferroelectric and piezoelectric properties of SBT compound, rare earth holmium (Ho3+) was chosen as a donor cation for substitution onto the Bi2O2 layer. Moreover, hardly any report on holmium substitution in stoichiometric SrBi2Ta2O9 and non-stoichiometric Sr0.8Bi2.2Ta2O9 compositions were available in the literature. The holmium substituted SrBi2-xHoxTa2O9 (x= 0.00-2.0) and Sr0.8Bi2.2Ta2O9 (x=0.0 and 0.01) compositions were synthesized by the solid state reaction method. The synthesized specimens were characterized for their structural and electrical properties. X-ray diffractograms reveal single phase layered perovskite structure formation for holmium content in stoichiometric SBT samples up to x ≤ 0.1. The granular morphology of the samples was investigated using scanning electron microscope (Hitachi, S-3700 N). The dielectric measurements were carried out using a precision LCR meter (Agilent 4284A) operating at oscillation amplitude of 1V. The variation of dielectric constant with temperature shows that the Curie temperature (Tc) decreases on increasing the holmium content. The specimen with x=2.0 i.e. the bismuth free specimen, has very low dielectric constant and does not show any appreciable variation with temperature. The dielectric loss reduces significantly with holmium substitution. The polarization–electric field (P–E) hysteresis loops were recorded using a P–E loop tracer based on Sawyer–Tower circuit. It is observed that the ferroelectric property improve with Ho substitution. Holmium substituted specimen exhibits enhanced value of remnant polarization (Pr= 9.22 μC/cm²) as compared to holmium free specimen (Pr= 2.55 μC/cm²). Piezoelectric co-efficient (d33 values) was measured using a piezo meter system (Piezo Test PM300). It is observed that holmium substitution enhances piezoelectric coefficient. Further, the optimized holmium content (x=0.01) in stoichiometric SrBi2-xHoxTa2O9 composition has been substituted in non-stoichiometric Sr0.8Bi2.2Ta2O9 composition to obtain further enhanced structural and electrical characteristics. It is expected that a new class of ferroelectric materials i.e. Rare Earth Layered Structured Ferroelectrics (RLSF) derived from Bismuth Layered Structured Ferroelectrics (BLSF) will generate which can be used to replace static (SRAM) and dynamic (DRAM) random access memories with ferroelectric random access memories (FeRAMS). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=dielectrics" title="dielectrics">dielectrics</a>, <a href="https://publications.waset.org/abstracts/search?q=ferroelectrics" title=" ferroelectrics"> ferroelectrics</a>, <a href="https://publications.waset.org/abstracts/search?q=piezoelectrics" title=" piezoelectrics"> piezoelectrics</a>, <a href="https://publications.waset.org/abstracts/search?q=strontium%20bismuth%20tantalate" title=" strontium bismuth tantalate"> strontium bismuth tantalate</a> </p> <a href="https://publications.waset.org/abstracts/58807/enhanced-dielectric-and-ferroelectric-properties-in-holmium-substituted-stoichiometric-and-non-stoichiometric-sbt-ferroelectric-ceramics" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58807.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">209</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">2</span> Pareto Optimal Material Allocation Mechanism</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Peter%20Egri">Peter Egri</a>, <a href="https://publications.waset.org/abstracts/search?q=Tamas%20Kis"> Tamas Kis</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Scheduling problems have been studied by the algorithmic mechanism design research from the beginning. This paper is focusing on a practically important, but theoretically rather neglected field: the project scheduling problem where the jobs connected by precedence constraints compete for various nonrenewable resources, such as materials. Although the centralized problem can be solved in polynomial-time by applying the algorithm of Carlier and Rinnooy Kan from the Eighties, obtaining materials in a decentralized environment is usually far from optimal. It can be observed in practical production scheduling situations that project managers tend to cache the required materials as soon as possible in order to avoid later delays due to material shortages. This greedy practice usually leads both to excess stocks for some projects and materials, and simultaneously, to shortages for others. The aim of this study is to develop a model for the material allocation problem of a production plant, where a central decision maker—the inventory—should assign the resources arriving at different points in time to the jobs. Since the actual due dates are not known by the inventory, the mechanism design approach is applied with the projects as the self-interested agents. The goal of the mechanism is to elicit the required information and allocate the available materials such that it minimizes the maximal tardiness among the projects. It is assumed that except the due dates, the inventory is familiar with every other parameters of the problem. A further requirement is that due to practical considerations monetary transfer is not allowed. Therefore a mechanism without money is sought which excludes some widely applied solutions such as the Vickrey–Clarke–Groves scheme. In this work, a type of Serial Dictatorship Mechanism (SDM) is presented for the studied problem, including a polynomial-time algorithm for computing the material allocation. The resulted mechanism is both truthful and Pareto optimal. Thus the randomization over the possible priority orderings of the projects results in a universally truthful and Pareto optimal randomized mechanism. However, it is shown that in contrast to problems like the many-to-many matching market, not every Pareto optimal solution can be generated with an SDM. In addition, no performance guarantee can be given compared to the optimal solution, therefore this approximation characteristic is investigated with experimental study. All in all, the current work studies a practically relevant scheduling problem and presents a novel truthful material allocation mechanism which eliminates the potential benefit of the greedy behavior that negatively influences the outcome. The resulted allocation is also shown to be Pareto optimal, which is the most widely used criteria describing a necessary condition for a reasonable solution. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=material%20allocation" title="material allocation">material allocation</a>, <a href="https://publications.waset.org/abstracts/search?q=mechanism%20without%20money" title=" mechanism without money"> mechanism without money</a>, <a href="https://publications.waset.org/abstracts/search?q=polynomial-time%20mechanism" title=" polynomial-time mechanism"> polynomial-time mechanism</a>, <a href="https://publications.waset.org/abstracts/search?q=project%20scheduling" title=" project scheduling"> project scheduling</a> </p> <a href="https://publications.waset.org/abstracts/68829/pareto-optimal-material-allocation-mechanism" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68829.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">333</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1</span> Embedded Semantic Segmentation Network Optimized for Matrix Multiplication Accelerator</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jaeyoung%20Lee">Jaeyoung Lee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Autonomous driving systems require high reliability to provide people with a safe and comfortable driving experience. However, despite the development of a number of vehicle sensors, it is difficult to always provide high perceived performance in driving environments that vary from time to season. The image segmentation method using deep learning, which has recently evolved rapidly, provides high recognition performance in various road environments stably. However, since the system controls a vehicle in real time, a highly complex deep learning network cannot be used due to time and memory constraints. Moreover, efficient networks are optimized for GPU environments, which degrade performance in embedded processor environments equipped simple hardware accelerators. In this paper, a semantic segmentation network, matrix multiplication accelerator network (MMANet), optimized for matrix multiplication accelerator (MMA) on Texas instrument digital signal processors (TI DSP) is proposed to improve the recognition performance of autonomous driving system. The proposed method is designed to maximize the number of layers that can be performed in a limited time to provide reliable driving environment information in real time. First, the number of channels in the activation map is fixed to fit the structure of MMA. By increasing the number of parallel branches, the lack of information caused by fixing the number of channels is resolved. Second, an efficient convolution is selected depending on the size of the activation. Since MMA is a fixed, it may be more efficient for normal convolution than depthwise separable convolution depending on memory access overhead. Thus, a convolution type is decided according to output stride to increase network depth. In addition, memory access time is minimized by processing operations only in L3 cache. Lastly, reliable contexts are extracted using the extended atrous spatial pyramid pooling (ASPP). The suggested method gets stable features from an extended path by increasing the kernel size and accessing consecutive data. In addition, it consists of two ASPPs to obtain high quality contexts using the restored shape without global average pooling paths since the layer uses MMA as a simple adder. To verify the proposed method, an experiment is conducted using perfsim, a timing simulator, and the Cityscapes validation sets. The proposed network can process an image with 640 x 480 resolution for 6.67 ms, so six cameras can be used to identify the surroundings of the vehicle as 20 frame per second (FPS). In addition, it achieves 73.1% mean intersection over union (mIoU) which is the highest recognition rate among embedded networks on the Cityscapes validation set. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=edge%20network" title="edge network">edge network</a>, <a href="https://publications.waset.org/abstracts/search?q=embedded%20network" title=" embedded network"> embedded network</a>, <a href="https://publications.waset.org/abstracts/search?q=MMA" title=" MMA"> MMA</a>, <a href="https://publications.waset.org/abstracts/search?q=matrix%20multiplication%20accelerator" title=" matrix multiplication accelerator"> matrix multiplication accelerator</a>, <a href="https://publications.waset.org/abstracts/search?q=semantic%20segmentation%20network" title=" semantic segmentation network"> semantic segmentation network</a> </p> <a href="https://publications.waset.org/abstracts/125967/embedded-semantic-segmentation-network-optimized-for-matrix-multiplication-accelerator" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/125967.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">129</span> </span> </div> </div> </div> </main> <footer> <div id="infolinks" class="pt-3 pb-2"> <div class="container"> <div style="background-color:#f5f5f5;" class="p-3"> <div class="row"> <div class="col-md-2"> <ul class="list-unstyled"> About <li><a href="https://waset.org/page/support">About Us</a></li> <li><a href="https://waset.org/page/support#legal-information">Legal</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/WASET-16th-foundational-anniversary.pdf">WASET celebrates its 16th foundational anniversary</a></li> </ul> </div> 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