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transistor</title> <meta name="description" content="Search results for: CMOS transistor"> <meta name="keywords" content="CMOS transistor"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none 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action="https://publications.waset.org/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="CMOS transistor"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 243</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: CMOS transistor</h1> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">243</span> A Fault-Tolerant Full Adder in Double Pass CMOS Transistor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Abdelmonaem%20Ayachi">Abdelmonaem Ayachi</a>, <a href="https://publications.waset.org/search?q=Belgacem%20Hamdi"> Belgacem Hamdi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Semiconductors" title="Semiconductors">Semiconductors</a>, <a href="https://publications.waset.org/search?q=digital%20electronics" title=" digital electronics"> digital electronics</a>, <a href="https://publications.waset.org/search?q=double%20pass%0D%0Atransistor%20technology" title=" double pass transistor technology"> double pass transistor technology</a>, <a href="https://publications.waset.org/search?q=Full%20adder" title=" Full adder"> Full adder</a>, <a href="https://publications.waset.org/search?q=fault%20tolerance." title=" fault tolerance."> fault tolerance.</a> </p> <a href="https://publications.waset.org/10003320/a-fault-tolerant-full-adder-in-double-pass-cmos-transistor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10003320/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10003320/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10003320/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10003320/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10003320/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10003320/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10003320/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10003320/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10003320/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10003320/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10003320.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2107</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">242</span> An Approach for Modeling CMOS Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Spyridon%20Nikolaidis">Spyridon Nikolaidis</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS%20gate%20modeling" title="CMOS gate modeling">CMOS gate modeling</a>, <a href="https://publications.waset.org/search?q=Inverter%20modeling" title=" Inverter modeling"> Inverter modeling</a>, <a href="https://publications.waset.org/search?q=transistor%0D%0Acurrent%20model" title=" transistor current model"> transistor current model</a>, <a href="https://publications.waset.org/search?q=timing%20model." title=" timing model."> timing model.</a> </p> <a href="https://publications.waset.org/10000015/an-approach-for-modeling-cmos-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10000015/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10000015/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10000015/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10000015/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10000015/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10000015/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10000015/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10000015/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10000015/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10000015/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10000015.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2027</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">241</span> A Novel Nano-Scaled SRAM Cell</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Arash%20Azizi%20Mazreah">Arash Azizi Mazreah</a>, <a href="https://publications.waset.org/search?q=Mohammad%20Reza%20Sahebi"> Mohammad Reza Sahebi</a>, <a href="https://publications.waset.org/search?q=Mohammad%20T.%20Manzuri%20Shalmani"> Mohammad T. Manzuri Shalmani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=SRAM%20Cell" title="SRAM Cell">SRAM Cell</a>, <a href="https://publications.waset.org/search?q=leakage%20current" title=" leakage current"> leakage current</a>, <a href="https://publications.waset.org/search?q=cell%20area." title=" cell area."> cell area.</a> </p> <a href="https://publications.waset.org/15296/a-novel-nano-scaled-sram-cell" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/15296/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/15296/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/15296/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/15296/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/15296/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/15296/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/15296/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/15296/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/15296/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/15296/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/15296.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1765</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">240</span> A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Shubhajit%20Roy%20Chowdhury">Shubhajit Roy Chowdhury</a>, <a href="https://publications.waset.org/search?q=Aritra%20Banerjee"> Aritra Banerjee</a>, <a href="https://publications.waset.org/search?q=Aniruddha%20Roy"> Aniruddha Roy</a>, <a href="https://publications.waset.org/search?q=Hiranmay%20Saha"> Hiranmay Saha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=XOR%20gate" title="XOR gate">XOR gate</a>, <a href="https://publications.waset.org/search?q=full%20adder" title=" full adder"> full adder</a>, <a href="https://publications.waset.org/search?q=improvement%20in%20speed" title=" improvement in speed"> improvement in speed</a>, <a href="https://publications.waset.org/search?q=area%20minimization" title=" area minimization"> area minimization</a>, <a href="https://publications.waset.org/search?q=transistor%20count%20minimization." title=" transistor count minimization."> transistor count minimization.</a> </p> <a href="https://publications.waset.org/1588/a-high-speed-8-transistor-full-adder-design-using-novel-3-transistor-xor-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/1588/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/1588/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/1588/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/1588/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/1588/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/1588/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/1588/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/1588/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/1588/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/1588/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/1588.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">6332</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">239</span> LFSR Counter Implementation in CMOS VLSI</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Doshi%20N.%20A.">Doshi N. A.</a>, <a href="https://publications.waset.org/search?q=Dhobale%20S.%20B."> Dhobale S. B.</a>, <a href="https://publications.waset.org/search?q=Kakade%20S.%20R."> Kakade S. R.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Chip%20technology" title="Chip technology">Chip technology</a>, <a href="https://publications.waset.org/search?q=Layout%20level" title=" Layout level"> Layout level</a>, <a href="https://publications.waset.org/search?q=LFSR" title=" LFSR"> LFSR</a>, <a href="https://publications.waset.org/search?q=Pass%20transistor" title=" Pass transistor"> Pass transistor</a> </p> <a href="https://publications.waset.org/4463/lfsr-counter-implementation-in-cmos-vlsi" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/4463/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/4463/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/4463/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/4463/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/4463/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/4463/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/4463/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/4463/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/4463/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/4463/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/4463.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">4513</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">238</span> A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Arash%20Azizi%20Mazreah">Arash Azizi Mazreah</a>, <a href="https://publications.waset.org/search?q=Mohammad%20T.%20Manzuri%20Shalmani"> Mohammad T. Manzuri Shalmani</a>, <a href="https://publications.waset.org/search?q=Hamid%20Barati"> Hamid Barati</a>, <a href="https://publications.waset.org/search?q=Ali%20Barati"> Ali Barati</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25渭m CMOS technology confirms all results obtained from this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Positive%20feedback" title="Positive feedback">Positive feedback</a>, <a href="https://publications.waset.org/search?q=leakage%20current" title=" leakage current"> leakage current</a>, <a href="https://publications.waset.org/search?q=read%20operation" title=" read operation"> read operation</a>, <a href="https://publications.waset.org/search?q=write%20operation" title=" write operation"> write operation</a>, <a href="https://publications.waset.org/search?q=dynamic%20energy%20consumption." title=" dynamic energy consumption."> dynamic energy consumption.</a> </p> <a href="https://publications.waset.org/7725/a-novel-four-transistor-sram-cell-with-low-dynamic-power-consumption" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7725/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7725/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/7725/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/7725/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/7725/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/7725/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/7725/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/7725/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/7725/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/7725/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/7725.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2859</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">237</span> A Single-chip Proportional to Absolute Temperature Sensor Using CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=AL.AL">AL.AL</a>, <a href="https://publications.waset.org/search?q=M.%20B.%20I.%20Reaz"> M. B. I. Reaz</a>, <a href="https://publications.waset.org/search?q=S.%20M.%20A.%20Motakabber"> S. M. A. Motakabber</a>, <a href="https://publications.waset.org/search?q=Mohd%20Alauddin%20Mohd%20Ali"> Mohd Alauddin Mohd Ali</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays it is a trend for electronic circuit designers to integrate all system components on a single-chip. This paper proposed the design of a single-chip proportional to absolute temperature (PTAT) sensor including a voltage reference circuit using CEDEC 0.18m CMOS Technology. It is a challenge to design asingle-chip wide range linear response temperature sensor for many applications. The channel widths between the compensation transistor and the reference transistor are critical to design the PTAT temperature sensor circuit. The designed temperature sensor shows excellent linearity between -100掳C to 200掳 and the sensitivity is about 0.05mV/掳C. The chip is designed to operate with a single voltage source of 1.6V. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=PTAT" title="PTAT">PTAT</a>, <a href="https://publications.waset.org/search?q=single-chip%20circuit" title=" single-chip circuit"> single-chip circuit</a>, <a href="https://publications.waset.org/search?q=linear%20temperature%20sensor" title=" linear temperature sensor"> linear temperature sensor</a>, <a href="https://publications.waset.org/search?q=CMOS%20technology." title=" CMOS technology."> CMOS technology.</a> </p> <a href="https://publications.waset.org/6952/a-single-chip-proportional-to-absolute-temperature-sensor-using-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/6952/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/6952/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/6952/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/6952/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/6952/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/6952/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/6952/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/6952/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/6952/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/6952/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/6952.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3431</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">236</span> A Low Power High Frequency CMOS RF Four Quadrant Analog Mixer</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=M.%20Aleshams">M. Aleshams</a>, <a href="https://publications.waset.org/search?q=A.%20Shahsavandi"> A. Shahsavandi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=RF-Mixer" title="RF-Mixer">RF-Mixer</a>, <a href="https://publications.waset.org/search?q=Multiplier" title=" Multiplier"> Multiplier</a>, <a href="https://publications.waset.org/search?q=cut-off%20frequency" title=" cut-off frequency"> cut-off frequency</a>, <a href="https://publications.waset.org/search?q=power%0Aconsumption" title=" power consumption"> power consumption</a> </p> <a href="https://publications.waset.org/4910/a-low-power-high-frequency-cmos-rf-four-quadrant-analog-mixer" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/4910/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/4910/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/4910/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/4910/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/4910/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/4910/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/4910/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/4910/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/4910/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/4910/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/4910.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2012</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">235</span> Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=M.%20Geetha%20Priya">M. Geetha Priya</a>, <a href="https://publications.waset.org/search?q=K.%20Baskaran"> K. Baskaran</a>, <a href="https://publications.waset.org/search?q=S.%20Srinivasan"> S. Srinivasan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Low%20power" title="Low power">Low power</a>, <a href="https://publications.waset.org/search?q=CMOS" title=" CMOS"> CMOS</a>, <a href="https://publications.waset.org/search?q=pass-transistor" title=" pass-transistor"> pass-transistor</a>, <a href="https://publications.waset.org/search?q=flash%20memory" title=" flash memory"> flash memory</a>, <a href="https://publications.waset.org/search?q=logic%20gates." title=" logic gates."> logic gates.</a> </p> <a href="https://publications.waset.org/9997187/robust-energy-efficient-universal-gates-for-high-performance-computer-networks-at-22nm-process-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/9997187/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/9997187/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/9997187/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/9997187/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/9997187/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/9997187/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/9997187/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/9997187/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/9997187/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/9997187/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/9997187.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2436</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">234</span> Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=N.%20Shen">N. Shen</a>, <a href="https://publications.waset.org/search?q=T.%20T.%20Le"> T. T. Le</a>, <a href="https://publications.waset.org/search?q=H.%20Y.%20Yu"> H. Y. Yu</a>, <a href="https://publications.waset.org/search?q=Z.%20X.%20Chen"> Z. X. Chen</a>, <a href="https://publications.waset.org/search?q=K.%20T.%20Win"> K. T. Win</a>, <a href="https://publications.waset.org/search?q=N.%20Singh"> N. Singh</a>, <a href="https://publications.waset.org/search?q=G.%20Q.%20Lo"> G. Q. Lo</a>, <a href="https://publications.waset.org/search?q=D.%20-L.%20Kwong"> D. -L. Kwong</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Nanowire%20%28NW%29" title="Nanowire (NW)">Nanowire (NW)</a>, <a href="https://publications.waset.org/search?q=Gate-all-around%20%28GAA%29" title=" Gate-all-around (GAA)"> Gate-all-around (GAA)</a>, <a href="https://publications.waset.org/search?q=polysilicon%20%28poly-Si%29" title=" polysilicon (poly-Si)"> polysilicon (poly-Si)</a>, <a href="https://publications.waset.org/search?q=thin-film%20transistor%20%28TFT%29." title=" thin-film transistor (TFT)."> thin-film transistor (TFT).</a> </p> <a href="https://publications.waset.org/4635/fabrication-and-characterization-of-poly-si-vertical-nanowire-thin-film-transistor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/4635/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/4635/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/4635/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/4635/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/4635/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/4635/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/4635/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/4635/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/4635/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/4635/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/4635.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2192</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">233</span> A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Jianping%20Hu">Jianping Hu</a>, <a href="https://publications.waset.org/search?q=Xiaolei%20Sheng"> Xiaolei Sheng</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32脳32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18渭m CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Low%20power" title="Low power">Low power</a>, <a href="https://publications.waset.org/search?q=Register%20file" title=" Register file"> Register file</a>, <a href="https://publications.waset.org/search?q=Complementarypass-transistor%20logic" title=" Complementarypass-transistor logic"> Complementarypass-transistor logic</a>, <a href="https://publications.waset.org/search?q=Adiabatic%20logic" title=" Adiabatic logic"> Adiabatic logic</a>, <a href="https://publications.waset.org/search?q=Single-phase%20power%20clock." title=" Single-phase power clock."> Single-phase power clock.</a> </p> <a href="https://publications.waset.org/2512/a-single-phase-register-file-with-complementary-pass-transistor-adiabatic-logic" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/2512/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/2512/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/2512/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/2512/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/2512/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/2512/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/2512/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/2512/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/2512/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/2512/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/2512.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1965</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">232</span> Versatile Dual-Mode Class-AB Four-Quadrant Analog Multiplier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Montree%20Kumngern">Montree Kumngern</a>, <a href="https://publications.waset.org/search?q=Kobchai%20Dejhan"> Kobchai Dejhan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Class-AB" title="Class-AB">Class-AB</a>, <a href="https://publications.waset.org/search?q=dual-mode%20CMOS%20analog%20multiplier" title=" dual-mode CMOS analog multiplier"> dual-mode CMOS analog multiplier</a>, <a href="https://publications.waset.org/search?q=CMOS%20analog%20integrated%20circuit" title="CMOS analog integrated circuit">CMOS analog integrated circuit</a>, <a href="https://publications.waset.org/search?q=CMOS%20translinear%20integrated%20circuit." title=" CMOS translinear integrated circuit."> CMOS translinear integrated circuit.</a> </p> <a href="https://publications.waset.org/401/versatile-dual-mode-class-ab-four-quadrant-analog-multiplier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/401/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/401/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/401/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/401/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/401/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/401/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/401/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/401/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/401/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/401/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/401.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2286</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">231</span> A 1.8 V RF CMOS Active Inductor with 0.18 um CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Siavash%20Heydarzadeh">Siavash Heydarzadeh</a>, <a href="https://publications.waset.org/search?q=Massoud%20Dousti"> Massoud Dousti</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS%20active%20inductor" title="CMOS active inductor ">CMOS active inductor </a>, <a href="https://publications.waset.org/search?q=0.18um%20CMOS%20technology" title=" 0.18um CMOS technology "> 0.18um CMOS technology </a>, <a href="https://publications.waset.org/search?q=ADS" title=" ADS"> ADS</a> </p> <a href="https://publications.waset.org/7310/a-18-v-rf-cmos-active-inductor-with-018-um-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7310/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7310/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/7310/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/7310/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/7310/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/7310/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/7310/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/7310/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/7310/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/7310/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/7310.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3334</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">230</span> High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Yngvar%20Berg">Yngvar Berg</a>, <a href="https://publications.waset.org/search?q=Omid%20Mirmotahari"> Omid Mirmotahari</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Low-voltage" title="Low-voltage">Low-voltage</a>, <a href="https://publications.waset.org/search?q=high-speed" title=" high-speed"> high-speed</a>, <a href="https://publications.waset.org/search?q=NAND" title=" NAND"> NAND</a>, <a href="https://publications.waset.org/search?q=NOR" title=" NOR"> NOR</a>, <a href="https://publications.waset.org/search?q=CMOS." title=" CMOS."> CMOS.</a> </p> <a href="https://publications.waset.org/852/high-speed-and-ultra-low-voltage-cmos-nand-and-nor-domino-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/852/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/852/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/852/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/852/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/852/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/852/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/852/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/852/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/852/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/852/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/852.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2553</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">229</span> Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Ankit%20Mitra">Ankit Mitra</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/search?q=TSPC" title=" TSPC"> TSPC</a>, <a href="https://publications.waset.org/search?q=MTCMOS" title=" MTCMOS"> MTCMOS</a>, <a href="https://publications.waset.org/search?q=ALU" title=" ALU"> ALU</a>, <a href="https://publications.waset.org/search?q=Clock%20gating" title=" Clock gating"> Clock gating</a>, <a href="https://publications.waset.org/search?q=power%20gating" title=" power gating"> power gating</a>, <a href="https://publications.waset.org/search?q=pipelining." title=" pipelining."> pipelining.</a> </p> <a href="https://publications.waset.org/9997712/design-and-analysis-of-a-low-power-high-speed-1-bit-full-adder-cell-based-on-tspc-logic-with-multi-threshold-cmos" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/9997712/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/9997712/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/9997712/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/9997712/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/9997712/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/9997712/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/9997712/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/9997712/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/9997712/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/9997712/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/9997712.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3073</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">228</span> Design and Analysis of Low-Power, High Speed and Area Efficient 2-Bit Digital Magnitude Comparator in 90nm CMOS Technology Using Gate Diffusion Input</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Fasil%20Endalamaw">Fasil Endalamaw</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Efficient" title="Efficient">Efficient</a>, <a href="https://publications.waset.org/search?q=gate%20diffusion%20input" title=" gate diffusion input"> gate diffusion input</a>, <a href="https://publications.waset.org/search?q=high%20speed" title=" high speed"> high speed</a>, <a href="https://publications.waset.org/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/search?q=CMOS." title=" CMOS."> CMOS.</a> </p> <a href="https://publications.waset.org/10012573/design-and-analysis-of-low-power-high-speed-and-area-efficient-2-bit-digital-magnitude-comparator-in-90nm-cmos-technology-using-gate-diffusion-input" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10012573/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10012573/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10012573/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10012573/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10012573/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10012573/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10012573/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10012573/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10012573/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10012573/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10012573.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">445</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">227</span> Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Yuzman%20Yusoff">Yuzman Yusoff</a>, <a href="https://publications.waset.org/search?q=Siti%20Noor%20Harun"> Siti Noor Harun</a>, <a href="https://publications.waset.org/search?q=Noor%20Shelida%20Sallehand%20Tan%20Kong%20Yew"> Noor Shelida Sallehand Tan Kong Yew</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Readout%20interface%20circuit%20%28ROIC%29" title="Readout interface circuit (ROIC)">Readout interface circuit (ROIC)</a>, <a href="https://publications.waset.org/search?q=analog%20interface%20circuit" title=" analog interface circuit"> analog interface circuit</a>, <a href="https://publications.waset.org/search?q=ion%20sensitive%20field%20effect%20transistor%20%28ISFET%29" title=" ion sensitive field effect transistor (ISFET)"> ion sensitive field effect transistor (ISFET)</a>, <a href="https://publications.waset.org/search?q=ion%20selective%20electrode%20%28ISE%29" title=" ion selective electrode (ISE)"> ion selective electrode (ISE)</a>, <a href="https://publications.waset.org/search?q=and%20ion%20sensor%20electronics." title=" and ion sensor electronics."> and ion sensor electronics.</a> </p> <a href="https://publications.waset.org/17148/design-and-characterization-of-cmos-readout-circuit-for-isfet-and-ise-based-sensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/17148/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/17148/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/17148/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/17148/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/17148/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/17148/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/17148/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/17148/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/17148/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/17148/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/17148.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2653</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">226</span> Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Yuzman%20Yusoff">Yuzman Yusoff</a>, <a href="https://publications.waset.org/search?q=Siti%20Noor%20Harun"> Siti Noor Harun</a>, <a href="https://publications.waset.org/search?q=Noor%20Shelida%20Sallehand"> Noor Shelida Sallehand</a>, <a href="https://publications.waset.org/search?q=Tan%20Kong%20Yew"> Tan Kong Yew</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Readout%20interface%20circuit%20%28ROIC%29" title="Readout interface circuit (ROIC)">Readout interface circuit (ROIC)</a>, <a href="https://publications.waset.org/search?q=analog%20interface%0D%0Acircuit" title=" analog interface circuit"> analog interface circuit</a>, <a href="https://publications.waset.org/search?q=ion%20sensitive%20field%20effect%20transistor%20%28ISFET%29" title=" ion sensitive field effect transistor (ISFET)"> ion sensitive field effect transistor (ISFET)</a>, <a href="https://publications.waset.org/search?q=ion%20selective%0D%0Aelectrode%20%28ISE%29" title=" ion selective electrode (ISE)"> ion selective electrode (ISE)</a>, <a href="https://publications.waset.org/search?q=ion%20sensor%20electronics." title=" ion sensor electronics."> ion sensor electronics.</a> </p> <a href="https://publications.waset.org/10001593/design-and-characterization-of-cmos-readout-circuit-for-isfet-and-ise-based-sensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10001593/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10001593/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10001593/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10001593/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10001593/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10001593/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10001593/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10001593/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10001593/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10001593/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10001593.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2064</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">225</span> A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=T.%20Vigneswaran">T. Vigneswaran</a>, <a href="https://publications.waset.org/search?q=B.%20Mukundhan"> B. Mukundhan</a>, <a href="https://publications.waset.org/search?q=P.%20Subbarami%20Reddy"> P. Subbarami Reddy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Arithmetic%20circuit" title="Arithmetic circuit">Arithmetic circuit</a>, <a href="https://publications.waset.org/search?q=full%20adder" title=" full adder"> full adder</a>, <a href="https://publications.waset.org/search?q=multiplier" title=" multiplier"> multiplier</a>, <a href="https://publications.waset.org/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/search?q=very%20Large-scale%20integration%20%28VLSI%29." title="very Large-scale integration (VLSI).">very Large-scale integration (VLSI).</a> </p> <a href="https://publications.waset.org/10516/a-novel-low-power-high-speed-14-transistor-cmos-full-adder-cell-with-50-improvement-in-threshold-loss-problem" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10516/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10516/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10516/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10516/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10516/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10516/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10516/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10516/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10516/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10516/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10516.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3959</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">224</span> Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=R%20.H.%20Talwekar">R .H. Talwekar</a>, <a href="https://publications.waset.org/search?q=S.%20S%20Limaye"> S. S Limaye</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Charge%20pump%20%28CP%29%20Orthogonal%20frequency%20divisionmultiplexing%20%28OFDM%29" title="Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM)">Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM)</a>, <a href="https://publications.waset.org/search?q=Phase%20locked%20loop%20%28PLL%29" title="Phase locked loop (PLL)">Phase locked loop (PLL)</a>, <a href="https://publications.waset.org/search?q=Phase%20frequencydetector%20%28PFD%29" title=" Phase frequencydetector (PFD)"> Phase frequencydetector (PFD)</a>, <a href="https://publications.waset.org/search?q=Voltage%20controlled%20oscillator%20%28VCO%29" title=" Voltage controlled oscillator (VCO)"> Voltage controlled oscillator (VCO)</a>, <a href="https://publications.waset.org/search?q=" title=""></a> </p> <a href="https://publications.waset.org/2445/design-of-high-gain-high-bandwidth-op-amp-for-reduction-of-mismatch-currents-in-charge-pump-pll-in-180-nm-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/2445/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/2445/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/2445/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/2445/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/2445/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/2445/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/2445/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/2445/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/2445/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/2445/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/2445.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3448</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">223</span> A High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=P.%20Asadee">P. Asadee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=adder" title="adder">adder</a>, <a href="https://publications.waset.org/search?q=CMOS" title=" CMOS"> CMOS</a>, <a href="https://publications.waset.org/search?q=counter" title=" counter"> counter</a>, <a href="https://publications.waset.org/search?q=Dadda%20tree" title=" Dadda tree"> Dadda tree</a>, <a href="https://publications.waset.org/search?q=encoder." title=" encoder."> encoder.</a> </p> <a href="https://publications.waset.org/10409/a-high-speed-multiplication-algorithm-using-modified-partial-product-reduction-tree" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10409/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10409/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10409/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10409/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10409/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10409/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10409/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10409/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10409/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10409/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10409.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2303</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">222</span> Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=H.%20Daoud%20Dammak">H. Daoud Dammak</a>, <a href="https://publications.waset.org/search?q=S.%20Bensalem"> S. Bensalem</a>, <a href="https://publications.waset.org/search?q=S.%20Zouari"> S. Zouari</a>, <a href="https://publications.waset.org/search?q=M.%20Loulou"> M. Loulou</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35渭m CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS%20IC%20design" title="CMOS IC design">CMOS IC design</a>, <a href="https://publications.waset.org/search?q=Folded%20Cascode%20OTA" title=" Folded Cascode OTA"> Folded Cascode OTA</a>, <a href="https://publications.waset.org/search?q=gm%2FID%0Amethodology" title=" gm/ID methodology"> gm/ID methodology</a>, <a href="https://publications.waset.org/search?q=optimization." title=" optimization."> optimization.</a> </p> <a href="https://publications.waset.org/7027/design-of-folded-cascode-ota-in-different-regions-of-operation-through-gmid-methodology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7027/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7027/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/7027/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/7027/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/7027/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/7027/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/7027/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/7027/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/7027/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/7027/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/7027.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">11726</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">221</span> Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Zina%20Saheb">Zina Saheb</a>, <a href="https://publications.waset.org/search?q=Ezz%20El-Masry"> Ezz El-Masry</a> </p> <p class="card-text"><strong>Abstract:</strong></p> As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS%20transistor" title="CMOS transistor">CMOS transistor</a>, <a href="https://publications.waset.org/search?q=direct-tunneling%20current" title=" direct-tunneling current"> direct-tunneling current</a>, <a href="https://publications.waset.org/search?q=floatinggate" title=" floatinggate"> floatinggate</a>, <a href="https://publications.waset.org/search?q=gate-leakage%20current" title=" gate-leakage current"> gate-leakage current</a>, <a href="https://publications.waset.org/search?q=simulation%20model." title=" simulation model."> simulation model.</a> </p> <a href="https://publications.waset.org/10002183/practical-simulation-model-of-floating-gate-mos-transistor-in-sub-100nm-technologies" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10002183/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10002183/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10002183/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10002183/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10002183/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10002183/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10002183/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10002183/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10002183/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10002183/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10002183.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2990</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">220</span> Design of a CMOS Differential Operational Transresistance Amplifier in 90 nm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Hafiz%20Muhammad%20Obaid">Hafiz Muhammad Obaid</a>, <a href="https://publications.waset.org/search?q=Umais%20Tayyab"> Umais Tayyab</a>, <a href="https://publications.waset.org/search?q=Shabbir%20Majeed%20Ch."> Shabbir Majeed Ch.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/search?q=differential" title=" differential"> differential</a>, <a href="https://publications.waset.org/search?q=operational%20transresistance%20amplifier" title=" operational transresistance amplifier"> operational transresistance amplifier</a>, <a href="https://publications.waset.org/search?q=OTRA" title=" OTRA"> OTRA</a>, <a href="https://publications.waset.org/search?q=90%20nm" title=" 90 nm"> 90 nm</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI. "> VLSI. </a> </p> <a href="https://publications.waset.org/10007961/design-of-a-cmos-differential-operational-transresistance-amplifier-in-90-nm-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10007961/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10007961/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10007961/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10007961/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10007961/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10007961/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10007961/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10007961/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10007961/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10007961/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10007961.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1139</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">219</span> Algorithm Design and Performance Evaluation of Equivalent CMOS Model</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Parvinder%20S.%20Sandhu">Parvinder S. Sandhu</a>, <a href="https://publications.waset.org/search?q=Iqbaldeep%20Kaur"> Iqbaldeep Kaur</a>, <a href="https://publications.waset.org/search?q=Amit%20Verma"> Amit Verma</a>, <a href="https://publications.waset.org/search?q=Inderpreet%20Kaur"> Inderpreet Kaur</a>, <a href="https://publications.waset.org/search?q=Birinderjit%20S.%20Kalyan"> Birinderjit S. Kalyan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work is a proposed model of CMOS for which the algorithm has been created and then the performance evaluation of this proposition has been done. In this context, another commonly used model called ZSTT (Zero Switching Time Transient) model is chosen to compare all the vital features and the results for the Proposed Equivalent CMOS are promising. In the end, the excerpts of the created algorithm are also included <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Dual%20Capacitor%20Model" title="Dual Capacitor Model">Dual Capacitor Model</a>, <a href="https://publications.waset.org/search?q=ZSTT" title=" ZSTT"> ZSTT</a>, <a href="https://publications.waset.org/search?q=CMOS" title=" CMOS"> CMOS</a>, <a href="https://publications.waset.org/search?q=SPICEMacro-Model." title=" SPICEMacro-Model."> SPICEMacro-Model.</a> </p> <a href="https://publications.waset.org/14943/algorithm-design-and-performance-evaluation-of-equivalent-cmos-model" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/14943/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/14943/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/14943/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/14943/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/14943/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/14943/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/14943/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/14943/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/14943/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/14943/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/14943.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1331</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">218</span> A Novel Low Power Digitally Controlled Oscillator with Improved linear Operating Range</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Nasser%20Erfani%20Majd">Nasser Erfani Majd</a>, <a href="https://publications.waset.org/search?q=Mojtaba%20Lotfizad"> Mojtaba Lotfizad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=digitally%20controlled%20oscillator%20%28DCO%29" title="digitally controlled oscillator (DCO)">digitally controlled oscillator (DCO)</a>, <a href="https://publications.waset.org/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/search?q=jitter%3B%20good%20linearity" title="jitter; good linearity">jitter; good linearity</a>, <a href="https://publications.waset.org/search?q=robust" title=" robust"> robust</a> </p> <a href="https://publications.waset.org/6238/a-novel-low-power-digitally-controlled-oscillator-with-improved-linear-operating-range" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/6238/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/6238/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/6238/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/6238/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/6238/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/6238/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/6238/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/6238/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/6238/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/6238/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/6238.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1910</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">217</span> The Design of PFM Mode DC-DC Converter with DT-CMOS Switch</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Jae-Chang%20Kwak">Jae-Chang Kwak</a>, <a href="https://publications.waset.org/search?q=Yong-Seo%20Koo"> Yong-Seo Koo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=DT-CMOS" title="DT-CMOS">DT-CMOS</a>, <a href="https://publications.waset.org/search?q=PMIC" title=" PMIC"> PMIC</a>, <a href="https://publications.waset.org/search?q=PFM" title=" PFM"> PFM</a>, <a href="https://publications.waset.org/search?q=DC-DC%20converter." title=" DC-DC converter."> DC-DC converter.</a> </p> <a href="https://publications.waset.org/9999074/the-design-of-pfm-mode-dc-dc-converter-with-dt-cmos-switch" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/9999074/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/9999074/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/9999074/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/9999074/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/9999074/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/9999074/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/9999074/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/9999074/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/9999074/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/9999074/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/9999074.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3203</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">216</span> Characterization of Responsivity, Sensitivity and Spectral Response in Thin Film SOI photo-BJMOS -FET Compatible with CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Hai-Qing%20Xie">Hai-Qing Xie</a>, <a href="https://publications.waset.org/search?q=Yun%20Zeng"> Yun Zeng</a>, <a href="https://publications.waset.org/search?q=Yong-Hong%20Yan"> Yong-Hong Yan</a>, <a href="https://publications.waset.org/search?q=Jian-Ping%20Zeng"> Jian-Ping Zeng</a>, <a href="https://publications.waset.org/search?q=Tai-Hong%20Wang"> Tai-Hong Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10脳10渭m2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Photo-BJMOSFET" title="Photo-BJMOSFET">Photo-BJMOSFET</a>, <a href="https://publications.waset.org/search?q=Responsivity" title=" Responsivity"> Responsivity</a>, <a href="https://publications.waset.org/search?q=Sensitivity" title=" Sensitivity"> Sensitivity</a>, <a href="https://publications.waset.org/search?q=Spectral%20response." title=" Spectral response."> Spectral response.</a> </p> <a href="https://publications.waset.org/14819/characterization-of-responsivity-sensitivity-and-spectral-response-in-thin-film-soi-photo-bjmos-fet-compatible-with-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/14819/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/14819/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/14819/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/14819/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/14819/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/14819/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/14819/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/14819/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/14819/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/14819/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/14819.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1539</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">215</span> Vertical GAA Silicon Nanowire Transistor with Impact of Temperature on Device Parameters</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=N.%20Shen">N. Shen</a>, <a href="https://publications.waset.org/search?q=Z.%20X.%20Chen"> Z. X. Chen</a>, <a href="https://publications.waset.org/search?q=K.D.%20Buddharaju"> K.D. Buddharaju</a>, <a href="https://publications.waset.org/search?q=H.%20M.%20Chua"> H. M. Chua</a>, <a href="https://publications.waset.org/search?q=X.%20Li"> X. Li</a>, <a href="https://publications.waset.org/search?q=N.%20Singh"> N. Singh</a>, <a href="https://publications.waset.org/search?q=G.Q%20Lo"> G.Q Lo</a>, <a href="https://publications.waset.org/search?q=D.-L.%20Kwong"> D.-L. Kwong</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Gate-all-around" title="Gate-all-around">Gate-all-around</a>, <a href="https://publications.waset.org/search?q=temperature%20dependence" title=" temperature dependence"> temperature dependence</a>, <a href="https://publications.waset.org/search?q=silicon%20nanowire" title=" silicon nanowire"> silicon nanowire</a> </p> <a href="https://publications.waset.org/8846/vertical-gaa-silicon-nanowire-transistor-with-impact-of-temperature-on-device-parameters" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/8846/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/8846/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/8846/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/8846/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/8846/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/8846/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/8846/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/8846/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/8846/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/8846/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/8846.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1852</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">214</span> Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Hassan%20Jassim%20Motlak">Hassan Jassim Motlak</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Pseudo-OTA%20used%20CMOS%20CFOA" title="Pseudo-OTA used CMOS CFOA">Pseudo-OTA used CMOS CFOA</a>, <a href="https://publications.waset.org/search?q=low%20power%20CFOA" title=" low power CFOA"> low power CFOA</a>, <a href="https://publications.waset.org/search?q=high-performance%20CFOA" title=" high-performance CFOA"> high-performance CFOA</a>, <a href="https://publications.waset.org/search?q=novel%20CFOA." title=" novel CFOA."> novel CFOA.</a> </p> <a href="https://publications.waset.org/10001668/design-of-cmos-cfoa-based-on-pseudo-operational-transconductance-amplifier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10001668/apa" target="_blank" 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