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systems and circuits security</title> <meta name="description" content="Search results for: hardware systems and circuits security"> <meta name="keywords" content="hardware systems and circuits security"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science 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method="get" action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="hardware systems and circuits security"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 12067</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: hardware systems and circuits security</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12067</span> Importance of Hardware Systems and Circuits in Secure Software Development Life Cycle</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mir%20Shahriar%20Emami">Mir Shahriar Emami</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SDLC" title="SDLC">SDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=SSDLC" title=" SSDLC"> SSDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20security" title=" software security"> software security</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20process%20engineering" title=" software process engineering"> software process engineering</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security" title=" hardware systems and circuits security"> hardware systems and circuits security</a> </p> <a href="https://publications.waset.org/abstracts/55558/importance-of-hardware-systems-and-circuits-in-secure-software-development-life-cycle" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/55558.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">261</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12066</span> A Machine Learning Approach for Detecting and Locating Hardware Trojans</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kaiwen%20Zheng">Kaiwen Zheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Nan%20Tang"> Nan Tang</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuanhang%20He"> Yuanhang He</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%20trojans" title="hardware trojans">hardware trojans</a>, <a href="https://publications.waset.org/abstracts/search?q=physical%20properties" title=" physical properties"> physical properties</a>, <a href="https://publications.waset.org/abstracts/search?q=machine%20learning" title=" machine learning"> machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a> </p> <a href="https://publications.waset.org/abstracts/164285/a-machine-learning-approach-for-detecting-and-locating-hardware-trojans" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/164285.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">146</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12065</span> Tamper Resistance Evaluation Tests with Noise Resources</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Masaya%20Yoshikawa">Masaya Yoshikawa</a>, <a href="https://publications.waset.org/abstracts/search?q=Toshiya%20Asai"> Toshiya Asai</a>, <a href="https://publications.waset.org/abstracts/search?q=Ryoma%20Matsuhisa"> Ryoma Matsuhisa</a>, <a href="https://publications.waset.org/abstracts/search?q=Yusuke%20Nozaki"> Yusuke Nozaki</a>, <a href="https://publications.waset.org/abstracts/search?q=Kensaku%20Asahi"> Kensaku Asahi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=tamper%20resistance" title="tamper resistance">tamper resistance</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptographic%20circuit" title=" cryptographic circuit"> cryptographic circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security%20evaluation" title=" hardware security evaluation"> hardware security evaluation</a>, <a href="https://publications.waset.org/abstracts/search?q=noise%20resources" title=" noise resources "> noise resources </a> </p> <a href="https://publications.waset.org/abstracts/25852/tamper-resistance-evaluation-tests-with-noise-resources" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25852.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">504</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12064</span> Analysis of Lightweight Register Hardware Threat</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yang%20Luo">Yang Luo</a>, <a href="https://publications.waset.org/abstracts/search?q=Beibei%20Wang"> Beibei Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=side-channel%20analysis" title="side-channel analysis">side-channel analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20Trojan" title=" hardware Trojan"> hardware Trojan</a>, <a href="https://publications.waset.org/abstracts/search?q=register%20transfer%20level" title=" register transfer level"> register transfer level</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20power" title=" dynamic power"> dynamic power</a> </p> <a href="https://publications.waset.org/abstracts/58138/analysis-of-lightweight-register-hardware-threat" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58138.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">279</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12063</span> Security Design of Root of Trust Based on RISC-V</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kang%20Huang">Kang Huang</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Shiwei%20Yuan"> Shiwei Yuan</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Since information technology develops rapidly, the security issue has become an increasingly critical for computer system. In particular, as cloud computing and the Internet of Things (IoT) continue to gain widespread adoption, computer systems need to new security threats and attacks. The Root of Trust (RoT) is the foundation for providing basic trusted computing, which is used to verify the security and trustworthiness of other components. Design a reliable Root of Trust and guarantee its own security are essential for improving the overall security and credibility of computer systems. In this paper, we discuss the implementation of self-security technology based on the RISC-V Root of Trust at the hardware level. To effectively safeguard the security of the Root of Trust, researches on security safeguard technology on the Root of Trust have been studied. At first, a lightweight and secure boot framework is proposed as a secure mechanism. Secondly, two kinds of memory protection mechanism are built to against memory attacks. Moreover, hardware implementation of proposed method has been also investigated. A series of experiments and tests have been carried on to verify to effectiveness of the proposed method. The experimental results demonstrated that the proposed approach is effective in verifying the integrity of the Root of Trust’s own boot rom, user instructions, and data, ensuring authenticity and enabling the secure boot of the Root of Trust’s own system. Additionally, our approach provides memory protection against certain types of memory attacks, such as cache leaks and tampering, and ensures the security of root-of-trust sensitive information, including keys. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=root%20of%20trust" title="root of trust">root of trust</a>, <a href="https://publications.waset.org/abstracts/search?q=secure%20boot" title=" secure boot"> secure boot</a>, <a href="https://publications.waset.org/abstracts/search?q=memory%20protection" title=" memory protection"> memory protection</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a> </p> <a href="https://publications.waset.org/abstracts/164581/security-design-of-root-of-trust-based-on-risc-v" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/164581.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">215</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12062</span> Numerical Solution Speedup of the Laplace Equation Using FPGA Hardware</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abbas%20Ebrahimi">Abbas Ebrahimi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Zandsalimy"> Mohammad Zandsalimy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=accelerating%20numerical%20solutions" title="accelerating numerical solutions">accelerating numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=CFD" title=" CFD"> CFD</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20definition%20language" title=" hardware definition language"> hardware definition language</a>, <a href="https://publications.waset.org/abstracts/search?q=numerical%20solutions" title=" numerical solutions"> numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20hardware" title=" reconfigurable hardware"> reconfigurable hardware</a> </p> <a href="https://publications.waset.org/abstracts/68002/numerical-solution-speedup-of-the-laplace-equation-using-fpga-hardware" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68002.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">382</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12061</span> Two Kinds of Self-Oscillating Circuits Mechanically Demonstrated</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shiang-Hwua%20Yu">Shiang-Hwua Yu</a>, <a href="https://publications.waset.org/abstracts/search?q=Po-Hsun%20Wu"> Po-Hsun Wu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=self-oscillation" title="self-oscillation">self-oscillation</a>, <a href="https://publications.waset.org/abstracts/search?q=sigma-delta%20modulator" title=" sigma-delta modulator"> sigma-delta modulator</a>, <a href="https://publications.waset.org/abstracts/search?q=pendulum%20clock" title=" pendulum clock"> pendulum clock</a>, <a href="https://publications.waset.org/abstracts/search?q=Coulomb%20friction" title=" Coulomb friction"> Coulomb friction</a>, <a href="https://publications.waset.org/abstracts/search?q=class-D%20amplifier" title=" class-D amplifier"> class-D amplifier</a> </p> <a href="https://publications.waset.org/abstracts/9932/two-kinds-of-self-oscillating-circuits-mechanically-demonstrated" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/9932.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">356</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12060</span> Optimization and Design of Current-Mode Multiplier Circuits with Applications in Analog Signal Processing for Gas Industrial Package Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohamad%20Baqer%20Heidari">Mohamad Baqer Heidari</a>, <a href="https://publications.waset.org/abstracts/search?q=Hefzollah.Mohammadian"> Hefzollah.Mohammadian </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20signal%20processing" title="analog signal processing">analog signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=current-mode%20%20operation" title=" current-mode operation"> current-mode operation</a>, <a href="https://publications.waset.org/abstracts/search?q=functional%20core" title=" functional core"> functional core</a>, <a href="https://publications.waset.org/abstracts/search?q=multiplier" title=" multiplier"> multiplier</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20circuits" title=" reconfigurable circuits"> reconfigurable circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=industrial%20package%20systems" title=" industrial package systems"> industrial package systems</a> </p> <a href="https://publications.waset.org/abstracts/36406/optimization-and-design-of-current-mode-multiplier-circuits-with-applications-in-analog-signal-processing-for-gas-industrial-package-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/36406.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">374</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12059</span> An Effective Route to Control of the Safety of Accessing and Storing Data in the Cloud-Based Data Base</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Omid%20%20Khodabakhshi">Omid Khodabakhshi</a>, <a href="https://publications.waset.org/abstracts/search?q=Amir%20Rozdel"> Amir Rozdel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The subject of cloud computing security research has allocated a number of challenges and competitions because the data center is comprised of complex private information and are always faced various risks of information disclosure by hacker attacks or internal enemies. Accordingly, the security of virtual machines in the cloud computing infrastructure layer is very important. So far, there are many software solutions to develop security in virtual machines. But using software alone is not enough to solve security problems. The purpose of this article is to examine the challenges and security requirements for accessing and storing data in an insecure cloud environment. In other words, in this article, a structure is proposed for the implementation of highly isolated security-sensitive codes using secure computing hardware in virtual environments. It also allows remote code validation with inputs and outputs. We provide these security features even in situations where the BIOS, the operating system, and even the super-supervisor are infected. To achieve these goals, we will use the hardware support provided by the new Intel and AMD processors, as well as the TPM security chip. In conclusion, the use of these technologies ultimately creates a root of dynamic trust and reduces TCB to security-sensitive codes. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=code" title="code">code</a>, <a href="https://publications.waset.org/abstracts/search?q=cloud%20computing" title=" cloud computing"> cloud computing</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=virtual%20machines" title=" virtual machines"> virtual machines</a> </p> <a href="https://publications.waset.org/abstracts/84007/an-effective-route-to-control-of-the-safety-of-accessing-and-storing-data-in-the-cloud-based-data-base" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/84007.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">191</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12058</span> Lightweight Hardware Firewall for Embedded System Based on Bus Transactions</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ziyuan%20Wu">Ziyuan Wu</a>, <a href="https://publications.waset.org/abstracts/search?q=Yulong%20Jia"> Yulong Jia</a>, <a href="https://publications.waset.org/abstracts/search?q=Xiang%20Zhang"> Xiang Zhang</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=IoT" title="IoT">IoT</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=SoC" title=" SoC"> SoC</a>, <a href="https://publications.waset.org/abstracts/search?q=bus%20architecture" title=" bus architecture"> bus architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=lightweight%20hardware%20firewall" title=" lightweight hardware firewall"> lightweight hardware firewall</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a> </p> <a href="https://publications.waset.org/abstracts/179081/lightweight-hardware-firewall-for-embedded-system-based-on-bus-transactions" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/179081.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">61</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12057</span> Secrecy Analysis in Downlink Cellular Networks in the Presence of D2D Pairs and Hardware Impairment</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mahdi%20Rahimi">Mahdi Rahimi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Mahdi%20Mojahedian"> Mohammad Mahdi Mojahedian</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Reza%20Aref"> Mohammad Reza Aref</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a cellular communication scenario with a transmitter and an authorized user is considered to analyze its secrecy in the face of eavesdroppers and the interferences propagated unintentionally through the communication network. It is also assumed that some D2D pairs and eavesdroppers are randomly located in the cell. Assuming hardware impairment, perfect connection probability is analytically calculated, and upper bound is provided for the secrecy outage probability. In addition, a method based on random activation of D2Ds is proposed to improve network security. Finally, the analytical results are verified by simulations. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=physical%20layer%20security" title="physical layer security">physical layer security</a>, <a href="https://publications.waset.org/abstracts/search?q=stochastic%20geometry" title=" stochastic geometry"> stochastic geometry</a>, <a href="https://publications.waset.org/abstracts/search?q=device-to-device" title=" device-to-device"> device-to-device</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20impairment" title=" hardware impairment"> hardware impairment</a> </p> <a href="https://publications.waset.org/abstracts/148278/secrecy-analysis-in-downlink-cellular-networks-in-the-presence-of-d2d-pairs-and-hardware-impairment" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/148278.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">180</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12056</span> Evolving Digital Circuits for Early Stage Breast Cancer Detection Using Cartesian Genetic Programming</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zahra%20Khalid">Zahra Khalid</a>, <a href="https://publications.waset.org/abstracts/search?q=Gul%20Muhammad%20Khan"> Gul Muhammad Khan</a>, <a href="https://publications.waset.org/abstracts/search?q=Arbab%20Masood%20Ahmad"> Arbab Masood Ahmad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Cartesian Genetic Programming (CGP) is explored to design an optimal circuit capable of early stage breast cancer detection. CGP is used to evolve simple multiplexer circuits for detection of malignancy in the Fine Needle Aspiration (FNA) samples of breast. The data set used is extracted from Wisconsins Breast Cancer Database (WBCD). A range of experiments were performed, each with different set of network parameters. The best evolved network detected malignancy with an accuracy of 99.14%, which is higher than that produced with most of the contemporary non-linear techniques that are computational expensive than the proposed system. The evolved network comprises of simple multiplexers and can be implemented easily in hardware without any further complications or inaccuracy, being the digital circuit. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=breast%20cancer%20detection" title="breast cancer detection">breast cancer detection</a>, <a href="https://publications.waset.org/abstracts/search?q=cartesian%20genetic%20programming" title=" cartesian genetic programming"> cartesian genetic programming</a>, <a href="https://publications.waset.org/abstracts/search?q=evolvable%20hardware" title=" evolvable hardware"> evolvable hardware</a>, <a href="https://publications.waset.org/abstracts/search?q=fine%20needle%20aspiration" title=" fine needle aspiration"> fine needle aspiration</a> </p> <a href="https://publications.waset.org/abstracts/96036/evolving-digital-circuits-for-early-stage-breast-cancer-detection-using-cartesian-genetic-programming" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/96036.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">216</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12055</span> Hardware Error Analysis and Severity Characterization in Linux-Based Server Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nikolaos%20Georgoulopoulos">Nikolaos Georgoulopoulos</a>, <a href="https://publications.waset.org/abstracts/search?q=Alkis%20Hatzopoulos"> Alkis Hatzopoulos</a>, <a href="https://publications.waset.org/abstracts/search?q=Konstantinos%20Karamitsios"> Konstantinos Karamitsios</a>, <a href="https://publications.waset.org/abstracts/search?q=Konstantinos%20Kotrotsios"> Konstantinos Kotrotsios</a>, <a href="https://publications.waset.org/abstracts/search?q=Alexandros%20I.%20Metsai"> Alexandros I. Metsai</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In modern server systems, business critical applications run in different types of infrastructure, such as cloud systems, physical machines and virtualization. Often, due to high load and over time, various hardware faults occur in servers that translate to errors, resulting to malfunction or even server breakdown. CPU, RAM and hard drive (HDD) are the hardware parts that concern server administrators the most regarding errors. In this work, selected RAM, HDD and CPU errors, that have been observed or can be simulated in kernel ring buffer log files from two groups of Linux servers, are investigated. Moreover, a severity characterization is given for each error type. Better understanding of such errors can lead to more efficient analysis of kernel logs that are usually exploited for fault diagnosis and prediction. In addition, this work summarizes ways of simulating hardware errors in RAM and HDD, in order to test the error detection and correction mechanisms of a Linux server. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%20errors" title="hardware errors">hardware errors</a>, <a href="https://publications.waset.org/abstracts/search?q=Kernel%20logs" title=" Kernel logs"> Kernel logs</a>, <a href="https://publications.waset.org/abstracts/search?q=Linux%20servers" title=" Linux servers"> Linux servers</a>, <a href="https://publications.waset.org/abstracts/search?q=RAM" title=" RAM"> RAM</a>, <a href="https://publications.waset.org/abstracts/search?q=hard%20disk" title=" hard disk"> hard disk</a>, <a href="https://publications.waset.org/abstracts/search?q=CPU" title=" CPU"> CPU</a> </p> <a href="https://publications.waset.org/abstracts/140496/hardware-error-analysis-and-severity-characterization-in-linux-based-server-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/140496.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">154</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12054</span> Memristor-A Promising Candidate for Neural Circuits in Neuromorphic Computing Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Juhi%20Faridi">Juhi Faridi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohd.%20Ajmal%20Kafeel"> Mohd. Ajmal Kafeel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20circuits" title="analog circuits">analog circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=digital%20circuits" title=" digital circuits"> digital circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=memristors" title=" memristors"> memristors</a>, <a href="https://publications.waset.org/abstracts/search?q=neuromorphic%20computing%20systems" title=" neuromorphic computing systems"> neuromorphic computing systems</a> </p> <a href="https://publications.waset.org/abstracts/100057/memristor-a-promising-candidate-for-neural-circuits-in-neuromorphic-computing-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/100057.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">174</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12053</span> One Period Loops of Memristive Circuits with Mixed-Mode Oscillations</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Wieslaw%20Marszalek">Wieslaw Marszalek</a>, <a href="https://publications.waset.org/abstracts/search?q=Zdzislaw%20Trzaska"> Zdzislaw Trzaska</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mixed-mode%20oscillations" title="mixed-mode oscillations">mixed-mode oscillations</a>, <a href="https://publications.waset.org/abstracts/search?q=memristive%20circuits" title=" memristive circuits"> memristive circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=pinched%20hysteresis" title=" pinched hysteresis"> pinched hysteresis</a>, <a href="https://publications.waset.org/abstracts/search?q=one-period%20loops" title=" one-period loops"> one-period loops</a>, <a href="https://publications.waset.org/abstracts/search?q=singularly%20perturbed%20circuits" title=" singularly perturbed circuits"> singularly perturbed circuits</a> </p> <a href="https://publications.waset.org/abstracts/20949/one-period-loops-of-memristive-circuits-with-mixed-mode-oscillations" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20949.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">470</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12052</span> Safety-Security Co-Engineering of Control Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Elena%20A.%20Troubitsyna">Elena A. Troubitsyna</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Designers of modern safety-critical control systems are increasingly relying on networking to provide the systems with advanced functionality and satisfy customer’s needs. However, networking nature of modern control systems also brings new technological challenges associated with ensuring system safety in the presence of openness and hence, potential security threats. In this paper, we propose a methodology that relies on systems-theoretic analysis to enable an integrated analysis of safety and security requirements of controlling software. We demonstrate how to create a safety case – a structured argument about system safety – with explicit representation of both safety and security goals. Our approach provides the designers with a systematic approach to analysing safety and security interdependencies while designing safety-critical control systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=controlling%20software" title="controlling software">controlling software</a>, <a href="https://publications.waset.org/abstracts/search?q=integrated%20analysis" title=" integrated analysis"> integrated analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=safety-security%20co-engineering" title=" safety-security co-engineering"> safety-security co-engineering</a> </p> <a href="https://publications.waset.org/abstracts/80090/safety-security-co-engineering-of-control-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/80090.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">497</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12051</span> The Benefits of Security Culture for Improving Physical Protection Systems at Detection and Radiation Measurement Laboratory</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ari%20S.%20Prabowo">Ari S. Prabowo</a>, <a href="https://publications.waset.org/abstracts/search?q=Nia%20Febriyanti"> Nia Febriyanti</a>, <a href="https://publications.waset.org/abstracts/search?q=Haryono%20B.%20Santosa"> Haryono B. Santosa</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Security function that is called as Physical Protection Systems (PPS) has functions to detect, delay and response. Physical Protection Systems (PPS) in Detection and Radiation Measurement Laboratory needs to be improved continually by using internal resources. The nuclear security culture provides some potentials to support this research. The study starts by identifying the security function’s weaknesses and its strengths of security culture as a purpose. Secondly, the strengths of security culture are implemented in the laboratory management. Finally, a simulation was done to measure its effectiveness. Some changes were happened in laboratory personnel behaviors and procedures. All became more prudent. The results showed a good influence of nuclear security culture in laboratory security functions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=laboratory" title="laboratory">laboratory</a>, <a href="https://publications.waset.org/abstracts/search?q=physical%20protection%20system" title=" physical protection system"> physical protection system</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20culture" title=" security culture"> security culture</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20function" title=" security function"> security function</a> </p> <a href="https://publications.waset.org/abstracts/102746/the-benefits-of-security-culture-for-improving-physical-protection-systems-at-detection-and-radiation-measurement-laboratory" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/102746.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">185</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12050</span> Enhancing the Network Security with Gray Code</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Thomas%20Adi%20Purnomo%20Sidhi">Thomas Adi Purnomo Sidhi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays, network is an essential need in almost every part of human daily activities. People now can seamlessly connect to others through the Internet. With advanced technology, our personal data now can be more easily accessed. One of many components we are concerned for delivering the best network is a security issue. This paper is proposing a method that provides more options for security. This research aims to improve network security by focusing on the physical layer which is the first layer of the OSI model. The layer consists of the basic networking hardware transmission technologies of a network. With the use of observation method, the research produces a schematic design for enhancing the network security through the gray code converter. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=network" title="network">network</a>, <a href="https://publications.waset.org/abstracts/search?q=network%20security" title=" network security"> network security</a>, <a href="https://publications.waset.org/abstracts/search?q=grey%20code" title=" grey code"> grey code</a>, <a href="https://publications.waset.org/abstracts/search?q=physical%20layer" title=" physical layer"> physical layer</a> </p> <a href="https://publications.waset.org/abstracts/41361/enhancing-the-network-security-with-gray-code" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/41361.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">503</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12049</span> Lockit: A Logic Locking Automation Software</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nemanja%20Kajtez">Nemanja Kajtez</a>, <a href="https://publications.waset.org/abstracts/search?q=Yue%20Zhan"> Yue Zhan</a>, <a href="https://publications.waset.org/abstracts/search?q=Basel%20Halak"> Basel Halak</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The significant rise in the cost of manufacturing of nanoscale integrated circuits (IC) has led the majority of IC design companies to outsource the fabrication of their products to other companies, often located in different countries. This multinational nature of the hardware supply chain has led to a host of security threats, including IP piracy, IC overproduction, and Trojan insertion. To combat that, researchers have proposed logic locking techniques to protect the intellectual properties of the design and increase the difficulty of malicious modification of its functionality. However, the adoption of logic locking approaches is rather slow due to the lack of the integration with IC production process and the lack of efficacy of existing algorithms. This work automates the logic locking process by developing software using Python that performs the locking on a gate-level netlist and can be integrated with the existing digital synthesis tools. Analysis of the latest logic locking algorithms has demonstrated that the SFLL-HD algorithm is one of the most secure and versatile in trading-off levels of protection against different types of attacks and was thus selected for implementation. The presented tool can also be expanded to incorporate the latest locking mechanisms to keep up with the fast-paced development in this field. The paper also presents a case study to demonstrate the functionality of the tool and how it could be used to explore the design space and compare different locking solutions. The source code of this tool is available freely from (https://www.researchgate.net/publication/353195333_Source_Code_for_The_Lockit_Tool). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=design%20automation" title="design automation">design automation</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a>, <a href="https://publications.waset.org/abstracts/search?q=IP%20piracy" title=" IP piracy"> IP piracy</a>, <a href="https://publications.waset.org/abstracts/search?q=logic%20locking" title=" logic locking"> logic locking</a> </p> <a href="https://publications.waset.org/abstracts/143937/lockit-a-logic-locking-automation-software" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/143937.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">182</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12048</span> Developing a Systems Dynamics Model for Security Management</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kuan-Chou%20Chen">Kuan-Chou Chen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper will demonstrate a simulation model of an information security system by using the systems dynamic approach. The relationships in the system model are designed to be simple and functional and do not necessarily represent any particular information security environments. The purpose of the paper aims to develop a generic system dynamic information security system model with implications on information security research. The interrelated and interdependent relationships of five primary sectors in the system dynamic model will be presented in this paper. The integrated information security systems model will include (1) information security characteristics, (2) users, (3) technology, (4) business functions, and (5) policy and management. Environments, attacks, government and social culture will be defined as the external sector. The interactions within each of these sectors will be depicted by system loop map as well. The proposed system dynamic model will not only provide a conceptual framework for information security analysts and designers but also allow information security managers to remove the incongruity between the management of risk incidents and the management of knowledge and further support information security managers and decision makers the foundation for managerial actions and policy decisions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=system%20thinking" title="system thinking">system thinking</a>, <a href="https://publications.waset.org/abstracts/search?q=information%20security%20systems" title=" information security systems"> information security systems</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20management" title=" security management"> security management</a>, <a href="https://publications.waset.org/abstracts/search?q=simulation" title=" simulation"> simulation</a> </p> <a href="https://publications.waset.org/abstracts/40859/developing-a-systems-dynamics-model-for-security-management" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/40859.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">429</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12047</span> Advancements in Smart Home Systems: A Comprehensive Exploration in Electronic Engineering</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Chukwuka%20E.%20V.">Chukwuka E. V.</a>, <a href="https://publications.waset.org/abstracts/search?q=Rowling%20J.%20K."> Rowling J. K.</a>, <a href="https://publications.waset.org/abstracts/search?q=Rushdie%20Salman"> Rushdie Salman</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The field of electronic engineering encompasses the study and application of electrical systems, circuits, and devices. Engineers in this discipline design, analyze and optimize electronic components to develop innovative solutions for various industries. This abstract provides a brief overview of the diverse areas within electronic engineering, including analog and digital electronics, signal processing, communication systems, and embedded systems. It highlights the importance of staying abreast of advancements in technology and fostering interdisciplinary collaboration to address contemporary challenges in this rapidly evolving field. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=smart%20home%20engineering" title="smart home engineering">smart home engineering</a>, <a href="https://publications.waset.org/abstracts/search?q=energy%20efficiency" title=" energy efficiency"> energy efficiency</a>, <a href="https://publications.waset.org/abstracts/search?q=user-centric%20design" title=" user-centric design"> user-centric design</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20frameworks" title=" security frameworks"> security frameworks</a> </p> <a href="https://publications.waset.org/abstracts/176467/advancements-in-smart-home-systems-a-comprehensive-exploration-in-electronic-engineering" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/176467.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">87</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12046</span> Lego Mindstorms as a Simulation of Robotic Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Miroslav%20Popelka">Miroslav Popelka</a>, <a href="https://publications.waset.org/abstracts/search?q=Jakub%20No%C5%BEi%C4%8Dka"> Jakub Nožička</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper we deal with using Lego Mindstorms in simulation of robotic systems with respect to cost reduction. Lego Mindstorms kit contains broad variety of hardware components which are required to simulate, program and test the robotics systems in practice. Algorithm programming went in development environment supplied together with Lego kit as in programming language C# as well. Algorithm following the line, which we dealt with in this paper, uses theoretical findings from area of controlling circuits. PID controller has been chosen as controlling circuit whose individual components were experimentally adjusted for optimal motion of robot tracking the line. Data which are determined to process by algorithm are collected by sensors which scan the interface between black and white surfaces followed by robot. Based on discovered facts Lego Mindstorms can be considered for low-cost and capable kit to simulate real robotics systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=LEGO%20Mindstorms" title="LEGO Mindstorms">LEGO Mindstorms</a>, <a href="https://publications.waset.org/abstracts/search?q=PID%20controller" title=" PID controller"> PID controller</a>, <a href="https://publications.waset.org/abstracts/search?q=low-cost%20robotics%20systems" title=" low-cost robotics systems"> low-cost robotics systems</a>, <a href="https://publications.waset.org/abstracts/search?q=line%20follower" title=" line follower"> line follower</a>, <a href="https://publications.waset.org/abstracts/search?q=sensors" title=" sensors"> sensors</a>, <a href="https://publications.waset.org/abstracts/search?q=programming%20language%20C%23" title=" programming language C#"> programming language C#</a>, <a href="https://publications.waset.org/abstracts/search?q=EV3%20Home%20Edition%20Software" title=" EV3 Home Edition Software"> EV3 Home Edition Software</a> </p> <a href="https://publications.waset.org/abstracts/10889/lego-mindstorms-as-a-simulation-of-robotic-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/10889.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">374</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12045</span> Efficient Field-Oriented Motor Control on Resource-Constrained Microcontrollers for Optimal Performance without Specialized Hardware</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nishita%20Jaiswal">Nishita Jaiswal</a>, <a href="https://publications.waset.org/abstracts/search?q=Apoorv%20Mohan%20Satpute"> Apoorv Mohan Satpute</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The increasing demand for efficient, cost-effective motor control systems in the automotive industry has driven the need for advanced, highly optimized control algorithms. Field-Oriented Control (FOC) has established itself as the leading approach for motor control, offering precise and dynamic regulation of torque, speed, and position. However, as energy efficiency becomes more critical in modern applications, implementing FOC on low-power, cost-sensitive microcontrollers pose significant challenges due to the limited availability of computational and hardware resources. Currently, most solutions rely on high-performance 32-bit microcontrollers or Application-Specific Integrated Circuits (ASICs) equipped with Floating Point Units (FPUs) and Hardware Accelerated Units (HAUs). These advanced platforms enable rapid computation and simplify the execution of complex control algorithms like FOC. However, these benefits come at the expense of higher costs, increased power consumption, and added system complexity. These drawbacks limit their suitability for embedded systems with strict power and budget constraints, where achieving energy and execution efficiency without compromising performance is essential. In this paper, we present an alternative approach that utilizes optimized data representation and computation techniques on a 16-bit microcontroller without FPUs or HAUs. By carefully optimizing data point formats and employing fixed-point arithmetic, we demonstrate how the precision and computational efficiency required for FOC can be maintained in resource-constrained environments. This approach eliminates the overhead performance associated with floating-point operations and hardware acceleration, providing a more practical solution in terms of cost, scalability and improved execution time efficiency, allowing faster response in motor control applications. Furthermore, it enhances system design flexibility, making it particularly well-suited for applications that demand stringent control over power consumption and costs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=field-oriented%20control" title="field-oriented control">field-oriented control</a>, <a href="https://publications.waset.org/abstracts/search?q=fixed-point%20arithmetic" title=" fixed-point arithmetic"> fixed-point arithmetic</a>, <a href="https://publications.waset.org/abstracts/search?q=floating%20point%20unit" title=" floating point unit"> floating point unit</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20accelerator%20unit" title=" hardware accelerator unit"> hardware accelerator unit</a>, <a href="https://publications.waset.org/abstracts/search?q=motor%20control%20systems" title=" motor control systems"> motor control systems</a> </p> <a href="https://publications.waset.org/abstracts/193331/efficient-field-oriented-motor-control-on-resource-constrained-microcontrollers-for-optimal-performance-without-specialized-hardware" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/193331.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">14</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12044</span> Multi-Level Security Measures in Cloud Computing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shobha%20G.%20Ranjan">Shobha G. Ranjan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Cloud computing is an emerging, on-demand and internet- based technology. Varieties of services like, software, hardware, data storage and infrastructure can be shared though the cloud computing. This technology is highly reliable, cost effective and scalable in nature. It is a must only the authorized users should access these services. Further the time granted to access these services should be taken into account for proper accounting purpose. Currently many organizations do the security measures in many different ways to provide the best cloud infrastructure to their clients, but that’s not the limitation. This paper presents the multi-level security measure technique which is in accordance with the OSI model. In this paper, details of proposed multilevel security measures technique are presented along with the architecture, activities, algorithms and probability of success in breaking authentication. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cloud%20computing" title="cloud computing">cloud computing</a>, <a href="https://publications.waset.org/abstracts/search?q=cloud%20security" title=" cloud security"> cloud security</a>, <a href="https://publications.waset.org/abstracts/search?q=integrity" title=" integrity"> integrity</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-tenancy" title=" multi-tenancy"> multi-tenancy</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a> </p> <a href="https://publications.waset.org/abstracts/3904/multi-level-security-measures-in-cloud-computing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/3904.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">501</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12043</span> Diversity for Safety and Security of Autonomous Vehicles against Accidental and Deliberate Faults</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Anil%20Ranjitbhai%20Patel">Anil Ranjitbhai Patel</a>, <a href="https://publications.waset.org/abstracts/search?q=Clement%20John%20Shaji"> Clement John Shaji</a>, <a href="https://publications.waset.org/abstracts/search?q=Peter%20Liggesmeyer"> Peter Liggesmeyer</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Safety and security of autonomous vehicles (AVs) is a growing concern, first, due to the increased number of safety-critical functions taken over by automotive embedded systems; second, due to the increased exposure of the software-intensive systems to potential attackers; third, due to dynamic interaction in an uncertain and unknown environment at runtime which results in changed functional and non-functional properties of the system. Frequently occurring environmental uncertainties, random component failures, and compromise security of the AVs might result in hazardous events, sometimes even in an accident, if left undetected. Beyond these technical issues, we argue that the safety and security of AVs against accidental and deliberate faults are poorly understood and rarely implemented. One possible way to overcome this is through a well-known diversity approach. As an effective approach to increase safety and security, diversity has been widely used in the aviation, railway, and aerospace industries. Thus, the paper proposes fault-tolerance by diversity model takes into consideration the mitigation of accidental and deliberate faults by application of structure and variant redundancy. The model can be used to design the AVs with various types of diversity in hardware and software-based multi-version system. The paper evaluates the presented approach by employing an example from adaptive cruise control, followed by discussing the case study with initial findings. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=autonomous%20vehicles" title="autonomous vehicles">autonomous vehicles</a>, <a href="https://publications.waset.org/abstracts/search?q=diversity" title=" diversity"> diversity</a>, <a href="https://publications.waset.org/abstracts/search?q=fault-tolerance" title=" fault-tolerance"> fault-tolerance</a>, <a href="https://publications.waset.org/abstracts/search?q=adaptive%20cruise%20control" title=" adaptive cruise control"> adaptive cruise control</a>, <a href="https://publications.waset.org/abstracts/search?q=safety" title=" safety"> safety</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a> </p> <a href="https://publications.waset.org/abstracts/130595/diversity-for-safety-and-security-of-autonomous-vehicles-against-accidental-and-deliberate-faults" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/130595.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">128</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12042</span> Paper-Based Detection Using Synthetic Gene Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vanessa%20Funk">Vanessa Funk</a>, <a href="https://publications.waset.org/abstracts/search?q=Steven%20Blum"> Steven Blum</a>, <a href="https://publications.waset.org/abstracts/search?q=Stephanie%20Cole"> Stephanie Cole</a>, <a href="https://publications.waset.org/abstracts/search?q=Jorge%20Maciel"> Jorge Maciel</a>, <a href="https://publications.waset.org/abstracts/search?q=Matthew%20Lux"> Matthew Lux</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cell-free%20lysates" title="cell-free lysates">cell-free lysates</a>, <a href="https://publications.waset.org/abstracts/search?q=detection" title=" detection"> detection</a>, <a href="https://publications.waset.org/abstracts/search?q=gene%20circuits" title=" gene circuits"> gene circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=in%20vitro" title=" in vitro"> in vitro</a> </p> <a href="https://publications.waset.org/abstracts/71047/paper-based-detection-using-synthetic-gene-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/71047.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">394</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12041</span> Integrated Teaching of Hardware Courses for the Undergraduates of Computer Science and Engineering to Attain Focused Outcomes</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Namrata%20D.%20Hiremath">Namrata D. Hiremath</a>, <a href="https://publications.waset.org/abstracts/search?q=Mahalaxmi%20Bhille"> Mahalaxmi Bhille</a>, <a href="https://publications.waset.org/abstracts/search?q=P.%20G.%20Sunitha%20Hiremath"> P. G. Sunitha Hiremath</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Computer systems play an integral role in all facets of the engineering profession. This calls for an understanding of the processor-level components of computer systems, their design and operation, and their impact on the overall performance of the systems. Systems users are always in need of faster, more powerful, yet cheaper computer systems. The focus of Computer Science engineering graduates is inclined towards software oriented base. To be an efficient programmer there is a need to understand the role of hardware architecture towards the same. It is essential for the students of Computer Science and Engineering to know the basic building blocks of any computing device and how the digital principles can be used to build them. Hence two courses Digital Electronics of 3 credits, which is associated with lab of 1.5 credits and Computer Organization of 5 credits, were introduced at the sophomore level. Activity was introduced with the objective to teach the hardware concepts to the students of Computer science engineering through structured lab. The students were asked to design and implement a component of a computing device using MultiSim simulation tool and build the same using hardware components. The experience of the activity helped the students to understand the real time applications of the SSI and MSI components. The impact of the activity was evaluated and the performance was measured. The paper explains the achievement of the ABET outcomes a, c and k. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=digital" title="digital">digital</a>, <a href="https://publications.waset.org/abstracts/search?q=computer%20organization" title=" computer organization"> computer organization</a>, <a href="https://publications.waset.org/abstracts/search?q=ABET" title=" ABET"> ABET</a>, <a href="https://publications.waset.org/abstracts/search?q=structured%20enquiry" title=" structured enquiry"> structured enquiry</a>, <a href="https://publications.waset.org/abstracts/search?q=course%20activity" title=" course activity"> course activity</a> </p> <a href="https://publications.waset.org/abstracts/21632/integrated-teaching-of-hardware-courses-for-the-undergraduates-of-computer-science-and-engineering-to-attain-focused-outcomes" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21632.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">500</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12040</span> CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ionel%20Zagan">Ionel Zagan</a>, <a href="https://publications.waset.org/abstracts/search?q=Vasile%20Gheorghita%20Gaitan"> Vasile Gheorghita Gaitan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%20scheduler" title="hardware scheduler">hardware scheduler</a>, <a href="https://publications.waset.org/abstracts/search?q=nMPRA%20processor" title=" nMPRA processor"> nMPRA processor</a>, <a href="https://publications.waset.org/abstracts/search?q=real-time%20systems" title=" real-time systems"> real-time systems</a>, <a href="https://publications.waset.org/abstracts/search?q=scheduling%20methods" title=" scheduling methods"> scheduling methods</a> </p> <a href="https://publications.waset.org/abstracts/58047/cpu-architecture-based-on-static-hardware-scheduler-engine-and-multiple-pipeline-registers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58047.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">267</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12039</span> Power Supply Feedback Regulation Loop Design Using Cadence PSpice Tool: Determining Converter Stability by Simulation</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Debabrata%20Das">Debabrata Das</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=power%20electronics" title="power electronics">power electronics</a>, <a href="https://publications.waset.org/abstracts/search?q=feedback%20loop" title=" feedback loop"> feedback loop</a>, <a href="https://publications.waset.org/abstracts/search?q=regulation" title=" regulation"> regulation</a>, <a href="https://publications.waset.org/abstracts/search?q=stability" title=" stability"> stability</a>, <a href="https://publications.waset.org/abstracts/search?q=pole" title=" pole"> pole</a>, <a href="https://publications.waset.org/abstracts/search?q=zero" title=" zero"> zero</a>, <a href="https://publications.waset.org/abstracts/search?q=oscillation" title=" oscillation"> oscillation</a> </p> <a href="https://publications.waset.org/abstracts/80824/power-supply-feedback-regulation-loop-design-using-cadence-pspice-tool-determining-converter-stability-by-simulation" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/80824.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">346</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12038</span> A Survey of Attacks and Security Requirements in Wireless Sensor Networks</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vishnu%20Pratap%20Singh%20Kirar">Vishnu Pratap Singh Kirar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Wireless sensor network (WSN) is a network of many interconnected networked systems, they equipped with energy resources and they are used to detect other physical characteristics. On WSN, there are many researches are performed in past decades. WSN applicable in many security systems govern by military and in many civilian related applications. Thus, the security of WSN gets attention of researchers and gives an opportunity for many future aspects. Still, there are many other issues are related to deployment and overall coverage, scalability, size, energy efficiency, quality of service (QoS), computational power and many more. In this paper we discus about various applications and security related issue and requirements of WSN. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=wireless%20sensor%20network%20%28WSN%29" title="wireless sensor network (WSN)">wireless sensor network (WSN)</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20network%20attacks" title=" wireless network attacks"> wireless network attacks</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20network%20security" title=" wireless network security"> wireless network security</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20requirements" title=" security requirements"> security requirements</a> </p> <a href="https://publications.waset.org/abstracts/22341/a-survey-of-attacks-and-security-requirements-in-wireless-sensor-networks" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/22341.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">491</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security&page=4">4</a></li> <li class="page-item"><a class="page-link" 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