<?xml version="1.0" encoding="UTF-8"?> <article key="pdf/7685" mdate="2010-03-01 00:00:00"> <author>Hong Li and Linfeng Li and Jianping Hu</author> <title>A PowerGating Scheme to Reduce Leakage Power for Ptype Adiabatic Logic Circuits</title> <pages>327 - 332</pages> <year>2010</year> <volume>4</volume> <number>2</number> <journal>International Journal of Electrical and Computer Engineering</journal> <ee>https://publications.waset.org/pdf/7685</ee> <url>https://publications.waset.org/vol/38</url> <publisher>World Academy of Science, Engineering and Technology</publisher> <abstract>With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in lowpower design. This paper presents a powergating scheme for PDTGAL (ptype dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of PDTGAL circuits with powergating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the PDTGAL with powergating techniques.</abstract> <index>Open Science Index 38, 2010</index> </article>