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id="order" name="order"><option selected value="-announced_date_first">Announcement date (newest first)</option><option value="announced_date_first">Announcement date (oldest first)</option><option value="-submitted_date">Submission date (newest first)</option><option value="submitted_date">Submission date (oldest first)</option><option value="">Relevance</option></select> </span> </div> <div class="control"> <button class="button is-small is-link">Go</button> </div> </div> </form> </div> </div> <ol class="breathe-horizontal" start="1"> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2412.04485">arXiv:2412.04485</a> <span> [<a href="https://arxiv.org/pdf/2412.04485">pdf</a>, <a href="https://arxiv.org/format/2412.04485">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> </div> </div> <p class="title is-5 mathjax"> EDA-Aware RTL Generation with Large Language Models </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Islam%2C+M+u">Mubashir ul Islam</a>, <a href="/search/cs?searchtype=author&query=Sami%2C+H">Humza Sami</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Tenace%2C+V">Valerio Tenace</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2412.04485v1-abstract-short" style="display: inline;"> Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, auto… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2412.04485v1-abstract-full').style.display = 'inline'; document.getElementById('2412.04485v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2412.04485v1-abstract-full" style="display: none;"> Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start. In this work, we introduce AIvril2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4$\times$ enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2412.04485v1-abstract-full').style.display = 'none'; document.getElementById('2412.04485v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 20 November, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2409.11411">arXiv:2409.11411</a> <span> [<a href="https://arxiv.org/pdf/2409.11411">pdf</a>, <a href="https://arxiv.org/format/2409.11411">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Multiagent Systems">cs.MA</span> </div> </div> <p class="title is-5 mathjax"> AIvril: AI-Driven RTL Generation With Verification In-The-Loop </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Islam%2C+M+u">Mubashir ul Islam</a>, <a href="/search/cs?searchtype=author&query=Sami%2C+H">Humza Sami</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Tenace%2C+V">Valerio Tenace</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2409.11411v1-abstract-short" style="display: inline;"> Large Language Models (LLMs) are computational models capable of performing complex natural language processing tasks. Leveraging these capabilities, LLMs hold the potential to transform the entire hardware design stack, with predictions suggesting that front-end and back-end tasks could be fully automated in the near future. Currently, LLMs show great promise in streamlining Register Transfer Lev… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.11411v1-abstract-full').style.display = 'inline'; document.getElementById('2409.11411v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2409.11411v1-abstract-full" style="display: none;"> Large Language Models (LLMs) are computational models capable of performing complex natural language processing tasks. Leveraging these capabilities, LLMs hold the potential to transform the entire hardware design stack, with predictions suggesting that front-end and back-end tasks could be fully automated in the near future. Currently, LLMs show great promise in streamlining Register Transfer Level (RTL) generation, enhancing efficiency, and accelerating innovation. However, their probabilistic nature makes them prone to inaccuracies - a significant drawback in RTL design, where reliability and precision are essential. To address these challenges, this paper introduces AIvril, an advanced framework designed to enhance the accuracy and reliability of RTL-aware LLMs. AIvril employs a multi-agent, LLM-agnostic system for automatic syntax correction and functional verification, significantly reducing - and in many cases, completely eliminating - instances of erroneous code generation. Experimental results conducted on the VerilogEval-Human dataset show that our framework improves code quality by nearly 2x when compared to previous works, while achieving an 88.46% success rate in meeting verification objectives. This represents a critical step toward automating and optimizing hardware design workflows, offering a more dependable methodology for AI-driven RTL design. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.11411v1-abstract-full').style.display = 'none'; document.getElementById('2409.11411v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 3 September, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2311.02055">arXiv:2311.02055</a> <span> [<a href="https://arxiv.org/pdf/2311.02055">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Guthaus%2C+M">M. Guthaus</a>, <a href="/search/cs?searchtype=author&query=Batten%2C+C">C. Batten</a>, <a href="/search/cs?searchtype=author&query=Brunvand%2C+E">E. Brunvand</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P+E">P. E. Gaillardon</a>, <a href="/search/cs?searchtype=author&query=harris%2C+D">D. harris</a>, <a href="/search/cs?searchtype=author&query=Manohar%2C+R">R. Manohar</a>, <a href="/search/cs?searchtype=author&query=Mazumder%2C+P">P. Mazumder</a>, <a href="/search/cs?searchtype=author&query=Pileggi%2C+L">L. Pileggi</a>, <a href="/search/cs?searchtype=author&query=Stine%2C+J">J. Stine</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2311.02055v1-abstract-short" style="display: inline;"> As the pace of progress that has followed Moore's law continues to diminish, it is critical that the US support Integrated Circuit (IC or chip) education and research to maintain technological innovation. Furthermore, US economic independence, security, and future international standing rely on having on-shore IC design capabilities. New devices with disparate technologies, improved design softwar… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2311.02055v1-abstract-full').style.display = 'inline'; document.getElementById('2311.02055v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2311.02055v1-abstract-full" style="display: none;"> As the pace of progress that has followed Moore's law continues to diminish, it is critical that the US support Integrated Circuit (IC or chip) education and research to maintain technological innovation. Furthermore, US economic independence, security, and future international standing rely on having on-shore IC design capabilities. New devices with disparate technologies, improved design software toolchains and methodologies, and technologies to integrate heterogeneous systems will be needed to advance IC design capabilities. This will require rethinking both how we teach design to address the new complexity and how we inspire student interest in a hardware systems career path. The main recommendation of this workshop is that accessibility is the key issue. To this end, a National Chip Design Center (NCDC) should be established to further research and education by partnering academics and industry to train our future workforce. This should not be limited to R1 universities, but should also include R2, community college, minority serving institutions (MSI), and K-12 institutions to have the broadest effect. The NCDC should support the access, development, and maintenance of open design tools, tool flows, design kits, design components, and educational materials. Open-source options should be emphasized wherever possible to maximize accessibility. The NCDC should also provide access and support for chip fabrication, packaging and testing for both research and educational purposes. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2311.02055v1-abstract-full').style.display = 'none'; document.getElementById('2311.02055v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 3 November, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">This material is based upon work supported by the NSF under Grant No. 2137629</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2205.07425">arXiv:2205.07425</a> <span> [<a href="https://arxiv.org/pdf/2205.07425">pdf</a>, <a href="https://arxiv.org/format/2205.07425">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1145/3489517.3530543">10.1145/3489517.3530543 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> ALICE: An Automatic Design Flow for eFPGA Redaction </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Tomajoli%2C+C+M">Chiara Muscari Tomajoli</a>, <a href="/search/cs?searchtype=author&query=Collini%2C+L">Luca Collini</a>, <a href="/search/cs?searchtype=author&query=Bhandari%2C+J">Jitendra Bhandari</a>, <a href="/search/cs?searchtype=author&query=Moosa%2C+A+K+T">Abdul Khader Thalakkattu Moosa</a>, <a href="/search/cs?searchtype=author&query=Tan%2C+B">Benjamin Tan</a>, <a href="/search/cs?searchtype=author&query=Tang%2C+X">Xifan Tang</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Karri%2C+R">Ramesh Karri</a>, <a href="/search/cs?searchtype=author&query=Pilato%2C+C">Christian Pilato</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2205.07425v1-abstract-short" style="display: inline;"> Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2205.07425v1-abstract-full').style.display = 'inline'; document.getElementById('2205.07425v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2205.07425v1-abstract-full" style="display: none;"> Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2205.07425v1-abstract-full').style.display = 'none'; document.getElementById('2205.07425v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 15 May, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Paper accepted for presentation at the IEEE/ACM Design Automation Conference (DAC 2022)</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2202.07721">arXiv:2202.07721</a> <span> [<a href="https://arxiv.org/pdf/2202.07721">pdf</a>, <a href="https://arxiv.org/format/2202.07721">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/TCAD.2022.3213611">10.1109/TCAD.2022.3213611 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Neto%2C+W+L">Walter Lau Neto</a>, <a href="/search/cs?searchtype=author&query=Li%2C+Y">Yingjie Li</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Yu%2C+C">Cunxi Yu</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2202.07721v2-abstract-short" style="display: inline;"> Recent years have seen increasing employment of decision intelligence in electronic design automation (EDA), which aims to reduce the manual efforts and boost the design closure process in modern toolflows. However, existing approaches either require a large number of labeled data and expensive training efforts, or are limited in practical EDA toolflow integration due to computation overhead. This… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2202.07721v2-abstract-full').style.display = 'inline'; document.getElementById('2202.07721v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2202.07721v2-abstract-full" style="display: none;"> Recent years have seen increasing employment of decision intelligence in electronic design automation (EDA), which aims to reduce the manual efforts and boost the design closure process in modern toolflows. However, existing approaches either require a large number of labeled data and expensive training efforts, or are limited in practical EDA toolflow integration due to computation overhead. This paper presents a generic end-to-end sequential decision making framework FlowTune for synthesis tooflow optimization, with a novel high-performance domain-specific, multi-stage multi-armed bandit (MAB) approach. This framework addresses optimization problems on Boolean optimization problems such as a) And-Inv-Graphs (# nodes), b) Conjunction Normal Form (CNF) minimization (# clauses) for Boolean Satisfiability; logic synthesis and technology mapping problems such as c) post static timing analysis (STA) delay and area optimization for standard-cell technology mapping, and d) FPGA technology mapping for 6-in LUT architectures. Moreover, we demonstrate the high extnsibility and generalizability of the proposed domain-specific MAB approach with end-to-end FPGA design flow, evaluated at post-routing stage, with two different FPGA backend tools (OpenFPGA and VPR) and two different logic synthesis representations (AIGs and MIGs). FlowTune is fully integrated with ABC [1], Yosys [2], VTR [3], LSOracle [4], OpenFPGA [5], and industrial tools, and is released publicly. The experimental results conducted on various design stages in the flow all demonstrate that our framework outperforms both hand-crafted flows [1] and ML explored flows [6], [7] in quality of results, and is orders of magnitude faster compared to ML-based approaches. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2202.07721v2-abstract-full').style.display = 'none'; document.getElementById('2202.07721v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 23 May, 2023; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 15 February, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> February 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">13 pages</span> </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Journal ref:</span> IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2023 </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2112.00621">arXiv:2112.00621</a> <span> [<a href="https://arxiv.org/pdf/2112.00621">pdf</a>, <a href="https://arxiv.org/format/2112.00621">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Other Computer Science">cs.OH</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Logic in Computer Science">cs.LO</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/TCAD.2022.3143489">10.1109/TCAD.2022.3143489 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Ammes%2C+G">Gabriel Ammes</a>, <a href="/search/cs?searchtype=author&query=Neto%2C+W+L">Walter Lau Neto</a>, <a href="/search/cs?searchtype=author&query=Butzen%2C+P">Paulo Butzen</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Ribas%2C+R+P">Renato P. Ribas</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2112.00621v1-abstract-short" style="display: inline;"> Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. Experimental results have shown significant literal count and runtime reduction compared to the state-o… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2112.00621v1-abstract-full').style.display = 'inline'; document.getElementById('2112.00621v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2112.00621v1-abstract-full" style="display: none;"> Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. Experimental results have shown significant literal count and runtime reduction compared to the state-of-the-art approach. The method scalability is illustrated for a high error threshold over large benchmark circuits. The obtained solutions have presented a literal number reduction up to 38%, 56% and 93% with respect to an error rate of 1%, 3% and 5%, respectively. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2112.00621v1-abstract-full').style.display = 'none'; document.getElementById('2112.00621v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 21 November, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">5 Pages, submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2110.13346">arXiv:2110.13346</a> <span> [<a href="https://arxiv.org/pdf/2110.13346">pdf</a>, <a href="https://arxiv.org/format/2110.13346">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Cryptography and Security">cs.CR</span> </div> </div> <p class="title is-5 mathjax"> Exploring eFPGA-based Redaction for IP Protection </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Bhandari%2C+J">Jitendra Bhandari</a>, <a href="/search/cs?searchtype=author&query=Moosa%2C+A+K+T">Abdul Khader Thalakkattu Moosa</a>, <a href="/search/cs?searchtype=author&query=Tan%2C+B">Benjamin Tan</a>, <a href="/search/cs?searchtype=author&query=Pilato%2C+C">Christian Pilato</a>, <a href="/search/cs?searchtype=author&query=Gore%2C+G">Ganesh Gore</a>, <a href="/search/cs?searchtype=author&query=Tang%2C+X">Xifan Tang</a>, <a href="/search/cs?searchtype=author&query=Temple%2C+S">Scott Temple</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Karri%2C+R">Ramesh Karri</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2110.13346v1-abstract-short" style="display: inline;"> Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing ov… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.13346v1-abstract-full').style.display = 'inline'; document.getElementById('2110.13346v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2110.13346v1-abstract-full" style="display: none;"> Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing overheads, as well as security factors. Adapting an open-source FPGA fabric generation flow, we perform a case study to explore the trade-offs when redacting different modules of open-source intellectual property blocks (IPs) and explore how different parts of an eFPGA contribute to the security. We provide new insights into the feasibility and challenges of using eFPGA-based redaction as a security solution. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.13346v1-abstract-full').style.display = 'none'; document.getElementById('2110.13346v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 October, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted to ICCAD 2021</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2012.02530">arXiv:2012.02530</a> <span> [<a href="https://arxiv.org/pdf/2012.02530">pdf</a>, <a href="https://arxiv.org/format/2012.02530">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> </div> </div> <p class="title is-5 mathjax"> Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Rai%2C+S">Shubham Rai</a>, <a href="/search/cs?searchtype=author&query=Neto%2C+W+L">Walter Lau Neto</a>, <a href="/search/cs?searchtype=author&query=Miyasaka%2C+Y">Yukio Miyasaka</a>, <a href="/search/cs?searchtype=author&query=Zhang%2C+X">Xinpei Zhang</a>, <a href="/search/cs?searchtype=author&query=Yu%2C+M">Mingfei Yu</a>, <a href="/search/cs?searchtype=author&query=Fujita%2C+Q+Y+M">Qingyang Yi Masahiro Fujita</a>, <a href="/search/cs?searchtype=author&query=Manske%2C+G+B">Guilherme B. Manske</a>, <a href="/search/cs?searchtype=author&query=Pontes%2C+M+F">Matheus F. Pontes</a>, <a href="/search/cs?searchtype=author&query=Junior%2C+L+S+d+R">Leomar S. da Rosa Junior</a>, <a href="/search/cs?searchtype=author&query=de+Aguiar%2C+M+S">Marilton S. de Aguiar</a>, <a href="/search/cs?searchtype=author&query=Butzen%2C+P+F">Paulo F. Butzen</a>, <a href="/search/cs?searchtype=author&query=Chien%2C+P">Po-Chun Chien</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Y">Yu-Shan Huang</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+H">Hoa-Ren Wang</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+J+R">Jie-Hong R. Jiang</a>, <a href="/search/cs?searchtype=author&query=Gu%2C+J">Jiaqi Gu</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zheng Zhao</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zixuan Jiang</a>, <a href="/search/cs?searchtype=author&query=Pan%2C+D+Z">David Z. Pan</a>, <a href="/search/cs?searchtype=author&query=de+Abreu%2C+B+A">Brunno A. de Abreu</a>, <a href="/search/cs?searchtype=author&query=Campos%2C+I+d+S">Isac de Souza Campos</a>, <a href="/search/cs?searchtype=author&query=Berndt%2C+A">Augusto Berndt</a>, <a href="/search/cs?searchtype=author&query=Meinhardt%2C+C">Cristina Meinhardt</a>, <a href="/search/cs?searchtype=author&query=Carvalho%2C+J+T">Jonata T. Carvalho</a>, <a href="/search/cs?searchtype=author&query=Grellert%2C+M">Mateus Grellert</a> , et al. (15 additional authors not shown) </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2012.02530v2-abstract-short" style="display: inline;"> Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthes… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2012.02530v2-abstract-full').style.display = 'inline'; document.getElementById('2012.02530v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2012.02530v2-abstract-full" style="display: none;"> Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2012.02530v2-abstract-full').style.display = 'none'; document.getElementById('2012.02530v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 15 December, 2020; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 4 December, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2020. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">In this 23 page manuscript, we explore the connection between machine learning and logic synthesis which was the main goal for International Workshop on logic synthesis. It includes approaches applied by ten teams spanning 6 countries across the world</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1502.06359">arXiv:1502.06359</a> <span> [<a href="https://arxiv.org/pdf/1502.06359">pdf</a>, <a href="https://arxiv.org/format/1502.06359">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Logic in Computer Science">cs.LO</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/TC.2015.2506566">10.1109/TC.2015.2506566 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> A Sound and Complete Axiomatization of Majority-n Logic </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Amaru%2C+L">Luca Amaru</a>, <a href="/search/cs?searchtype=author&query=Gaillardon%2C+P">Pierre-Emmanuel Gaillardon</a>, <a href="/search/cs?searchtype=author&query=Chattopadhyay%2C+A">Anupam Chattopadhyay</a>, <a href="/search/cs?searchtype=author&query=De+Micheli%2C+G">Giovanni De Micheli</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1502.06359v3-abstract-short" style="display: inline;"> Manipulating logic functions via majority operators recently drew the attention of researchers in computer science. For example, circuit optimization based on majority operators enables superior results as compared to traditional logic systems. Also, the Boolean satisfiability problem finds new solving approaches when described in terms of majority decisions. To support computer logic applications… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1502.06359v3-abstract-full').style.display = 'inline'; document.getElementById('1502.06359v3-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1502.06359v3-abstract-full" style="display: none;"> Manipulating logic functions via majority operators recently drew the attention of researchers in computer science. For example, circuit optimization based on majority operators enables superior results as compared to traditional logic systems. Also, the Boolean satisfiability problem finds new solving approaches when described in terms of majority decisions. To support computer logic applications based on majority a sound and complete set of axioms is required. Most of the recent advances in majority logic deal only with ternary majority (MAJ- 3) operators because the axiomatization with solely MAJ-3 and complementation operators is well understood. However, it is of interest extending such axiomatization to n-ary majority operators (MAJ-n) from both the theoretical and practical perspective. In this work, we address this issue by introducing a sound and complete axiomatization of MAJ-n logic. Our axiomatization naturally includes existing majority logic systems. Based on this general set of axioms, computer applications can now fully exploit the expressive power of majority logic. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1502.06359v3-abstract-full').style.display = 'none'; document.getElementById('1502.06359v3-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 November, 2015; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 23 February, 2015; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> February 2015. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted by the IEEE Transactions on Computers</span> </p> </li> </ol> <div class="is-hidden-tablet"> <!-- feedback for mobile only --> <span class="help" style="display: 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