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tag-buried-power-rails tag-cfet tag-intel tag-nanosheet-transistors post-section--topic/semiconductors" data-category="Semiconductors"><article elid="2657807330" data-frozen-sections="[]" class="clearfix page-article sm-mb-1 quality-HD post-2657807330" data-category="Semiconductors"><div class="row px10"><div class="rm-col-center col sm-mb-1" style="width:100.0%;"><div class="widget__body clearfix sm-mt-1"><div class="all-related-sections"><a href="https://spectrum.ieee.org/topic/semiconductors/">Semiconductors</a><a href="https://spectrum.ieee.org/magazine/2022/december/">December 2022</a><a href="https://spectrum.ieee.org/magazine/">Magazine</a><a href="https://spectrum.ieee.org/special-reports/the-transistor-at-75/">The Transistor at 75</a><a href="https://spectrum.ieee.org/type/feature/">Feature</a><a href="https://spectrum.ieee.org/special-reports/">Special Reports</a></div><h1 class="widget__headline h1"><span class="widget__headline-text custom-post-headline" data-type="text"> 3D-Stacked CMOS Takes Moore’s Law to New Heights </span></h1><div class="widget__subheadline"><h2 class="widget__subheadline-text h2" data-type="text"><p>When transistors can’t get any smaller, the only direction is up</p></h2></div><div class="social-author clearfix"><div class="social-author__avatar image"><div class="cover-all image" style="background-image: url("https://spectrum.ieee.org/res/avatars/default")"></div></div><a class="social-author__name" href="https://spectrum.ieee.org/u/marko-radosavljevic" data-type="text">Marko Radosavljevic</a><div class="social-author__avatar image"><div class="cover-all image" style="background-image: url("https://spectrum.ieee.org/res/avatars/default")"></div></div><a class="social-author__name" href="https://spectrum.ieee.org/u/jack-kavalieros" data-type="text">Jack Kavalieros</a></div><div class="social-date"><span class="social-date__text">11 Aug 2022</span></div><div class="time-to-read">9 min read</div><div class="like-button" data-post-likes="58"></div><div class="widget__shares share-panel"><a href="mailto:?subject=3D-Stacked%20CMOS%20Takes%20Moore%E2%80%99s%20Law%20to%20New%20Heights&body=https://spectrum.ieee.org/3d-cmos" target="_blank" data-track-share="Email" class="share share-popup share-email" rel="noopener noreferrer" aria-label="Share via Email"><i aria-hidden="true" class="icons-share em fa fa-envelope"></i></a><a href="https://spectrum.ieee.org/3d-cmos" data-clipboard-text="https://spectrum.ieee.org/3d-cmos" class="share share-copy-link" title="Copy this link to clipboard"><i class="icons-share" style="width: 60%"><svg aria-hidden="true" data-prefix="far" data-icon="copy" class="svg-inline--fa fa-copy fa-w-14" role="img" xmlns="http://www.w3.org/2000/svg" viewbox="0 0 448 512"><path fill="currentColor" d="M433.941 65.941l-51.882-51.882A48 48 0 0 0 348.118 0H176c-26.51 0-48 21.49-48 48v48H48c-26.51 0-48 21.49-48 48v320c0 26.51 21.49 48 48 48h224c26.51 0 48-21.49 48-48v-48h80c26.51 0 48-21.49 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class="icons-share fb fa fa-facebook"></i></a><a href="https://www.linkedin.com/shareArticle?mini=false&url=https://spectrum.ieee.org/3d-cmos&" target="_blank" class="share share-popup share-linkedin" data-track-share="Linkedin" rel="noopener noreferrer" aria-label="Share on Linkedin"><i aria-hidden="true" class="icons-share fa fa-linkedin"></i></a></div></div><div class="widget__head"><picture><source srcset="https://spectrum.ieee.org/media-library/an-image-of-stacked-squares-with-yellow-flat-bars-through-them.png?id=30541109&width=3600&height=2419 3x, https://spectrum.ieee.org/media-library/an-image-of-stacked-squares-with-yellow-flat-bars-through-them.png?id=30541109&width=2400&height=1613 2x, https://spectrum.ieee.org/media-library/an-image-of-stacked-squares-with-yellow-flat-bars-through-them.png?id=30541109&width=1200&height=806 1x"/><img fetchpriority="high" role="img" alt="An image of stacked squares with yellow flat bars through them. " aria-label="An image of stacked squares with yellow flat bars through them. " src="https://spectrum.ieee.org/media-library/an-image-of-stacked-squares-with-yellow-flat-bars-through-them.png?id=30541109&width=1200&height=806" style="object-fit: cover;" class="rm-lazyloadable-image rm-hero-media" width="2400" height="1613"/></picture></div><div class="widget__body clearfix sm-mt-1"><div class="photo-credit"> Emily Cooper </div><div class="custom-field-FeaturePostColor">LightGreen</div><span class="js-scroll-trigger" data-target="body" data-triggers="render-rebelbar" data-toggle-class="with-floating-shares"></span><div id="utm_campaign"></div><div class="body js-expandable clearfix js-listicle-body css-listicle-body-2657807330" data-headline="3D-Stacked CMOS Takes Moore’s Law to New Heights"><div class="body-description"><p><strong>Perhaps the most</strong> far-reaching technological achievement over the last 50 years has been the steady <a href="https://spectrum.ieee.org/a-better-way-to-measure-progress-in-semiconductors" target="_self">march toward ever smaller transistors</a>, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our <a href="https://spectrum.ieee.org/topic/careers/">careers</a> at <a href="https://spectrum.ieee.org/tag/intel">Intel</a> more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further. </p><p> Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” <a href="https://spectrum.ieee.org/tag/transistor">transistor</a> designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits. </p><hr/><div class="ieee-sidebar-small"><p> This article is part of our special report on the <a href="https://spectrum.ieee.org/special-reports/the-transistor-at-75/" target="_blank">75th anniversary of the invention of the transistor</a>. </p></div><p> So where will we turn for future scaling? We will continue to look to the third dimension. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade. </p><h2>The Evolution of the Transistor </h2><p><strong>Continuous innovation is an essential underpinning of Moore’s Law</strong>, but each improvement comes with trade-offs. To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation. </p><p> Every metal-oxide-semiconductor field-effect transistor, or MOSFET, has the same set of basic parts: the gate stack, the channel region, the source, and the drain. The source and drain are chemically doped to make them both either rich in mobile electrons ( <em>n</em>-type) or deficient in them (<em>p</em>-type). The channel region has the opposite doping to the source and drain. </p><p><div class="rebellt-item col1" id="rebelltitem18" data-id="18" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-18" data-basename="particle-18" data-post-id="2657807330" data-published-at="1669928886" data-use-pagination="False"><div class="rblad-ieee_in_content"></div></div><div class="rebellt-item col1" id="rebelltitem19" data-id="19" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-19" data-basename="particle-19" data-post-id="2657807330" data-published-at="1669929004" data-use-pagination="False"><p>In the planar version in use in advanced microprocessors up to 2011, the MOSFET’s gate stack is situated just above the channel region and is designed to project an electric field into the channel region. Applying a large enough voltage to the gate (relative to the source) creates a layer of mobile charge carriers in the channel region that allows current to flow between the source and drain.</p><p>As we scaled down the classic planar transistors, what device physicists call short-channel effects took center stage. Basically, the distance between the source and drain became so small that current would leak across the channel when it wasn’t supposed to, because the gate electrode struggled to deplete the channel of charge carriers. To address this, the industry moved to an entirely different transistor architecture called a <a href="https://spectrum.ieee.org/how-the-father-of-finfets-helped-save-moores-law" target="_self">FinFET</a>. It wrapped the gate around the channel on three sides to provide better electrostatic control.</p></div><div class="rebellt-item ieee-sidebar-fullwidth-columns col2" id="rebelltitem1" data-id="1" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/transistor-evolution" data-basename="transistor-evolution" data-post-id="2657807330" data-published-at="1659640046" data-use-pagination="False"><h3 data-role="headline"> Transistor Evolution </h3><img id="dc39f" data-rm-shortcode-id="5efbe5a5bb1d156298d117a1372c0553" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/blocks-of-grey-silver-and-black-with-a-stripe-of-gold-dots-on-one-and-a-fin-shaped-structure-of-gold-dots-on-the-other.jpg?id=30799212&width=980" width="1300" height="1300" alt="Blocks of grey, silver, and black with a stripe of gold dots on one and a fin-shaped structure of gold dots on the other."/></div><div class="rebellt-item ieee-sidebar-fullwidth-columns col2" id="rebelltitem3" data-id="3" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-3" data-basename="particle-3" data-post-id="2657807330" data-published-at="1659640046" data-use-pagination="False"><img id="e1679" data-rm-shortcode-id="19f1ce24c1d6d33cec903b159c775a2f" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/blocks-of-grey-silver-and-black-with-a-stripe-of-gold-dots-on-one-and-a-fin-shaped-structure-of-gold-dots-on-the-other.jpg?id=30541824&width=980" width="1300" height="1300" alt="Blocks of grey, silver, and black with a stripe of gold dots on one and a fin-shaped structure of gold dots on the other."/></div><div class="rebellt-item ieee-sidebar-fullwidth col1" id="rebelltitem2" data-id="2" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-2" data-basename="particle-2" data-post-id="2657807330" data-published-at="1659640046" data-use-pagination="False"><p class="caption"> The shift from a planar transistor architecture [left] to the FinFET [right] provided greater control of the channel [covered by blue box], resulting in a reduction in power consumption of 50 percent and an increase in performance of 37 percent. <style class="photo-credit"> Emily Cooper </style></p></div><div class="rebellt-item col1" id="rebelltitem4" data-id="4" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-4" data-basename="particle-4" data-post-id="2657807330" data-published-at="1669927851" data-use-pagination="False"><p><a href="https://spectrum.ieee.org/intels-new-transistors-enter-the-third-dimension" target="_self">Intel introduced its FinFETs</a> in 2011, at the 22-nanometer node, with the third-generation Core processor, and the device architecture has been the workhorse of Moore’s Law ever since. With FinFETs, we could operate at a lower voltage and still have less leakage, reducing power consumption by some 50 percent at the same performance level as the previous-generation planar architecture. FinFETs also switched faster, boosting performance by 37 percent. And because conduction occurs on both vertical sides of the “fin,” the device can drive more current through a given area of silicon than can a planar device, which only conducts along one surface.</p><p>However, we did lose something in moving to FinFETs. In planar devices, the width of a transistor was defined by lithography, and therefore it is a highly flexible parameter. But in FinFETs, the transistor width comes in the form of discrete increments—adding one fin at a time–a characteristic often referred to as fin quantization. As flexible as the FinFET may be, fin quantization remains a significant design constraint. The design rules around it and the desire to add more fins to boost performance increase the overall area of logic cells and complicate the stack of interconnects that turn individual transistors into complete logic circuits. It also increases the transistor’s capacitance, thereby sapping some of its switching speed. So, while the FinFET has served us well as the industry’s workhorse, a new, more refined approach is needed. And it’s that approach that led us to the 3D transistors we’re introducing soon.</p></div><div class="rebellt-item ieee-sidebar-left col1" id="rebelltitem5" data-id="5" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-5" data-basename="particle-5" data-post-id="2657807330" data-published-at="1669927851" data-use-pagination="False"><img id="b8771" data-rm-shortcode-id="fa96a297e477e7e7eadd67480f3fba36" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/a-blue-block-pierced-by-three-gold-coated-ribbons-all-atop-a-thicker-grey-block.jpg?id=30541900&width=980" width="1300" height="1300" alt="A blue block pierced by three gold-coated ribbons all atop a thicker grey block."/><small class="image-media media-caption">In the RibbonFET, the gate wraps around the transistor channel region to enhance control of charge carriers. The new structure also enables better performance and more refined optimization.</small><small class="image-media media-photo-credit">Emily Cooper</small></div><div class="rebellt-item col1" id="rebelltitem6" data-id="6" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-6" data-basename="particle-6" data-post-id="2657807330" data-published-at="1669927940" data-use-pagination="False"><p>This advance, the RibbonFET, is our first new transistor architecture since the FinFET’s debut 11 years ago. In it, the gate fully surrounds the channel, providing even tighter control of charge carriers within channels that are now formed by nanometer-scale ribbons of silicon. With these nanoribbons (also called <a href="https://spectrum.ieee.org/the-nanosheet-transistor-is-the-next-and-maybe-last-step-in-moores-law" target="_self">nanosheets)</a>, we can again vary the width of a transistor as needed using lithography.</p><p>With the quantization constraint removed, we can produce the appropriately sized width for the application. That lets us balance power, performance, and cost. What’s more, with the ribbons stacked and operating in parallel, the device can drive more current, boosting performance without increasing the area of the device.<br/></p><p>We see RibbonFETs as the best option for higher performance at reasonable power, and we will be introducing them in 2024 along with other innovations, such as PowerVia, our version of <a href="https://spectrum.ieee.org/next-gen-chips-will-be-powered-from-below" target="_self">backside power delivery</a>, with the <a href="https://spectrum.ieee.org/tag/intel">Intel</a> 20A fabrication process.</p></div><div class="rebellt-item col1" id="rebelltitem7" data-id="7" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-7" data-basename="particle-7" data-post-id="2657807330" data-published-at="1669928096" data-use-pagination="False"><h2>Stacked CMOS</h2><p>One commonality of planar, FinFET, and RibbonFET transistors is that they all use CMOS technology, which, as mentioned, consists of <em>n</em>-type (NMOS) and <em>p</em>-type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it draws significantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to greater operating frequencies and higher transistor densities.</p><p>To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a <a href="https://ieeexplore.ieee.org/document/8993462/" rel="noopener noreferrer" target="_blank">keynote</a> at the <a href="https://ieeexplore.ieee.org/xpl/conhome/8971803/proceeding" rel="noopener noreferrer" target="_blank">IEEE International Electron Devices Meeting (IEDM) in 2019</a>, we introduced the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The following year, at IEDM 2020, we presented <a href="https://ieeexplore.ieee.org/document/9372066" rel="noopener noreferrer" target="_blank">the design for the first logic circuit using this 3D technique</a>, an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the limits of Moore’s Law.</p></div><div class="rebellt-item ieee-sidebar-left col1" id="rebelltitem8" data-id="8" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-8" data-basename="particle-8" data-post-id="2657807330" data-published-at="1669928096" data-use-pagination="False"><img id="f2f30" data-rm-shortcode-id="b04eb1af44bc9883f0a9d8f0b2856597" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/two-blue-blocks-stacked-atop-each-other-each-is-pierced-through-by-gold-coated-ribbons.jpg?id=30566578&width=980" width="1300" height="1300" alt="Two blue blocks stacked atop each other. Each is pierced through by gold coated ribbons."/><small class="image-media media-caption">3D-stacked CMOS puts a PMOS device on top of an NMOS device in the same footprint a single RibbonFET would occupy. The NMOS and PMOS gates use different metals.</small><small class="image-media media-photo-credit">Emily Cooper</small></div><div class="rebellt-item col1" id="rebelltitem9" data-id="9" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-9" data-basename="particle-9" data-post-id="2657807330" data-published-at="1669928096" data-use-pagination="False"><p>Taking advantage of the potential benefits of 3D stacking means solving a number of process integration challenges, some of which will stretch the limits of CMOS fabrication.</p><p>We built the 3D-stacked CMOS inverter using what is known as a self-aligned process, in which both transistors are constructed in one manufacturing step. This means constructing both <em>n</em>-type and <em>p</em>-type sources and drains by epitaxy—crystal deposition—and adding different metal gates for the two transistors. By combining the source-drain and dual-metal-gate processes, we are able to create different conductive types of silicon nanoribbons (<em>p</em>-type and <em>n</em>-type) to make up the stacked CMOS transistor pairs. It also allows us to adjust the device’s threshold voltage—the voltage at which a transistor begins to switch—separately for the top and bottom nanoribbons.</p></div><div class="rebellt-item col1" id="rebelltitem10" data-id="10" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-10" data-basename="particle-10" data-post-id="2657807330" data-published-at="1669928280" data-use-pagination="False"><img id="be20b" data-rm-shortcode-id="6b57a2642594eb748f7a1356e29d79ac" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201498%201060'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/three-pairs-of-two-grey-rectangles-float-above-three-more-pairs-of-grey-rectangles-in-a-black-and-white-micrograph.png?id=30542655&width=980" width="1498" height="1060" alt="Three pairs of two grey rectangles float above three more pairs of grey rectangles in a black-and-white micrograph."/><small class="image-media media-caption"><p>In CMOS logic, NMOS and PMOS devices usually sit side by side on chips. An early prototype has NMOS devices stacked on top of PMOS devices, compressing circuit sizes.</p></small><small class="image-media media-photo-credit"><p>Intel</p></small></div><div class="rebellt-item col1" id="rebelltitem11" data-id="11" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-11" data-basename="particle-11" data-post-id="2657807330" data-published-at="1669928280" data-use-pagination="False"><p>How do we do all that? The self-aligned 3D CMOS fabrication begins with a silicon wafer. On this wafer, we deposit repeating layers of silicon and silicon germanium, a structure called a superlattice. We then use lithographic patterning to cut away parts of the superlattice and leave a finlike structure. The superlattice crystal provides a strong support structure for what comes later.</p></div><div class="rebellt-item col1" id="rebelltitem21" data-id="21" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-21" data-basename="particle-21" data-post-id="2657807330" data-published-at="1669929156" data-use-pagination="False"><div class="rblad-ieee_in_content"></div></div><div class="rebellt-item col1" id="rebelltitem20" data-id="20" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-20" data-basename="particle-20" data-post-id="2657807330" data-published-at="1669929156" data-use-pagination="False"><p>Next, we deposit a block of “dummy” polycrystalline silicon atop the part of the superlattice where the device gates will go, protecting them from the next step in the procedure. That step, called the vertically stacked dual source/drain process, grows phosphorous-doped silicon on both ends of the top nanoribbons (the future NMOS device) while also selectively growing boron-doped silicon germanium on the bottom nanoribbons (the future PMOS device). After this, we deposit dielectric around the sources and drains to electrically isolate them from one another. The latter step requires that we then polish the wafer down to perfect flatness.</p></div><div class="rebellt-item ieee-sidebar-left col1" id="rebelltitem12" data-id="12" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-12" data-basename="particle-12" data-post-id="2657807330" data-published-at="1669928471" data-use-pagination="False"><img id="9fbe8" data-rm-shortcode-id="ad9814ead45122c0f7376c9ee8ebb848" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/gold-columns-are-bridged-by-a-purple-polygon-and-a-green-one-a-rectangle-bisects-the-polygon-it-u2019s-pink-on-top-and-yellow.jpg?id=30567356&width=980" width="1300" height="1300" alt="Gold columns are bridged by a purple polygon and a green one. A rectangle bisects the polygon. It\u2019s pink on top and yellow on the bottom."/><small class="image-media media-caption">An edge-on view of the 3D stacked inverter shows how complicated its connections are.</small><small class="image-media media-photo-credit">Emily Cooper</small></div><div class="rebellt-item col1" id="rebelltitem15" data-id="15" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-15" data-basename="particle-15" data-post-id="2657807330" data-published-at="1669928643" data-use-pagination="False"><p>Finally, we construct the gate. First, we remove that dummy gate we’d put in place earlier, exposing the silicon nanoribbons. We next etch away only the silicon germanium, releasing a stack of parallel silicon nanoribbons, which will be the channel regions of the transistors. We then coat the nanoribbons on all sides with a vanishingly thin layer of an insulator that has a high dielectric constant. The nanoribbon channels are so small and positioned in such a way that we can’t effectively dope them chemically as we would with a planar transistor. Instead, we use a property of the metal gates called the work function to impart the same effect. We surround the bottom nanoribbons with one metal to make a <em>p</em>-doped channel and the top ones with another to form an <em>n</em>-doped channel. Thus, the gate stacks are finished off and the two transistors are complete.</p></div><div class="rebellt-item ieee-sidebar-left col1" id="rebelltitem13" data-id="13" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-13" data-basename="particle-13" data-post-id="2657807330" data-published-at="1669928471" data-use-pagination="False"><img id="17c9b" data-rm-shortcode-id="7232d8e96c05ad8d156703462d0242f2" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%20900'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/blue-pink-and-green-rectangles-representing-different-parts-of-transistors-are-arranged-in-a-larger-circuit-on-the-left-and-one.jpg?id=30542209&width=980" width="1300" height="900" alt="Blue, pink and green rectangles representing different parts of transistors are arranged in a larger circuit on the left and one half the size on the right."/><small class="image-media media-caption">By stacking NMOS on top of PMOS transistors, 3D stacking effectively doubles CMOS transistor density per square millimeter, though the real density depends on the complexity of the logic cell involved. The inverter cells are shown from above indicating source and drain interconnects [red], gate interconnects [blue], and vertical connections [green].</small><small class="image-media media-photo-credit">Emily Cooper</small></div><div class="rebellt-item col1" id="rebelltitem14" data-id="14" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-14" data-basename="particle-14" data-post-id="2657807330" data-published-at="1669928471" data-use-pagination="False"><p>The process might seem complex, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on separate wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process takes fewer manufacturing steps and keeps a tighter rein on manufacturing cost, something we demonstrated in research and reported at IEDM 2019.<br/></p><p>Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being explored to facilitate integration of silicon with nonsilicon channel materials, such as germanium and III-V semiconductor materials. These approaches and materials may become relevant as we look to tightly integrate optoelectronics and other functions on a single chip.</p></div><div class="rebellt-item ieee-sidebar-left col1" id="rebelltitem16" data-id="16" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-16" data-basename="particle-16" data-post-id="2657807330" data-published-at="1669928814" data-use-pagination="False"><img id="78c40" data-rm-shortcode-id="079d62546629794c81cb963df79065fb" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%201300%201300'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/orange-elongated-blocks-connect-to-several-narrower-blocks-of-a-variety-of-colors.jpg?id=30542266&width=980" width="1300" height="1300" alt="Orange elongated blocks connect to several narrower blocks of a variety of colors. "/><small class="image-media media-caption"><p>Making all the needed connections to 3D-stacked CMOS is a challenge. Power connections will need to be made from below the device stack. In this design, the NMOS device [top] and PMOS device [bottom] have separate source/drain contacts, but both devices have a gate in common.</p></small><small class="image-media media-photo-credit">Emily Cooper</small></div><div class="rebellt-item col1" id="rebelltitem17" data-id="17" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-17" data-basename="particle-17" data-post-id="2657807330" data-published-at="1669928814" data-use-pagination="False"><p>The new self-aligned CMOS process, and the 3D-stacked CMOS it creates, work well and appear to have substantial room for further miniaturization. At this early stage, that’s highly encouraging. Devices having a gate length of 75 nm demonstrated both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the smallest distance between two sets of stacked devices is only <a href="https://ieeexplore.ieee.org/document/9720633" target="_blank">55 nm</a>. While the device performance results we achieved are not records in and of themselves, they do compare well with individual nonstacked control devices built on the same wafer with the same processing.</p><p>In parallel with the process integration and experimental work, we have many ongoing theoretical, simulation, and design studies underway looking to provide insight into how best to use 3D CMOS. Through these, we’ve found some of the key considerations in the design of our transistors. Notably, we now know that we need to optimize the vertical spacing between the NMOS and PMOS—if it’s too short it will increase parasitic capacitance, and if it’s too long it will increase the resistance of the interconnects between the two devices. Either extreme results in slower circuits that consume more power.</p><p>Many design studies, such as one by <a href="https://ieeexplore.ieee.org/document/9720577/" target="_blank">TEL Research Center America presented at IEDM 2021</a>, focus on providing all the necessary interconnects in the 3D CMOS’s limited space and doing so without significantly increasing the area of the logic cells they make up. The TEL research showed that there are many opportunities for innovation in finding the best interconnect options. That research also highlights that 3D-stacked CMOS will need to have interconnects both above and below the devices. This scheme, called <a href="https://spectrum.ieee.org/next-gen-chips-will-be-powered-from-below" target="_self">buried power rails</a>, takes the interconnects that provide power to logic cells but don’t carry data and removes them to the silicon below the transistors. Intel’s PowerVIA technology, which does just that and is scheduled for introduction in 2024, will therefore play a key role in making 3D-stacked CMOS a commercial reality.</p><h2>The Future of Moore’s Law</h2><p>With RibbonFETs and 3D CMOS, we have a clear path to extend Moore’s Law beyond 2024. In a <a href="https://large.stanford.edu/courses/2012/ph250/lee1/docs/Excepts_A_Conversation_with_Gordon_Moore.pdf" rel="noopener noreferrer" target="_blank">2005 interview</a> in which he was asked to reflect on what became his law, <a href="https://spectrum.ieee.org/tag/gordon-moore">Gordon Moore</a> admitted to being “periodically amazed at how we’re able to make progress. Several times along the way, I thought we reached the end of the line, things taper off, and our creative engineers come up with ways around them.”</p><p>With the move to FinFETs, the ensuing optimizations, and now the development of RibbonFETs and eventually 3D-stacked CMOS, supported by the myriad packaging enhancements around them, we’d like to think Mr. Moore will be amazed yet again.</p></div><div class="rebellt-item ieee-sidebar-fullwidth col1" id="rebelltitem22" data-id="22" data-reload-ads="false" data-is-image="True" data-href="https://spectrum.ieee.org/3d-cmos/particle-22" data-basename="particle-22" data-post-id="2657807330" data-published-at="1669929156" data-use-pagination="False"><img id="71a6c" data-rm-shortcode-id="7032fa6d48912d3b920dff66b8c08541" data-rm-shortcode-name="rebelmouse-image" class="rm-shortcode rm-lazyloadable-image " lazy-loadable="true" src="data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%204408%203306'%3E%3C/svg%3E" data-runner-src="https://spectrum.ieee.org/media-library/image.jpg?id=32243744&width=980" width="4408" height="3306" alt=""/></div><div class="rebellt-item ieee-sidebar-fullwidth-columns col2" id="rebelltitem23" data-id="23" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/the-transistor-at-75" data-basename="the-transistor-at-75" data-post-id="2657807330" data-published-at="1669929156" data-use-pagination="False"><h3 data-role="headline"> The Transistor at 75 </h3><p><strong><a href="https://spectrum.ieee.org/invention-of-the-transistor" target="_self">The Transistor at 75</a></strong></p><p>The past, present, and future of the modern world’s most important invention</p><p><strong><a href="https://spectrum.ieee.org/transistor-history" target="_self">How the First Transistor Worked</a></strong></p><p>Even its inventors didn’t fully understand the point-contact transistor</p><p><strong><a href="https://spectrum.ieee.org/transistor-timeline" target="_self">The Ultimate Transistor Timeline</a></strong></p><p>The transistor’s amazing evolution from point contacts to quantum tunnels</p><p><strong><a href="https://spectrum.ieee.org/transistor-density" target="_self">The State of the Transistor in 3 Charts</a></strong></p><p>In 75 years, it’s become tiny, mighty, ubiquitous, and just plain weird</p></div><div class="rebellt-item ieee-sidebar-fullwidth-columns col2" id="rebelltitem24" data-id="24" data-reload-ads="false" data-is-image="False" data-href="https://spectrum.ieee.org/3d-cmos/particle-24" data-basename="particle-24" data-post-id="2657807330" data-published-at="1669929156" data-use-pagination="False"><p><strong><a href="https://spectrum.ieee.org/3d-cmos" target="_self">3D-Stacked CMOS Takes Moore’s Law to New Heights</a></strong></p><p>When transistors can’t get any smaller, the only direction is up</p><a rel="noopener noreferrer" target="_blank"></a><p><strong><a href="https://spectrum.ieee.org/the-transistor-of-2047-expert-predictions" target="_self">The Transistor of 2047: Expert Predictions</a></strong></p><p>What will the device be like on its 100th anniversary?</p><p><strong><a href="https://spectrum.ieee.org/the-future-of-transistors" target="_self">The Future of the Transistor Is Our Future</a></strong></p><p>Nothing but better devices can tackle humanity’s growing challenges</p><a rel="noopener noreferrer" target="_blank"></a><p><strong><a href="https://spectrum.ieee.org/transistor-music-box" target="_self">John Bardeen’s Terrific Transistorized Music Box</a></strong></p><p>This simple gadget showed off the magic of the first transistor</p></div></p><div class="post-pager js-listicle-pager" data-listicle-style="" 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- IEEE Spectrum"></span><div class="tags"><a class="tags__item" href="https://spectrum.ieee.org/tag/cmos">cmos</a><a class="tags__item" href="https://spectrum.ieee.org/tag/nanoribbon">nanoribbon</a><a class="tags__item" href="https://spectrum.ieee.org/tag/moore-s-law">moore's law</a><a class="tags__item" href="https://spectrum.ieee.org/tag/buried-power-rails">buried power rails</a><a class="tags__item" href="https://spectrum.ieee.org/tag/cfet">cfet</a><a class="tags__item" href="https://spectrum.ieee.org/tag/intel">intel</a><a class="tags__item" href="https://spectrum.ieee.org/tag/nanosheet-transistors">nanosheet transistors</a></div><div class="custom-field-lightbox-img-shortcode-ids">{"imageShortcodeIds":[]}</div></div></div></div><script type="application/json" id="post-context-2657807330" class="post-context post-context-2657807330"> {"customDimensions": {"5":"Marko Radosavljevic, Jack Kavalieros","11":2657807330,"7":"cmos, nanoribbon, moore's law, buried power rails, cfet, intel, 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class="placeholder__button_publish"></div></div><div class="comment-login-wrp"></div></div></div><div class="comment-header"></div><div class="talk--messages"><div class="talk--messages__featured"></div><div class="talk--messages__top_level"><div id="comment-6306571936cdd7dc73e30ed4" class="comment--item approved-comment" data-talk_id="post:2657807330:comments" data-message_id="6306571936cdd7dc73e30ed4" data-parents=""><div class="comment--item-avatar"><img src="https://spectrum.ieee.org/res/avatars/default" title="Kim Hartman" alt="Kim Hartman" loading="lazy" width="38" height="38"/></div><div class="comment--item-text"><span class="comment--item-username">Kim Hartman</span><span class="comment--item-date" title="August 24 2022, 16:51:37">24 Aug, 2022</span><div class="comment--custom-field-grade" data-value="M"> M </div><div class="comment--item-message"><p>In the early '80s Tektronix implemented a 5 layer ECL bipolar IC process capable of high-speed 8-bit A/D conversion at 500MS/s with remarkable effective bits. The process technology was problematic leading to zero yield in some batches. These hot LBT "little bitty transistor" devices made for huge advances in realizing high bandwidth transient recorders as well as paving a way into real-time digital spectrum analysis. Nearly 40 years of advancement, it's about time to go vertical. </p></div><div class="comment--item--action"><div><a href="javascript: void(0);" title="reply" class="comment--item__reply disabled" data-message_id="6306571936cdd7dc73e30ed4" aria-label="reply"><svg class="comment-action-icon" xmlns="http://www.w3.org/2000/svg" width="17" height="17" viewbox="0 0 24 24" aria-hidden="true"><path d="M10 9V5l-7 7 7 7v-4.1c5 0 8.5 1.6 11 5.1-1-5-4-10-11-11z"></path><path d="M0 0h24v24H0z" fill="none"></path></svg></a><a href="javascript: void(0);" title="share" class="comment--item__share disabled" data-message_id="6306571936cdd7dc73e30ed4" aria-label="share"><svg class="comment-action-icon" xmlns="http://www.w3.org/2000/svg" width="17" height="17" viewbox="0 0 24 24" aria-hidden="true"><path d="M0 0h24v24H0z" fill="none"></path><path d="M18 16.08c-.76 0-1.44.3-1.96.77L8.91 12.7c.05-.23.09-.46.09-.7s-.04-.47-.09-.7l7.05-4.11c.54.5 1.25.81 2.04.81 1.66 0 3-1.34 3-3s-1.34-3-3-3-3 1.34-3 3c0 .24.04.47.09.7L8.04 9.81C7.5 9.31 6.79 9 6 9c-1.66 0-3 1.34-3 3s1.34 3 3 3c.79 0 1.5-.31 2.04-.81l7.12 4.16c-.05.21-.08.43-.08.65 0 1.61 1.31 2.92 2.92 2.92 1.61 0 2.92-1.31 2.92-2.92s-1.31-2.92-2.92-2.92z"></path></svg></a><a href="javascript: void(0);" title="like" class="comment--item__like disabled" data-action="like" data-message_id="6306571936cdd7dc73e30ed4" aria-label="like"><svg class="comment-action-icon" xmlns="http://www.w3.org/2000/svg" width="17" height="17" viewbox="0 0 24 24" aria-hidden="true"><path fill="none" d="M0 0h24v24H0V0z"></path><path d="M1 21h4V9H1v12zm22-11c0-1.1-.9-2-2-2h-6.31l.95-4.57.03-.32c0-.41-.17-.79-.44-1.06L14.17 1 7.59 7.59C7.22 7.95 7 8.45 7 9v10c0 1.1.9 2 2 2h9c.83 0 1.54-.5 1.84-1.22l3.02-7.05c.09-.23.14-.47.14-.73v-2z"></path></svg></a><a href="javascript: void(0);" title="unlike" class="comment--item__dislike disabled" data-action="dislike" data-message_id="6306571936cdd7dc73e30ed4" aria-label="unlike"><svg class="comment-action-icon" xmlns="http://www.w3.org/2000/svg" width="17" height="17" viewbox="0 0 24 24" aria-hidden="true"><path fill="none" d="M0 0h24v24H0z"></path><path d="M15 3H6c-.83 0-1.54.5-1.84 1.22l-3.02 7.05c-.09.23-.14.47-.14.73v2c0 1.1.9 2 2 2h6.31l-.95 4.57-.03.32c0 .41.17.79.44 1.06L9.83 23l6.59-6.59c.36-.36.58-.86.58-1.41V5c0-1.1-.9-2-2-2zm4 0v12h4V3h-4z"></path></svg></a></div></div><div class="comment-login-wrp"></div></div><div class="replies level-two hidden"><a href="javascript: void(0);" class="comment--show--replies" data-message_id="6306571936cdd7dc73e30ed4" aria-label="show replies"><svg xmlns="http://www.w3.org/2000/svg" width="16" height="16" viewbox="0 0 24 24" aria-hidden="true"><path d="M16.59 8.59L12 13.17 7.41 8.59 6 10l6 6 6-6z"></path><path d="M0 0h24v24H0z" fill="none"></path></svg><span class="comment--count">0</span> Replies </a><a href="javascript: void(0);" class="comment--hide--replies hidden" data-message_id="6306571936cdd7dc73e30ed4" aria-label="hide replies"><svg xmlns="http://www.w3.org/2000/svg" width="16" height="16" viewbox="0 0 24 24" aria-hidden="true"><path d="M12 8l-6 6 1.41 1.41L12 10.83l4.59 4.58L18 14z"></path><path d="M0 0h24v24H0z" fill="none"></path></svg> Hide replies </a><div class="reply-items hidden"></div><div class="talk--load_more__replies hidden" data-message_id="6306571936cdd7dc73e30ed4">Show More Replies</div></div></div></div></div><script type="rm-preact-state">{"authors": {"23643744": {"id": 25324470, "path": "u/kim-hartman", "title": "Kim Hartman", "image": "https://spectrum.ieee.org/res/avatars/default", "about": "", "rating": 0, "owner_id": 23643744, "site_specific_data": {"member_badges": null, "Instagram": null, "grade": "M", "affiliation": null, "LinkedIn": null, "Facebook": null, "Twitter": null, "works_for": null, "alumni_of": null, "member_of": null, "first_name": "Kim", "last_name": "Hartman", "job_title": null, "mini_bio": null}}}, "forcedComments": [], "topLevelComments": [{"id": "6306571936cdd7dc73e30ed4", "html": "\u003cp\u003eIn the early '80s Tektronix implemented a 5 layer ECL bipolar IC process capable of high-speed 8-bit A/D conversion at 500MS/s with remarkable effective bits. The process technology was problematic leading to zero yield in some batches. These hot LBT \"little bitty transistor\" devices made for huge advances in realizing high bandwidth transient recorders as well as paving a way into real-time digital spectrum analysis. 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