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href="https://ar.wikipedia.org/wiki/%D9%85%D9%86%D8%B7%D9%82_%D8%AA%D8%B3%D9%84%D8%B3%D9%84%D9%8A" title="منطق تسلسلي – Arabic" lang="ar" hreflang="ar" data-title="منطق تسلسلي" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%9F%D0%BE%D1%81%D0%BB%D0%B5%D0%B4%D0%BE%D0%B2%D0%B0%D1%82%D0%B5%D0%BB%D0%BD%D0%B0_%D0%BB%D0%BE%D0%B3%D0%B8%D1%87%D0%B5%D1%81%D0%BA%D0%B0_%D1%81%D1%85%D0%B5%D0%BC%D0%B0" title="Последователна логическа схема – Bulgarian" lang="bg" hreflang="bg" data-title="Последователна логическа схема" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Sistema_digital_seq%C3%BCencial" title="Sistema digital seqüencial – Catalan" lang="ca" hreflang="ca" data-title="Sistema digital seqüencial" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Sekven%C4%8Dn%C3%AD_obvod" title="Sekvenční obvod – Czech" lang="cs" hreflang="cs" data-title="Sekvenční obvod" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Schaltwerk_(Technische_Informatik)" title="Schaltwerk (Technische Informatik) – German" lang="de" hreflang="de" data-title="Schaltwerk (Technische Informatik)" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Sistema_secuencial" title="Sistema secuencial – Spanish" lang="es" hreflang="es" data-title="Sistema secuencial" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/Logika_sekuentzial" title="Logika sekuentzial – Basque" lang="eu" hreflang="eu" data-title="Logika sekuentzial" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%85%D9%86%D8%B7%D9%82_%D8%AA%D8%B1%D8%AA%DB%8C%D8%A8%DB%8C" title="منطق ترتیبی – Persian" lang="fa" hreflang="fa" data-title="منطق ترتیبی" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Logique_s%C3%A9quentielle" title="Logique séquentielle – French" lang="fr" hreflang="fr" data-title="Logique séquentielle" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%88%9C%EC%B0%A8_%EB%85%BC%EB%A6%AC" title="순차 논리 – Korean" lang="ko" hreflang="ko" data-title="순차 논리" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hi mw-list-item"><a href="https://hi.wikipedia.org/wiki/%E0%A4%85%E0%A4%A8%E0%A5%81%E0%A4%95%E0%A5%8D%E0%A4%B0%E0%A4%AE%E0%A4%BF%E0%A4%95_%E0%A4%B2%E0%A5%89%E0%A4%9C%E0%A4%BF%E0%A4%95" title="अनुक्रमिक लॉजिक – Hindi" lang="hi" hreflang="hi" data-title="अनुक्रमिक लॉजिक" data-language-autonym="हिन्दी" data-language-local-name="Hindi" class="interlanguage-link-target"><span>हिन्दी</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Sekvencijalni_sklop" title="Sekvencijalni sklop – Croatian" lang="hr" hreflang="hr" data-title="Sekvencijalni sklop" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Circuito_sequenziale" title="Circuito sequenziale – Italian" lang="it" hreflang="it" data-title="Circuito sequenziale" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%9E%D7%A2%D7%92%D7%9C_%D7%A1%D7%93%D7%A8%D7%AA%D7%99" title="מעגל סדרתי – Hebrew" lang="he" hreflang="he" data-title="מעגל סדרתי" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Szekvenci%C3%A1lis_logika" title="Szekvenciális logika – Hungarian" lang="hu" hreflang="hu" data-title="Szekvenciális logika" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Volgordeschakeling" title="Volgordeschakeling – Dutch" lang="nl" hreflang="nl" data-title="Volgordeschakeling" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E9%A0%86%E5%BA%8F%E5%9B%9E%E8%B7%AF" title="順序回路 – Japanese" lang="ja" hreflang="ja" data-title="順序回路" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Uk%C5%82ad_sekwencyjny" title="Układ sekwencyjny – Polish" lang="pl" hreflang="pl" data-title="Układ sekwencyjny" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/L%C3%B3gica_sequencial" title="Lógica sequencial – Portuguese" lang="pt" hreflang="pt" data-title="Lógica sequencial" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%A1%D0%B5%D0%BA%D0%B2%D0%B5%D0%BD%D1%86%D0%B8%D0%B0%D0%BB%D1%8C%D0%BD%D0%B0%D1%8F_%D0%BB%D0%BE%D0%B3%D0%B8%D0%BA%D0%B0" title="Секвенциальная логика – Russian" lang="ru" hreflang="ru" data-title="Секвенциальная логика" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Sekven%C4%8Dn%C3%BD_obvod" title="Sekvenčný obvod – Slovak" lang="sk" hreflang="sk" data-title="Sekvenčný obvod" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%A7%E0%B8%87%E0%B8%88%E0%B8%A3%E0%B9%80%E0%B8%8A%E0%B8%B4%E0%B8%87%E0%B8%A5%E0%B8%B3%E0%B8%94%E0%B8%B1%E0%B8%9A" title="วงจรเชิงลำดับ – Thai" lang="th" hreflang="th" data-title="วงจรเชิงลำดับ" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/S%C4%B1ral%C4%B1_mant%C4%B1k" title="Sıralı mantık – Turkish" lang="tr" hreflang="tr" data-title="Sıralı mantık" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%A1%D0%B5%D0%BA%D0%B2%D0%B5%D0%BD%D1%86%D1%96%D0%B9%D0%BD%D0%B0_%D0%BB%D0%BE%D0%B3%D1%96%D0%BA%D0%B0" title="Секвенційна логіка – Ukrainian" lang="uk" hreflang="uk" data-title="Секвенційна логіка" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a 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.hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"Sequential circuit" redirects here. For the synthesizer company, see <a href="/wiki/Sequential_Circuits" class="mw-redirect" title="Sequential Circuits">Sequential Circuits</a>.</div> <p> In <a href="/wiki/Automata_theory" title="Automata theory">automata theory</a>, <b>sequential logic</b> is a type of <a href="/wiki/Logic_circuit" class="mw-redirect" title="Logic circuit">logic circuit</a> whose output depends on the present value of its input signals and on the <a href="/wiki/Sequence" title="Sequence">sequence</a> of past inputs, the input history.<sup id="cite_ref-Vai_2000_1-0" class="reference"><a href="#cite_note-Vai_2000-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Cavanagh_2006_2-0" class="reference"><a href="#cite_note-Cavanagh_2006-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Lipiansky_2012_3-0" class="reference"><a href="#cite_note-Lipiansky_2012-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Dally-Harting_2012_4-0" class="reference"><a href="#cite_note-Dally-Harting_2012-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> This is in contrast to <i><a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a></i>, whose output is a function of only the present input. That is, sequential logic has <i><a href="/wiki/State_(computer_science)" title="State (computer science)">state</a></i> (<i>memory</i>) while combinational logic does not. </p><p>Sequential logic is used to construct <a href="/wiki/Finite-state_machine" title="Finite-state machine">finite-state machines</a>, a basic building block in all digital circuitry. Virtually all circuits in practical digital devices are a mixture of combinational and sequential logic. </p><p>A familiar example of a device with sequential logic is a <a href="/wiki/Television_set" title="Television set">television set</a> with "channel up" and "channel down" buttons.<sup id="cite_ref-Vai_2000_1-1" class="reference"><a href="#cite_note-Vai_2000-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Pressing the "up" button gives the television an input telling it to switch to the next channel above the one it is currently receiving. If the television is on channel 5, pressing "up" switches it to receive channel 6. However, if the television is on channel 8, pressing "up" switches it to channel "9". In order for the channel selection to operate correctly, the television must be aware of which channel it is currently receiving, which was determined by past channel selections.<sup id="cite_ref-Vai_2000_1-2" class="reference"><a href="#cite_note-Vai_2000-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The television stores the current channel as part of its <i><a href="/wiki/State_(computer_science)" title="State (computer science)">state</a></i>. When a "channel up" or "channel down" input is given to it, the sequential logic of the channel selection circuitry calculates the new channel from the input and the current channel. </p><p>Digital sequential logic circuits are divided into <a href="/wiki/Synchronous_logic" class="mw-redirect" title="Synchronous logic">synchronous</a> and <a href="/wiki/Asynchronous_logic" class="mw-redirect" title="Asynchronous logic">asynchronous</a> types. In synchronous sequential circuits, the state of the device changes only at discrete times in response to a <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a>. In asynchronous circuits the state of the device can change at any time in response to changing inputs. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Synchronous_sequential_logic">Synchronous sequential logic</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Sequential_logic&action=edit&section=1" title="Edit section: Synchronous sequential logic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Nearly all sequential logic today is <i>clocked</i> or <i>synchronous</i> logic. In a synchronous circuit, an <a href="/wiki/Electronic_oscillator" title="Electronic oscillator">electronic oscillator</a> called a <i>clock</i> (or <a href="/wiki/Clock_generator" title="Clock generator">clock generator</a>) generates a sequence of repetitive pulses called the <i><a href="/wiki/Clock_signal" title="Clock signal">clock signal</a></i> which is distributed to all the memory elements in the circuit. The basic memory element in synchronous logic is the <a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flop</a>. The output of each flip-flop only changes when triggered by the clock pulse, so changes to the logic signals throughout the circuit all begin at the same time, at regular intervals, synchronized by the clock. </p><p>The output of all the storage elements (flip-flops) in the circuit at any given time, the binary data they contain, is called the <i><a href="/wiki/State_(computer_science)" title="State (computer science)">state</a></i> of the circuit. The state of the synchronous circuit only changes on clock pulses. At each cycle, the next state is determined by the current state and the value of the input signals when the clock pulse occurs. </p><p>The main advantage of synchronous logic is its simplicity. The logic gates which perform the operations on the data require a finite amount of time to respond to changes to their inputs. This is called <i><a href="/wiki/Propagation_delay" title="Propagation delay">propagation delay</a></i>. The interval between clock pulses must be long enough so that all the logic gates have time to respond to the changes and their outputs "settle" to stable logic values before the next clock pulse occurs. As long as this condition is met (ignoring certain other details) the circuit is guaranteed to be stable and reliable. This determines the maximum operating speed of the synchronous circuit. </p><p>Synchronous logic has two main disadvantages: </p> <ul><li>The maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise known as the critical path. Every logical calculation, from the simplest to the most complex, must complete in one clock cycle. So logic paths that complete their calculations quickly are idle much of the time, waiting for the next clock pulse. Therefore, synchronous logic can be slower than asynchronous logic. One way to speed up synchronous circuits is to split complex operations into several simple operations which can be performed in successive clock cycles, a technique known as <i><a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipelining</a></i>. This technique is extensively used in <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> design and helps to improve the performance of modern processors.</li> <li>The clock signal must be distributed to every flip-flop in the circuit. As the clock is usually a high-frequency signal, this distribution consumes a relatively large amount of power and dissipates much heat. Even the flip-flops that are doing nothing consume a small amount of power, thereby generating <a href="/wiki/Waste_heat" title="Waste heat">waste heat</a> in the chip. In battery-powered devices, additional hardware and software complexity is required to reduce the clock speed or temporarily turn off the clock while the device is not being actively used, in order to maintain a usable battery life.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Asynchronous_sequential_logic"><span class="anchor" id="Venjunction"></span><span class="anchor" id="Sequention"></span>Asynchronous sequential logic</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Sequential_logic&action=edit&section=2" title="Edit section: Asynchronous sequential logic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous circuit</a></div> <p><i>Asynchronous</i> (<i>clockless</i> or <i>self-timed</i>) <i>sequential logic</i> is not synchronized by a clock signal; the outputs of the circuit change directly in response to changes in inputs. The advantage of asynchronous logic is that it can be faster than synchronous logic, because the circuit doesn't have to wait for a clock signal to process inputs. The speed of the device is potentially limited only by the <a href="/wiki/Propagation_delay" title="Propagation delay">propagation delays</a> of the <a href="/wiki/Logic_gate" title="Logic gate">logic gates</a> used. </p><p>However, asynchronous logic is more difficult to design and is subject to problems not encountered in synchronous designs. The main problem is that digital memory elements are sensitive to the order that their input signals arrive; if two signals arrive at a <a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flop</a> or latch at almost the same time, which state the circuit goes into can depend on which signal gets to the gate first. Therefore, the circuit can go into the wrong state, depending on small differences in the <a href="/wiki/Propagation_delay" title="Propagation delay">propagation delays</a> of the logic gates. This is called a <a href="/wiki/Race_condition" title="Race condition">race condition</a>. This problem is not as severe in synchronous circuits because the outputs of the memory elements only change at each clock pulse. The interval between clock signals is designed to be long enough to allow the outputs of the memory elements to "settle" so they are not changing when the next clock comes. Therefore, the only timing problems are due to "asynchronous inputs"; inputs to the circuit from other systems which are not synchronized to the clock signal. </p><p>Asynchronous sequential circuits are typically used only in a few critical parts of otherwise synchronous systems where speed is at a premium, such as parts of microprocessors and <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> circuits. </p><p>The design of asynchronous logic uses different mathematical models and techniques from synchronous logic, and is an active area of research. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Sequential_logic&action=edit&section=3" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous circuit</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous circuit</a></li> <li><a href="/wiki/Logic_design" class="mw-redirect" title="Logic design">Logic design</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Sequential_logic&action=edit&section=4" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-Vai_2000-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-Vai_2000_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Vai_2000_1-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Vai_2000_1-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFVai2000" class="citation book cs1">Vai, M. Michael (2000). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=x9VicwHqocYC&q=%22sequential+logic%22+history+inputs+state&pg=PA147"><i>VLSI Design</i></a>. <a href="/wiki/CRC_Press" title="CRC Press">CRC Press</a>. p. 147. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-84931876-9" title="Special:BookSources/0-84931876-9"><bdi>0-84931876-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=VLSI+Design&rft.pages=147&rft.pub=CRC+Press&rft.date=2000&rft.isbn=0-84931876-9&rft.aulast=Vai&rft.aufirst=M.+Michael&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dx9VicwHqocYC%26q%3D%2522sequential%2Blogic%2522%2Bhistory%2Binputs%2Bstate%26pg%3DPA147&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></span> </li> <li id="cite_note-Cavanagh_2006-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Cavanagh_2006_2-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCavanagh2006" class="citation book cs1">Cavanagh, Joseph (2006). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=ryz8UbjBfWAC&q=history+%22sequential+logic&pg=PR11"><i>Sequential Logic: Analysis and Synthesis</i></a>. <a href="/wiki/CRC_Press" title="CRC Press">CRC Press</a>. p. ix. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-84937564-9" title="Special:BookSources/0-84937564-9"><bdi>0-84937564-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Sequential+Logic%3A+Analysis+and+Synthesis&rft.pages=ix&rft.pub=CRC+Press&rft.date=2006&rft.isbn=0-84937564-9&rft.aulast=Cavanagh&rft.aufirst=Joseph&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dryz8UbjBfWAC%26q%3Dhistory%2B%2522sequential%2Blogic%26pg%3DPR11&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></span> </li> <li id="cite_note-Lipiansky_2012-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-Lipiansky_2012_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLipiansky2012" class="citation book cs1">Lipiansky, Ed (2012). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=oe31X8WoZnAC&q=%22sequential+logic%22+history+inputs&pg=SA8-PA39"><i>Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers</i></a>. <a href="/wiki/Wiley_(publisher)" title="Wiley (publisher)">Wiley</a>. p. 8.39. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-11841454-5" title="Special:BookSources/978-1-11841454-5"><bdi>978-1-11841454-5</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Electrical%2C+Electronics%2C+and+Digital+Hardware+Essentials+for+Scientists+and+Engineers&rft.pages=8.39&rft.pub=Wiley&rft.date=2012&rft.isbn=978-1-11841454-5&rft.aulast=Lipiansky&rft.aufirst=Ed&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Doe31X8WoZnAC%26q%3D%2522sequential%2Blogic%2522%2Bhistory%2Binputs%26pg%3DSA8-PA39&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></span> </li> <li id="cite_note-Dally-Harting_2012-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-Dally-Harting_2012_4-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDallyHarting2012" class="citation book cs1"><a href="/wiki/William_James_Dally" class="mw-redirect" title="William James Dally">Dally, William James</a>; Harting, R. Curtis (2012). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=WLoHOG0MhbIC&q=%22sequential+logic%22+history+inputs&pg=PA291"><i>Digital Design: A Systems Approach</i></a>. <a href="/wiki/Cambridge_University_Press" title="Cambridge University Press">Cambridge University Press</a>. p. 291. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-52119950-6" title="Special:BookSources/978-0-52119950-6"><bdi>978-0-52119950-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Digital+Design%3A+A+Systems+Approach&rft.pages=291&rft.pub=Cambridge+University+Press&rft.date=2012&rft.isbn=978-0-52119950-6&rft.aulast=Dally&rft.aufirst=William+James&rft.au=Harting%2C+R.+Curtis&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DWLoHOG0MhbIC%26q%3D%2522sequential%2Blogic%2522%2Bhistory%2Binputs%26pg%3DPA291&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Sequential_logic&action=edit&section=5" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKatzBorriello2005" class="citation book cs1"><a href="/wiki/Randy_Katz" title="Randy Katz">Katz, Randy</a>; <a href="/wiki/Gaetano_Borriello" title="Gaetano Borriello">Borriello, Gaetano</a> (2005). <i>Contemporary Logic Design</i> (2 ed.). <a href="/wiki/Prentice_Hall" title="Prentice Hall">Prentice Hall</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-201-30857-6" title="Special:BookSources/0-201-30857-6"><bdi>0-201-30857-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Contemporary+Logic+Design&rft.edition=2&rft.pub=Prentice+Hall&rft.date=2005&rft.isbn=0-201-30857-6&rft.aulast=Katz&rft.aufirst=Randy&rft.au=Borriello%2C+Gaetano&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKohaviJha2009" class="citation book cs1">Kohavi, Zvi; Jha, Niraj K. (2009). <i>Switching and Finite Automata Theory</i> (3 ed.). <a href="/wiki/Cambridge_University_Press" title="Cambridge University Press">Cambridge University Press</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-521-85748-2" title="Special:BookSources/978-0-521-85748-2"><bdi>978-0-521-85748-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Switching+and+Finite+Automata+Theory&rft.edition=3&rft.pub=Cambridge+University+Press&rft.date=2009&rft.isbn=978-0-521-85748-2&rft.aulast=Kohavi&rft.aufirst=Zvi&rft.au=Jha%2C+Niraj+K.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFVasyukevich2009" class="citation web cs1">Vasyukevich, Vadim O. (2009). <a rel="nofollow" class="external text" href="http://asynlog.balticom.lv/Content/Files/en.pdf">"Asynchronous logic elements. Venjunction and sequention"</a> <span class="cs1-format">(PDF)</span>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110722160840/http://asynlog.balticom.lv/Content/Files/en.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2011-07-22.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Asynchronous+logic+elements.+Venjunction+and+sequention&rft.date=2009&rft.aulast=Vasyukevich&rft.aufirst=Vadim+O.&rft_id=http%3A%2F%2Fasynlog.balticom.lv%2FContent%2FFiles%2Fen.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span> (118 pages)</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFVasyukevich2011" class="citation book cs1 cs1-prop-location-test">Vasyukevich, Vadim O. (2011). Written at Riga, Latvia. <i>Asynchronous Operators of Sequential Logic: Venjunction & Sequention — Digital Circuits Analysis and Design</i>. Lecture Notes in Electrical Engineering (LNEE). Vol. 101 (1 ed.). Berlin / Heidelberg, Germany: <a href="/wiki/Springer-Verlag" class="mw-redirect" title="Springer-Verlag">Springer-Verlag</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2F978-3-642-21611-4">10.1007/978-3-642-21611-4</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-642-21610-7" title="Special:BookSources/978-3-642-21610-7"><bdi>978-3-642-21610-7</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1876-1100">1876-1100</a>. <a href="/wiki/LCCN_(identifier)" class="mw-redirect" title="LCCN (identifier)">LCCN</a> <a rel="nofollow" class="external text" href="https://lccn.loc.gov/2011929655">2011929655</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Asynchronous+Operators+of+Sequential+Logic%3A+Venjunction+%26+Sequention+%E2%80%94+Digital+Circuits+Analysis+and+Design&rft.place=Berlin+%2F+Heidelberg%2C+Germany&rft.series=Lecture+Notes+in+Electrical+Engineering+%28LNEE%29&rft.edition=1&rft.pub=Springer-Verlag&rft.date=2011&rft_id=info%3Adoi%2F10.1007%2F978-3-642-21611-4&rft.issn=1876-1100&rft_id=info%3Alccn%2F2011929655&rft.isbn=978-3-642-21610-7&rft.aulast=Vasyukevich&rft.aufirst=Vadim+O.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASequential+logic" class="Z3988"></span> (xiii+1+123+7 pages) (NB. The back cover of this book erroneously states volume 4, whereas it actually is volume 101.)</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist 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electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a class="mw-selflink selflink">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=Sequential_logic&oldid=1157202833">https://en.wikipedia.org/w/index.php?title=Sequential_logic&oldid=1157202833</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Automata_(computation)" title="Category:Automata (computation)">Automata (computation)</a></li><li><a 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