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field-programmable gate array (FPGA)</title> <meta name="description" content="Search results for: field-programmable gate array (FPGA)"> <meta name="keywords" content="field-programmable gate array (FPGA)"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science 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method="get" action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="field-programmable gate array (FPGA)"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 1072</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: field-programmable gate array (FPGA)</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1072</span> High Performance Field Programmable Gate Array-Based Stochastic Low-Density Parity-Check Decoder Design for IEEE 802.3an Standard </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ghania%20Zerari">Ghania Zerari</a>, <a href="https://publications.waset.org/abstracts/search?q=Abderrezak%20Guessoum"> Abderrezak Guessoum</a>, <a href="https://publications.waset.org/abstracts/search?q=Rachid%20Beguenane"> Rachid Beguenane</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper introduces high-performance architecture for fully parallel stochastic Low-Density Parity-Check (LDPC) field programmable gate array (FPGA) based LDPC decoder. The new approach is designed to decrease the decoding latency and to reduce the FPGA logic utilisation. To accomplish the target logic utilisation reduction, the routing of the proposed sub-variable node (VN) internal memory is designed to utilize one slice distributed RAM. Furthermore, a VN initialization, using the channel input probability, is achieved to enhance the decoder convergence, without extra resources and without integrating the output saturated-counters. The Xilinx FPGA implementation, of IEEE 802.3an standard LDPC code, shows that the proposed decoding approach attain high performance along with reduction of FPGA logic utilisation. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=low-density%20parity-check%20%28LDPC%29%20decoder" title="low-density parity-check (LDPC) decoder">low-density parity-check (LDPC) decoder</a>, <a href="https://publications.waset.org/abstracts/search?q=stochastic%20decoding" title=" stochastic decoding"> stochastic decoding</a>, <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array%20%28FPGA%29" title=" field programmable gate array (FPGA)"> field programmable gate array (FPGA)</a>, <a href="https://publications.waset.org/abstracts/search?q=IEEE%20802.3an%20standard" title=" IEEE 802.3an standard"> IEEE 802.3an standard</a> </p> <a href="https://publications.waset.org/abstracts/81538/high-performance-field-programmable-gate-array-based-stochastic-low-density-parity-check-decoder-design-for-ieee-8023an-standard" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/81538.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">297</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1071</span> A Survey of Field Programmable Gate Array-Based Convolutional Neural Network Accelerators</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Wei%20Zhang">Wei Zhang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the rapid development of deep learning, neural network and deep learning algorithms play a significant role in various practical applications. Due to the high accuracy and good performance, Convolutional Neural Networks (CNNs) especially have become a research hot spot in the past few years. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses a significant challenge to construct a high-performance implementation of deep learning neural networks. Meanwhile, many of these application scenarios also have strict requirements on the performance and low-power consumption of hardware devices. Therefore, it is particularly critical to choose a moderate computing platform for hardware acceleration of CNNs. This article aimed to survey the recent advance in Field Programmable Gate Array (FPGA)-based acceleration of CNNs. Various designs and implementations of the accelerator based on FPGA under different devices and network models are overviewed, and the versions of Graphic Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs) are compared to present our own critical analysis and comments. Finally, we give a discussion on different perspectives of these acceleration and optimization methods on FPGA platforms to further explore the opportunities and challenges for future research. More helpfully, we give a prospect for future development of the FPGA-based accelerator. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=deep%20learning" title="deep learning">deep learning</a>, <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title=" field programmable gate array"> field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20accelerator" title=" hardware accelerator"> hardware accelerator</a>, <a href="https://publications.waset.org/abstracts/search?q=convolutional%20neural%20networks" title=" convolutional neural networks"> convolutional neural networks</a>, <a href="https://publications.waset.org/abstracts/search?q=CNN" title=" CNN"> CNN</a> </p> <a href="https://publications.waset.org/abstracts/128017/a-survey-of-field-programmable-gate-array-based-convolutional-neural-network-accelerators" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/128017.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">128</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1070</span> Numerical Solution Speedup of the Laplace Equation Using FPGA Hardware</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abbas%20Ebrahimi">Abbas Ebrahimi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Zandsalimy"> Mohammad Zandsalimy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=accelerating%20numerical%20solutions" title="accelerating numerical solutions">accelerating numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=CFD" title=" CFD"> CFD</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20definition%20language" title=" hardware definition language"> hardware definition language</a>, <a href="https://publications.waset.org/abstracts/search?q=numerical%20solutions" title=" numerical solutions"> numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20hardware" title=" reconfigurable hardware"> reconfigurable hardware</a> </p> <a href="https://publications.waset.org/abstracts/68002/numerical-solution-speedup-of-the-laplace-equation-using-fpga-hardware" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68002.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">383</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1069</span> Field-Programmable Gate Array Based Tester for Protective Relay </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=H.%20Bentarzi">H. Bentarzi</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Zitouni"> A. Zitouni</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=amplifier%20class%20D" title="amplifier class D">amplifier class D</a>, <a href="https://publications.waset.org/abstracts/search?q=field-programmable%20gate%20array%20%28FPGA%29" title=" field-programmable gate array (FPGA)"> field-programmable gate array (FPGA)</a>, <a href="https://publications.waset.org/abstracts/search?q=protective%20relay" title=" protective relay"> protective relay</a>, <a href="https://publications.waset.org/abstracts/search?q=tester" title=" tester"> tester</a> </p> <a href="https://publications.waset.org/abstracts/74115/field-programmable-gate-array-based-tester-for-protective-relay" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/74115.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">216</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1068</span> FPGA Implementation of the BB84 Protocol</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jaouadi%20Ikram">Jaouadi Ikram</a>, <a href="https://publications.waset.org/abstracts/search?q=Machhout%20Mohsen"> Machhout Mohsen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=QKD" title="QKD">QKD</a>, <a href="https://publications.waset.org/abstracts/search?q=BB84" title=" BB84"> BB84</a>, <a href="https://publications.waset.org/abstracts/search?q=protocol" title=" protocol"> protocol</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptography" title=" cryptography"> cryptography</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=key" title=" key"> key</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=communication" title=" communication"> communication</a> </p> <a href="https://publications.waset.org/abstracts/98812/fpga-implementation-of-the-bb84-protocol" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/98812.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">183</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1067</span> Design of Local Interconnect Network Controller for Automotive Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jong-Bae%20Lee">Jong-Bae Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Seongsoo%20Lee"> Seongsoo Lee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=local%20interconnect%20network" title="local interconnect network">local interconnect network</a>, <a href="https://publications.waset.org/abstracts/search?q=controller" title=" controller"> controller</a>, <a href="https://publications.waset.org/abstracts/search?q=transceiver" title=" transceiver"> transceiver</a>, <a href="https://publications.waset.org/abstracts/search?q=processor" title=" processor"> processor</a> </p> <a href="https://publications.waset.org/abstracts/60861/design-of-local-interconnect-network-controller-for-automotive-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/60861.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">288</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1066</span> Run-Time Customisation of Soft-Core CPUs on Field Programmable Gate Array</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rehab%20Abdullah%20Shendi">Rehab Abdullah Shendi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=customisation" title="customisation">customisation</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=MIPS" title=" MIPS"> MIPS</a>, <a href="https://publications.waset.org/abstracts/search?q=partial%20reconfiguration" title=" partial reconfiguration"> partial reconfiguration</a>, <a href="https://publications.waset.org/abstracts/search?q=PR" title=" PR"> PR</a> </p> <a href="https://publications.waset.org/abstracts/51763/run-time-customisation-of-soft-core-cpus-on-field-programmable-gate-array" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/51763.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">267</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1065</span> FPGA Implementation of Novel Triangular Systolic Array Based Architecture for Determining the Eigenvalues of Matrix</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Soumitr%20Sanjay%20Dubey">Soumitr Sanjay Dubey</a>, <a href="https://publications.waset.org/abstracts/search?q=Shubhajit%20Roy%20Chowdhury"> Shubhajit Roy Chowdhury</a>, <a href="https://publications.waset.org/abstracts/search?q=Rahul%20Shrestha"> Rahul Shrestha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we have presented a novel approach of calculating eigenvalues of any matrix for the first time on Field Programmable Gate Array (FPGA) using Triangular Systolic Arra (TSA) architecture. Conventionally, additional computation unit is required in the architecture which is compliant to the algorithm for determining the eigenvalues and this in return enhances the delay and power consumption. However, recently reported works are only dedicated for symmetric matrices or some specific case of matrix. This works presents an architecture to calculate eigenvalues of any matrix based on QR algorithm which is fully implementable on FPGA. For the implementation of QR algorithm we have used TSA architecture, which is further utilising CORDIC (CO-ordinate Rotation DIgital Computer) algorithm, to calculate various trigonometric and arithmetic functions involved in the procedure. The proposed architecture gives an error in the range of 10−4. Power consumption by the design is 0.598W. It can work at the frequency of 900 MHz. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=coordinate%20rotation%20digital%20computer" title="coordinate rotation digital computer">coordinate rotation digital computer</a>, <a href="https://publications.waset.org/abstracts/search?q=three%20angle%20complex%20rotation" title=" three angle complex rotation"> three angle complex rotation</a>, <a href="https://publications.waset.org/abstracts/search?q=triangular%20systolic%20array" title=" triangular systolic array"> triangular systolic array</a>, <a href="https://publications.waset.org/abstracts/search?q=QR%20algorithm" title=" QR algorithm "> QR algorithm </a> </p> <a href="https://publications.waset.org/abstracts/40252/fpga-implementation-of-novel-triangular-systolic-array-based-architecture-for-determining-the-eigenvalues-of-matrix" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/40252.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">415</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1064</span> Embedded Hw-Sw Reconfigurable Techniques For Wireless Sensor Network Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Kirubakaran">B. Kirubakaran</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Rajasekaran"> C. Rajasekaran </a> </p> <p class="card-text"><strong>Abstract:</strong></p> Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title="field programmable gate array">field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=peripheral%20interrupt%20controller" title=" peripheral interrupt controller"> peripheral interrupt controller</a>, <a href="https://publications.waset.org/abstracts/search?q=runtime%20reconfigurable%20techniques" title=" runtime reconfigurable techniques"> runtime reconfigurable techniques</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20sensor%20networks" title=" wireless sensor networks"> wireless sensor networks</a> </p> <a href="https://publications.waset.org/abstracts/5897/embedded-hw-sw-reconfigurable-techniques-for-wireless-sensor-network-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/5897.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">407</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1063</span> Agile Real-Time Field Programmable Gate Array-Based Image Processing System for Drone Imagery in Digital Agriculture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sabiha%20Shahid%20Antora">Sabiha Shahid Antora</a>, <a href="https://publications.waset.org/abstracts/search?q=Young%20Ki%20Chang"> Young Ki Chang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Along with various farm management technologies, imagery is an important tool that facilitates crop assessment, monitoring, and management. As a consequence, drone imaging technology is playing a vital role to capture the state of the entire field for yield mapping, crop scouting, weed detection, and so on. Although it is essential to inspect the cultivable lands in real-time for making rapid decisions regarding field variable inputs to combat stresses and diseases, drone imagery is still evolving in this area of interest. Cost margin and post-processing complexions of the image stream are the main challenges of imaging technology. Therefore, this proposed project involves the cost-effective field programmable gate array (FPGA) based image processing device that would process the image stream in real-time as well as providing the processed output to support on-the-spot decisions in the crop field. As a result, the real-time FPGA-based image processing system would reduce operating costs while minimizing a few intermediate steps to deliver scalable field decisions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=real-time" title="real-time">real-time</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=drone%20imagery" title=" drone imagery"> drone imagery</a>, <a href="https://publications.waset.org/abstracts/search?q=image%20processing" title=" image processing"> image processing</a>, <a href="https://publications.waset.org/abstracts/search?q=crop%20monitoring" title=" crop monitoring"> crop monitoring</a> </p> <a href="https://publications.waset.org/abstracts/132611/agile-real-time-field-programmable-gate-array-based-image-processing-system-for-drone-imagery-in-digital-agriculture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/132611.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">113</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1062</span> Field-Programmable Gate Array-Based Baseband Signals Generator of X-Band Transmitter for Micro Satellite/CubeSat</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shih-Ming%20Wang">Shih-Ming Wang</a>, <a href="https://publications.waset.org/abstracts/search?q=Chun-Kai%20Yeh"> Chun-Kai Yeh</a>, <a href="https://publications.waset.org/abstracts/search?q=Ming-Hwang%20Shie"> Ming-Hwang Shie</a>, <a href="https://publications.waset.org/abstracts/search?q=Tai-Wei%20Lin"> Tai-Wei Lin</a>, <a href="https://publications.waset.org/abstracts/search?q=Chieh-Fu%20Chang"> Chieh-Fu Chang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper introduces a FPGA-based baseband signals generator (BSG) of X-band transmitter developed by National Space Organization (NSPO), Taiwan, for earth observation. In order to gain more flexibility for various applications, a number of modulation schemes, QPSK, DeQPSK and 8PSK 4D-TCM are included. For micro satellite scenario, the maximum symbol rate is up to 150Mbsps, and the EVM is as low as 1.9%. For CubeSat scenario, the maximum symbol rate is up to 60Mbsps, and the EVM is less than 1.7%. The maximum data rates are 412.5Mbps and 165Mbps, respectively. Besides, triple modular redundancy (TMR) scheme is implemented in order to reduce single event effect (SEE) induced by radiation. Finally, the theoretical error performance is provided based on comprehensive analysis, especially when BER is lower and much lower than 10⁻⁶ due to low error bit requirement of modern high-resolution earth remote-sensing instruments. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=X-band%20transmitter" title="X-band transmitter">X-band transmitter</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA%20%28Field-Programmable%20Gate%20Array%29" title=" FPGA (Field-Programmable Gate Array)"> FPGA (Field-Programmable Gate Array)</a>, <a href="https://publications.waset.org/abstracts/search?q=CubeSat" title=" CubeSat"> CubeSat</a>, <a href="https://publications.waset.org/abstracts/search?q=micro%20satellite" title=" micro satellite"> micro satellite</a> </p> <a href="https://publications.waset.org/abstracts/72514/field-programmable-gate-array-based-baseband-signals-generator-of-x-band-transmitter-for-micro-satellitecubesat" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/72514.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">295</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1061</span> Implementation of Edge Detection Based on Autofluorescence Endoscopic Image of Field Programmable Gate Array</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hao%20Cheng">Hao Cheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Zhiwu%20Wang"> Zhiwu Wang</a>, <a href="https://publications.waset.org/abstracts/search?q=Guozheng%20Yan"> Guozheng Yan</a>, <a href="https://publications.waset.org/abstracts/search?q=Pingping%20Jiang"> Pingping Jiang</a>, <a href="https://publications.waset.org/abstracts/search?q=Shijia%20Qin"> Shijia Qin</a>, <a href="https://publications.waset.org/abstracts/search?q=Shuai%20Kuang"> Shuai Kuang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Autofluorescence Imaging (AFI) is a technology for detecting early carcinogenesis of the gastrointestinal tract in recent years. Compared with traditional white light endoscopy (WLE), this technology greatly improves the detection accuracy of early carcinogenesis, because the colors of normal tissues are different from cancerous tissues. Thus, edge detection can distinguish them in grayscale images. In this paper, based on the traditional Sobel edge detection method, optimization has been performed on this method which considers the environment of the gastrointestinal, including adaptive threshold and morphological processing. All of the processes are implemented on our self-designed system based on the image sensor OV6930 and Field Programmable Gate Array (FPGA), The system can capture the gastrointestinal image taken by the lens in real time and detect edges. The final experiments verified the feasibility of our system and the effectiveness and accuracy of the edge detection algorithm. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=AFI" title="AFI">AFI</a>, <a href="https://publications.waset.org/abstracts/search?q=edge%20detection" title=" edge detection"> edge detection</a>, <a href="https://publications.waset.org/abstracts/search?q=adaptive%20threshold" title=" adaptive threshold"> adaptive threshold</a>, <a href="https://publications.waset.org/abstracts/search?q=morphological%20processing" title=" morphological processing"> morphological processing</a>, <a href="https://publications.waset.org/abstracts/search?q=OV6930" title=" OV6930"> OV6930</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a> </p> <a href="https://publications.waset.org/abstracts/102685/implementation-of-edge-detection-based-on-autofluorescence-endoscopic-image-of-field-programmable-gate-array" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/102685.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">230</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1060</span> Novel Coprocessor for DNA Sequence Alignment in Resequencing Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Atef%20Ibrahim">Atef Ibrahim</a>, <a href="https://publications.waset.org/abstracts/search?q=Hamed%20Elsimary"> Hamed Elsimary</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdullah%20Aljumah"> Abdullah Aljumah</a>, <a href="https://publications.waset.org/abstracts/search?q=Fayez%20Gebali"> Fayez Gebali</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a novel semi-systolic array architecture for an optimized parallel sequence alignment algorithm. This architecture has the advantage that it can be modiﬁed to be reused for multiple pass processing in order to increase the number of processing elements that can be packed into a single FPGA and to increase the number of sequences that can be aligned in parallel in a single FPGA. This resolves the potential problem of many FPGA resources left unused for designs that have large values of short read length. When using the previously published conventional hardware design. FPGA implementation results show that, for large values of short read lengths (M>128), the proposed design has a slightly higher speed up and FPGA utilization over the the conventional one. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=bioinformatics" title="bioinformatics">bioinformatics</a>, <a href="https://publications.waset.org/abstracts/search?q=genome%20sequence%20alignment" title=" genome sequence alignment"> genome sequence alignment</a>, <a href="https://publications.waset.org/abstracts/search?q=re-sequencing%20applications" title=" re-sequencing applications"> re-sequencing applications</a>, <a href="https://publications.waset.org/abstracts/search?q=systolic%20array" title=" systolic array "> systolic array </a> </p> <a href="https://publications.waset.org/abstracts/23325/novel-coprocessor-for-dna-sequence-alignment-in-resequencing-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/23325.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">531</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1059</span> FPGA Implementation of Adaptive Clock Recovery for TDMoIP Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Semih%20Demir">Semih Demir</a>, <a href="https://publications.waset.org/abstracts/search?q=Anil%20Celebi"> Anil Celebi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Circuit switched networks widely used until the end of the 20<sup>th </sup>century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=clock%20recovery%20on%20TDMoIP" title="clock recovery on TDMoIP">clock recovery on TDMoIP</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=MATLAB%20reference%20model" title=" MATLAB reference model"> MATLAB reference model</a>, <a href="https://publications.waset.org/abstracts/search?q=clock%20synchronization" title=" clock synchronization"> clock synchronization</a> </p> <a href="https://publications.waset.org/abstracts/79237/fpga-implementation-of-adaptive-clock-recovery-for-tdmoip-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/79237.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">278</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1058</span> Exploration of Various Metrics for Partitioning of Cellular Automata Units for Efficient Reconfiguration of Field Programmable Gate Arrays (FPGAs)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Peter%20Tabatt">Peter Tabatt</a>, <a href="https://publications.waset.org/abstracts/search?q=Christian%20Siemers"> Christian Siemers</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA" title="reconfigurable FPGA">reconfigurable FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=cellular%20automata" title=" cellular automata"> cellular automata</a>, <a href="https://publications.waset.org/abstracts/search?q=partitioning" title=" partitioning"> partitioning</a>, <a href="https://publications.waset.org/abstracts/search?q=metrics" title=" metrics"> metrics</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20computing" title=" parallel computing"> parallel computing</a> </p> <a href="https://publications.waset.org/abstracts/56244/exploration-of-various-metrics-for-partitioning-of-cellular-automata-units-for-efficient-reconfiguration-of-field-programmable-gate-arrays-fpgas" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/56244.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">272</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1057</span> Portable and Parallel Accelerated Development Method for Field-Programmable Gate Array (FPGA)-Central Processing Unit (CPU)- Graphics Processing Unit (GPU) Heterogeneous Computing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nan%20Hu">Nan Hu</a>, <a href="https://publications.waset.org/abstracts/search?q=Chao%20Wang"> Chao Wang</a>, <a href="https://publications.waset.org/abstracts/search?q=Xi%20Li"> Xi Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Xuehai%20Zhou"> Xuehai Zhou</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The field-programmable gate array (FPGA) has been widely adopted in the high-performance computing domain. In recent years, the embedded system-on-a-chip (SoC) contains coarse granularity multi-core CPU (central processing unit) and mobile GPU (graphics processing unit) that can be used as general-purpose accelerators. The motivation is that algorithms of various parallel characteristics can be efficiently mapped to the heterogeneous architecture coupled with these three processors. The CPU and GPU offload partial computationally intensive tasks from the FPGA to reduce the resource consumption and lower the overall cost of the system. However, in present common scenarios, the applications always utilize only one type of accelerator because the development approach supporting the collaboration of the heterogeneous processors faces challenges. Therefore, a systematic approach takes advantage of write-once-run-anywhere portability, high execution performance of the modules mapped to various architectures and facilitates the exploration of design space. In this paper, A servant-execution-flow model is proposed for the abstraction of the cooperation of the heterogeneous processors, which supports task partition, communication and synchronization. At its first run, the intermediate language represented by the data flow diagram can generate the executable code of the target processor or can be converted into high-level programming languages. The instantiation parameters efficiently control the relationship between the modules and computational units, including two hierarchical processing units mapping and adjustment of data-level parallelism. An embedded system of a three-dimensional waveform oscilloscope is selected as a case study. The performance of algorithms such as contrast stretching, etc., are analyzed with implementations on various combinations of these processors. The experimental results show that the heterogeneous computing system with less than 35% resources achieves similar performance to the pure FPGA and approximate energy efficiency. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FPGA-CPU-GPU%20collaboration" title="FPGA-CPU-GPU collaboration">FPGA-CPU-GPU collaboration</a>, <a href="https://publications.waset.org/abstracts/search?q=design%20space%20exploration" title=" design space exploration"> design space exploration</a>, <a href="https://publications.waset.org/abstracts/search?q=heterogeneous%20computing" title=" heterogeneous computing"> heterogeneous computing</a>, <a href="https://publications.waset.org/abstracts/search?q=intermediate%20language" title=" intermediate language"> intermediate language</a>, <a href="https://publications.waset.org/abstracts/search?q=parameterized%20instantiation" title=" parameterized instantiation"> parameterized instantiation</a> </p> <a href="https://publications.waset.org/abstracts/150890/portable-and-parallel-accelerated-development-method-for-field-programmable-gate-array-fpga-central-processing-unit-cpu-graphics-processing-unit-gpu-heterogeneous-computing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/150890.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">118</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1056</span> Field-Programmable Gate Arrays Based High-Efficiency Oriented Fast and Rotated Binary Robust Independent Elementary Feature Extraction Method Using Feature Zone Strategy</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Huang%20Bai-Cheng">Huang Bai-Cheng</a> </p> <p class="card-text"><strong>Abstract:</strong></p> When deploying the Oriented Fast and Rotated Binary Robust Independent Elementary Feature (BRIEF) (ORB) extraction algorithm on field-programmable gate arrays (FPGA), the access of global storage for 31×31 pixel patches of the features has become the bottleneck of the system efficiency. Therefore, a feature zone strategy has been proposed. Zones are searched as features are detected. Pixels around the feature zones are extracted from global memory and distributed into patches corresponding to feature coordinates. The proposed FPGA structure is targeted on a Xilinx FPGA development board of Zynq UltraScale+ series, and multiple datasets are tested. Compared with the streaming pixel patch extraction method, the proposed architecture obtains at least two times acceleration consuming extra 3.82% Flip-Flops (FFs) and 7.78% Look-Up Tables (LUTs). Compared with the non-streaming one, the proposed architecture saves 22.3% LUT and 1.82% FF, causing a latency of only 0.2ms and a drop in frame rate for 1. Compared with the related works, the proposed strategy and hardware architecture have the superiority of keeping a balance between FPGA resources and performance. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=feature%20extraction" title="feature extraction">feature extraction</a>, <a href="https://publications.waset.org/abstracts/search?q=real-time" title=" real-time"> real-time</a>, <a href="https://publications.waset.org/abstracts/search?q=ORB" title=" ORB"> ORB</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA%20implementation" title=" FPGA implementation"> FPGA implementation</a> </p> <a href="https://publications.waset.org/abstracts/158130/field-programmable-gate-arrays-based-high-efficiency-oriented-fast-and-rotated-binary-robust-independent-elementary-feature-extraction-method-using-feature-zone-strategy" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/158130.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">122</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1055</span> FSO Performance under High Solar Irradiation: Case Study Qatar</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Syed%20Jawad%20Hussain">Syed Jawad Hussain</a>, <a href="https://publications.waset.org/abstracts/search?q=Abir%20Touati"> Abir Touati</a>, <a href="https://publications.waset.org/abstracts/search?q=Farid%20Touati"> Farid Touati</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Free-Space Optics (FSO) is a wireless technology that enables the optical transmission of data though the air. FSO is emerging as a promising alternative or complementary technology to fiber optic and wireless radio-frequency (RF) links due to its high-bandwidth, robustness to EMI, and operation in unregulated spectrum. These systems are envisioned to be an essential part of future generation heterogeneous communication networks. Despite the vibrant advantages of FSO technology and the variety of its applications, its widespread adoption has been hampered by rather disappointing link reliability for long-range links due to atmospheric turbulence-induced fading and sensitivity to detrimental climate conditions. Qatar, with modest cloud coverage, high concentrations of airborne dust and high relative humidity particularly lies in virtually rainless sunny belt with a typical daily average solar radiation exceeding 6 kWh/m2 and 80-90% clear skies throughout the year. The specific objective of this work is to study for the first time in Qatar the effect of solar irradiation on the deliverability of the FSO Link. In order to analyze the transport media, we have ported Embedded Linux kernel on Field Programmable Gate Array (FPGA) and designed a network sniffer application that can run into FPGA. We installed new FSO terminals and configure and align them successively. In the reporting period, we carry out measurement and relate them to weather conditions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=free%20space%20optics" title="free space optics">free space optics</a>, <a href="https://publications.waset.org/abstracts/search?q=solar%20irradiation" title=" solar irradiation"> solar irradiation</a>, <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title=" field programmable gate array"> field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=FSO%20outage" title=" FSO outage"> FSO outage</a> </p> <a href="https://publications.waset.org/abstracts/39197/fso-performance-under-high-solar-irradiation-case-study-qatar" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/39197.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">360</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1054</span> Area-Efficient FPGA Implementation of an FFT Processor by Reusing Butterfly Units</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Atin%20Mukherjee">Atin Mukherjee</a>, <a href="https://publications.waset.org/abstracts/search?q=Amitabha%20Sinha"> Amitabha Sinha</a>, <a href="https://publications.waset.org/abstracts/search?q=Debesh%20Choudhury"> Debesh Choudhury</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Fast Fourier transform (FFT) of large-number of samples requires larger hardware resources of field programmable gate arrays and it asks for more area as well as power. In this paper, an area efficient architecture of FFT processor is proposed, that reuses the butterfly units more than once. The FFT processor is emulated and the results are validated on Virtex-6 FPGA. The proposed architecture outperforms the conventional architecture of a N-point FFT processor in terms of area which is reduced by a factor of log_N(2) with the negligible increase of processing time. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FFT" title="FFT">FFT</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=resource%20optimization" title=" resource optimization"> resource optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=butterfly%20units" title=" butterfly units"> butterfly units</a> </p> <a href="https://publications.waset.org/abstracts/17094/area-efficient-fpga-implementation-of-an-fft-processor-by-reusing-butterfly-units" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/17094.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">523</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1053</span> A High Time Resolution Digital Pulse Width Modulator Based on Field Programmable Gate Array’s Phase Locked Loop Megafunction</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jun%20Wang">Jun Wang</a>, <a href="https://publications.waset.org/abstracts/search?q=Tingcun%20Wei"> Tingcun Wei</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DPWM" title="DPWM">DPWM</a>, <a href="https://publications.waset.org/abstracts/search?q=digitally-controlled%20DC-DC%20switching%20converter" title=" digitally-controlled DC-DC switching converter"> digitally-controlled DC-DC switching converter</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=PLL%20megafunction" title=" PLL megafunction"> PLL megafunction</a>, <a href="https://publications.waset.org/abstracts/search?q=time%20resolution" title=" time resolution"> time resolution</a> </p> <a href="https://publications.waset.org/abstracts/50826/a-high-time-resolution-digital-pulse-width-modulator-based-on-field-programmable-gate-arrays-phase-locked-loop-megafunction" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/50826.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">480</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1052</span> Computational Analysis on Thermal Performance of Chip Package in Electro-Optical Device</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Long%20Kim%20Vu">Long Kim Vu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CFD" title="CFD">CFD</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=heat%20transfer" title=" heat transfer"> heat transfer</a>, <a href="https://publications.waset.org/abstracts/search?q=thermal%20analysis" title=" thermal analysis"> thermal analysis</a> </p> <a href="https://publications.waset.org/abstracts/137585/computational-analysis-on-thermal-performance-of-chip-package-in-electro-optical-device" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/137585.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">184</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1051</span> FPGA Based Vector Control of PM Motor Using Sliding Mode Observer</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hanan%20Mikhael%20Dawood">Hanan Mikhael Dawood</a>, <a href="https://publications.waset.org/abstracts/search?q=Afaneen%20Anwer%20Abood%20Al-Khazraji"> Afaneen Anwer Abood Al-Khazraji </a> </p> <p class="card-text"><strong>Abstract:</strong></p> The paper presents an investigation of field oriented control strategy of Permanent Magnet Synchronous Motor (PMSM) based on hardware in the loop simulation (HIL) over a wide speed range. A sensorless rotor position estimation using sliding mode observer for permanent magnet synchronous motor is illustrated considering the effects of magnetic saturation between the d and q axes. The cross saturation between d and q axes has been calculated by finite-element analysis. Therefore, the inductance measurement regards the saturation and cross saturation which are used to obtain the suitable id-characteristics in base and flux weakening regions. Real time matrix multiplication in Field Programmable Gate Array (FPGA) using floating point number system is used utilizing Quartus-II environment to develop FPGA designs and then download these designs files into development kit. dSPACE DS1103 is utilized for Pulse Width Modulation (PWM) switching and the controller. The hardware in the loop results conducted to that from the Matlab simulation. Various dynamic conditions have been investigated. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=magnetic%20saturation" title="magnetic saturation">magnetic saturation</a>, <a href="https://publications.waset.org/abstracts/search?q=rotor%20position%20estimation" title=" rotor position estimation"> rotor position estimation</a>, <a href="https://publications.waset.org/abstracts/search?q=sliding%20mode%20observer" title=" sliding mode observer"> sliding mode observer</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20in%20the%20loop%20%28HIL%29" title=" hardware in the loop (HIL)"> hardware in the loop (HIL)</a> </p> <a href="https://publications.waset.org/abstracts/18977/fpga-based-vector-control-of-pm-motor-using-sliding-mode-observer" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/18977.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">529</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1050</span> Classification of Myoelectric Signals Using Multilayer Perceptron Neural Network with Back-Propagation Algorithm in a Wireless Surface Myoelectric Prosthesis of the Upper-Limb</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kevin%20D.%20Manalo">Kevin D. Manalo</a>, <a href="https://publications.waset.org/abstracts/search?q=Jumelyn%20L.%20Torres"> Jumelyn L. Torres</a>, <a href="https://publications.waset.org/abstracts/search?q=Noel%20B.%20Linsangan"> Noel B. Linsangan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper focuses on a wireless myoelectric prosthesis of the upper-limb that uses a Multilayer Perceptron Neural network with back propagation. The algorithm is widely used in pattern recognition. The network can be used to train signals and be able to use it in performing a function on their own based on sample inputs. The paper makes use of the Neural Network in classifying the electromyography signal that is produced by the muscle in the amputee’s skin surface. The gathered data will be passed on through the Classification Stage wirelessly through Zigbee Technology. The signal will be classified and trained to be used in performing the arm positions in the prosthesis. Through programming using Verilog and using a Field Programmable Gate Array (FPGA) with Zigbee, the EMG signals will be acquired and will be used for classification. The classified signal is used to produce the corresponding Hand Movements (Open, Pick, Hold, and Grip) through the Zigbee controller. The data will then be processed through the MLP Neural Network using MATLAB which then be used for the surface myoelectric prosthesis. Z-test will be used to display the output acquired from using the neural network. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title="field programmable gate array">field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=multilayer%20perceptron%20neural%20network" title=" multilayer perceptron neural network"> multilayer perceptron neural network</a>, <a href="https://publications.waset.org/abstracts/search?q=verilog" title=" verilog"> verilog</a>, <a href="https://publications.waset.org/abstracts/search?q=zigbee" title=" zigbee"> zigbee</a> </p> <a href="https://publications.waset.org/abstracts/19846/classification-of-myoelectric-signals-using-multilayer-perceptron-neural-network-with-back-propagation-algorithm-in-a-wireless-surface-myoelectric-prosthesis-of-the-upper-limb" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/19846.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">389</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1049</span> FPGA Based IIR Filter Design Using MAC Algorithm</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rajesh%20Mehra">Rajesh Mehra</a>, <a href="https://publications.waset.org/abstracts/search?q=Bharti%20Thakur"> Bharti Thakur</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with Matlab and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Butterworth%20filter" title="Butterworth filter">Butterworth filter</a>, <a href="https://publications.waset.org/abstracts/search?q=DSP" title=" DSP"> DSP</a>, <a href="https://publications.waset.org/abstracts/search?q=IIR" title=" IIR"> IIR</a>, <a href="https://publications.waset.org/abstracts/search?q=MAC" title=" MAC"> MAC</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a> </p> <a href="https://publications.waset.org/abstracts/41409/fpga-based-iir-filter-design-using-mac-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/41409.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">388</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1048</span> Wireless FPGA-Based Motion Controller Design by Implementing 3-Axis Linear Trajectory</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kiana%20Zeighami">Kiana Zeighami</a>, <a href="https://publications.waset.org/abstracts/search?q=Morteza%20Ozlati%20Moghadam"> Morteza Ozlati Moghadam</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Designing a high accuracy and high precision motion controller is one of the important issues in today’s industry. There are effective solutions available in the industry but the real-time performance, smoothness and accuracy of the movement can be further improved. This paper discusses a complete solution to carry out the movement of three stepper motors in three dimensions. The objective is to provide a method to design a fully integrated System-on-Chip (SOC)-based motion controller to reduce the cost and complexity of production by incorporating Field Programmable Gate Array (FPGA) into the design. In the proposed method the FPGA receives its commands from a host computer via wireless internet communication and calculates the motion trajectory for three axes. A profile generator module is designed to realize the interpolation algorithm by translating the position data to the real-time pulses. This paper discusses an approach to implement the linear interpolation algorithm, since it is one of the fundamentals of robots’ movements and it is highly applicable in motion control industries. Along with full profile trajectory, the triangular drive is implemented to eliminate the existence of error at small distances. To integrate the parallelism and real-time performance of FPGA with the power of Central Processing Unit (CPU) in executing complex and sequential algorithms, the NIOS II soft-core processor was added into the design. This paper presents different operating modes such as absolute, relative positioning, reset and velocity modes to fulfill the user requirements. The proposed approach was evaluated by designing a custom-made FPGA board along with a mechanical structure. As a result, a precise and smooth movement of stepper motors was observed which proved the effectiveness of this approach. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=3-axis%20linear%20interpolation" title="3-axis linear interpolation">3-axis linear interpolation</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=motion%20controller" title=" motion controller"> motion controller</a>, <a href="https://publications.waset.org/abstracts/search?q=micro-stepping" title=" micro-stepping"> micro-stepping</a> </p> <a href="https://publications.waset.org/abstracts/54237/wireless-fpga-based-motion-controller-design-by-implementing-3-axis-linear-trajectory" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/54237.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">208</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1047</span> Reconfigurable Efficient IIR Filter Design Using MAC Algorithm </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rajesh%20Mehra">Rajesh Mehra</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with MATLAB and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=butterworth" title="butterworth">butterworth</a>, <a href="https://publications.waset.org/abstracts/search?q=DSP" title=" DSP"> DSP</a>, <a href="https://publications.waset.org/abstracts/search?q=IIR" title=" IIR"> IIR</a>, <a href="https://publications.waset.org/abstracts/search?q=MAC" title=" MAC"> MAC</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA "> FPGA </a> </p> <a href="https://publications.waset.org/abstracts/13274/reconfigurable-efficient-iir-filter-design-using-mac-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/13274.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">357</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1046</span> Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tomasz%20Grzes">Tomasz Grzes</a>, <a href="https://publications.waset.org/abstracts/search?q=Maciej%20Kopczynski"> Maciej Kopczynski</a>, <a href="https://publications.waset.org/abstracts/search?q=Jaroslaw%20Stepaniuk"> Jaroslaw Stepaniuk</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The rough sets theory developed by Prof. Z. Pawlak is one of the tools that can be used in the intelligent systems for data analysis and processing. Banking, medicine, image recognition and security are among the possible fields of utilization. In all these fields, the amount of the collected data is increasing quickly, but with the increase of the data, the computation speed becomes the critical factor. Data reduction is one of the solutions to this problem. Removing the redundancy in the rough sets can be achieved with the reduct. A lot of algorithms of generating the reduct were developed, but most of them are only software implementations, therefore have many limitations. Microprocessor uses the fixed word length, consumes a lot of time for either fetching as well as processing of the instruction and data; consequently, the software based implementations are relatively slow. Hardware systems don’t have these limitations and can process the data faster than a software. Reduct is the subset of the decision attributes that provides the discernibility of the objects. For the given decision table there can be more than one reduct. Core is the set of all indispensable condition attributes. None of its elements can be removed without affecting the classification power of all condition attributes. Moreover, every reduct consists of all the attributes from the core. In this paper, the hardware implementation of the two-stage greedy algorithm to find the one reduct is presented. The decision table is used as an input. Output of the algorithm is the superreduct which is the reduct with some additional removable attributes. First stage of the algorithm is calculating the core using the discernibility matrix. Second stage is generating the superreduct by enriching the core with the most common attributes, i.e., attributes that are more frequent in the decision table. Described above algorithm has two disadvantages: i) generating the superreduct instead of reduct, ii) additional first stage may be unnecessary if the core is empty. But for the systems focused on the fast computation of the reduct the first disadvantage is not the key problem. The core calculation can be achieved with a combinational logic block, and thus add respectively little time to the whole process. Algorithm presented in this paper was implemented in Field Programmable Gate Array (FPGA) as a digital device consisting of blocks that process the data in a single step. Calculating the core is done by the comparators connected to the block called 'singleton detector', which detects if the input word contains only single 'one'. Calculating the number of occurrences of the attribute is performed in the combinational block made up of the cascade of the adders. The superreduct generation process is iterative and thus needs the sequential circuit for controlling the calculations. For the research purpose, the algorithm was also implemented in C language and run on a PC. The times of execution of the reduct calculation in a hardware and software were considered. Results show increase in the speed of data processing. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=data%20reduction" title="data reduction">data reduction</a>, <a href="https://publications.waset.org/abstracts/search?q=digital%20systems%20design" title=" digital systems design"> digital systems design</a>, <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array%20%28FPGA%29" title=" field programmable gate array (FPGA)"> field programmable gate array (FPGA)</a>, <a href="https://publications.waset.org/abstracts/search?q=reduct" title=" reduct"> reduct</a>, <a href="https://publications.waset.org/abstracts/search?q=rough%20set" title=" rough set"> rough set</a> </p> <a href="https://publications.waset.org/abstracts/81856/hardware-implementation-on-field-programmable-gate-array-of-two-stage-algorithm-for-rough-set-reduct-generation" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/81856.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">219</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1045</span> Embedded System of Signal Processing on FPGA: Underwater Application Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelkader%20Elhanaoui">Abdelkader Elhanaoui</a>, <a href="https://publications.waset.org/abstracts/search?q=Mhamed%20Hadji"> Mhamed Hadji</a>, <a href="https://publications.waset.org/abstracts/search?q=Rachid%20Skouri"> Rachid Skouri</a>, <a href="https://publications.waset.org/abstracts/search?q=Said%20Agounad"> Said Agounad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The purpose of this paper is to study the phenomenon of acoustic scattering by using a new method. The signal processing (Fast Fourier Transform FFT Inverse Fast Fourier Transform iFFT and BESSEL functions) is widely applied to obtain information with high precision accuracy. Signal processing has a wider implementation in general-purpose pro-cessors. Our interest was focused on the use of FPGAs (Field-Programmable Gate Ar-rays) in order to minimize the computational complexity in single processor architecture, then be accelerated on FPGA and meet real-time and energy efficiency requirements. Gen-eral-purpose processors are not efficient for signal processing. We implemented the acous-tic backscattered signal processing model on the Altera DE-SOC board and compared it to Odroid xu4. By comparison, the computing latency of Odroid xu4 and FPGA is 60 sec-onds and 3 seconds, respectively. The detailed SoC FPGA-based system has shown that acoustic spectra are performed up to 20 times faster than the Odroid xu4 implementation. FPGA-based system of processing algorithms is realized with an absolute error of about 10⁻³. This study underlines the increasing importance of embedded systems in underwater acoustics, especially in non-destructive testing. It is possible to obtain information related to the detection and characterization of submerged cells. So we have achieved good exper-imental results in real-time and energy efficiency. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DE1%20FPGA" title="DE1 FPGA">DE1 FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=acoustic%20scattering" title=" acoustic scattering"> acoustic scattering</a>, <a href="https://publications.waset.org/abstracts/search?q=form%20function" title=" form function"> form function</a>, <a href="https://publications.waset.org/abstracts/search?q=signal%20processing" title=" signal processing"> signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=non-destructive%20testing" title=" non-destructive testing"> non-destructive testing</a> </p> <a href="https://publications.waset.org/abstracts/162313/embedded-system-of-signal-processing-on-fpga-underwater-application-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/162313.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">79</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1044</span> Implementation of Iterative Algorithm for Earthquake Location</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hussain%20K.%20Chaiel">Hussain K. Chaiel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The development in the field of the digital signal processing (DSP) and the microelectronics technology reduces the complexity of the iterative algorithms that need large number of arithmetic operations. Virtex-Field Programmable Gate Arrays (FPGAs) are programmable silicon foundations which offer an important solution for addressing the needs of high performance DSP designer. In this work, Virtex-7 FPGA technology is used to implement an iterative algorithm to estimate the earthquake location. Simulation results show that an implementation based on block RAMB36E1 and DSP48E1 slices of Virtex-7 type reduces the number of cycles of the clock frequency. This enables the algorithm to be used for earthquake prediction. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DSP" title="DSP">DSP</a>, <a href="https://publications.waset.org/abstracts/search?q=earthquake" title=" earthquake"> earthquake</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=iterative%20algorithm" title=" iterative algorithm "> iterative algorithm </a> </p> <a href="https://publications.waset.org/abstracts/28897/implementation-of-iterative-algorithm-for-earthquake-location" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28897.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">389</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1043</span> Lightweight Hardware Firewall for Embedded System Based on Bus Transactions</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ziyuan%20Wu">Ziyuan Wu</a>, <a href="https://publications.waset.org/abstracts/search?q=Yulong%20Jia"> Yulong Jia</a>, <a href="https://publications.waset.org/abstracts/search?q=Xiang%20Zhang"> Xiang Zhang</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=IoT" title="IoT">IoT</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=SoC" title=" SoC"> SoC</a>, <a href="https://publications.waset.org/abstracts/search?q=bus%20architecture" title=" bus architecture"> bus architecture</a>, <a href="https://publications.waset.org/abstracts/search?q=lightweight%20hardware%20firewall" title=" lightweight hardware firewall"> lightweight hardware firewall</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a> </p> <a href="https://publications.waset.org/abstracts/179081/lightweight-hardware-firewall-for-embedded-system-based-on-bus-transactions" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/179081.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">61</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=field-programmable%20gate%20array%20%28FPGA%29&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=field-programmable%20gate%20array%20%28FPGA%29&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=field-programmable%20gate%20array%20%28FPGA%29&page=4">4</a></li> <li class="page-item"><a class="page-link" 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