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5 nm process - Wikipedia

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vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#4_nm_process_nodes"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>4 nm process nodes</span> </div> </a> <ul id="toc-4_nm_process_nodes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Beyond_4_nm" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Beyond_4_nm"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Beyond 4 nm</span> </div> </a> <ul id="toc-Beyond_4_nm-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" 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cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">5 nm process</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 14 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-14" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">14 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B9%D8%A7%D9%84%D8%AC%D8%A7%D8%AA_5_%D9%86%D8%A7%D9%86%D9%88" title="معالجات 5 نانو – Arabic" lang="ar" hreflang="ar" data-title="معالجات 5 نانو" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-zh-min-nan mw-list-item"><a href="https://zh-min-nan.wikipedia.org/wiki/5_n%C4%81i-b%C3%AD_ch%C3%A8-t%C3%AAng" title="5 nāi-bí chè-têng – Minnan" lang="nan" hreflang="nan" data-title="5 nāi-bí chè-têng" data-language-autonym="閩南語 / Bân-lâm-gú" data-language-local-name="Minnan" class="interlanguage-link-target"><span>閩南語 / Bân-lâm-gú</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/5_nan%C3%B2metres" title="5 nanòmetres – Catalan" lang="ca" hreflang="ca" data-title="5 nanòmetres" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/5_nan%C3%B3metros" title="5 nanómetros – Spanish" lang="es" hreflang="es" data-title="5 nanómetros" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%81%D8%B1%D8%A7%DB%8C%D9%86%D8%AF_%DB%B5_%D9%86%D8%A7%D9%86%D9%88%D9%85%D8%AA%D8%B1" title="فرایند ۵ نانومتر – Persian" lang="fa" hreflang="fa" data-title="فرایند ۵ نانومتر" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/5_nm" title="5 nm – French" lang="fr" hreflang="fr" data-title="5 nm" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/5_nm_%EA%B3%B5%EC%A0%95" title="5 nm 공정 – Korean" lang="ko" hreflang="ko" data-title="5 nm 공정" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Proses_5_nm" title="Proses 5 nm – Indonesian" lang="id" hreflang="id" data-title="Proses 5 nm" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/5_nm" title="5 nm – Italian" lang="it" hreflang="it" data-title="5 nm" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/5%E3%83%8A%E3%83%8E%E3%83%A1%E3%83%BC%E3%83%88%E3%83%AB" title="5ナノメートル – Japanese" lang="ja" hreflang="ja" data-title="5ナノメートル" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/5_nan%C3%B4metros" title="5 nanômetros – Portuguese" lang="pt" hreflang="pt" data-title="5 nanômetros" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/5_nm" title="5 nm – Russian" lang="ru" hreflang="ru" data-title="5 nm" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/5%E7%B4%8D%E7%B1%B3%E8%A3%BD%E7%A8%8B" title="5納米製程 – Cantonese" lang="yue" hreflang="yue" data-title="5納米製程" data-language-autonym="粵語" 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=5nm&amp;redirect=no" class="mw-redirect" title="5nm">5nm</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Semiconductor manufacturing processes</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul 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class="sidebar-title" style="font-size: 110%"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor<br />device<br />fabrication</a></th></tr><tr><td class="sidebar-image"><span typeof="mw:File"><a href="/wiki/File:4-fach-NAND-C10.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d5/4-fach-NAND-C10.JPG/100px-4-fach-NAND-C10.JPG" decoding="async" width="100" height="125" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d5/4-fach-NAND-C10.JPG/150px-4-fach-NAND-C10.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d5/4-fach-NAND-C10.JPG/200px-4-fach-NAND-C10.JPG 2x" data-file-width="967" data-file-height="1206" /></a></span></td></tr><tr><td class="sidebar-content plainlist" style="text-align:left;;text-align:center;"> <a href="/wiki/MOSFET#Scaling" title="MOSFET">MOSFET scaling</a><br />(<a href="/wiki/List_of_semiconductor_scale_examples" title="List of semiconductor scale examples">process nodes</a>)</td> </tr><tr><td class="sidebar-content plainlist" style="text-align:left;"> <div style="padding-left:14px;"> <ul><li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/20_%CE%BCm_process" class="mw-redirect" title="20 μm process">20&#160;μm</a>&#160;– 1968</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/10_%CE%BCm_process" class="mw-redirect" title="10 μm process">10&#160;μm</a>&#160;– 1971</li> <li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/6_%CE%BCm_process" title="6 μm process">6&#160;μm</a>&#160;– 1974</li> <li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/3_%CE%BCm_process" title="3 μm process">3&#160;μm</a>&#160;– 1977</li> <li><span style="padding-left:0.05em;">&#160;</span><a href="/wiki/1.5_%CE%BCm_process" title="1.5 μm process">1.5&#160;μm</a>&#160;– 1981</li> <li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/1_%CE%BCm_process" title="1 μm process">1&#160;μm</a>&#160;– 1984</li> <li><a href="/wiki/800_nm_process" title="800 nm process">800&#160;nm</a>&#160;– 1987</li> <li><a href="/wiki/600_nm_process" title="600 nm process">600&#160;nm</a>&#160;– 1990</li> <li><a href="/wiki/350_nm_process" title="350 nm process">350&#160;nm</a>&#160;– 1993</li> <li><a href="/wiki/250_nm_process" title="250 nm process">250&#160;nm</a>&#160;– 1996</li> <li><a href="/wiki/180_nm_process" title="180 nm process">180&#160;nm</a>&#160;– 1999</li> <li><a href="/wiki/130_nm_process" title="130 nm process">130&#160;nm</a>&#160;– 2001</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/90_nm_process" title="90 nm process">90&#160;nm</a>&#160;– 2003</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/65_nm_process" title="65 nm process">65&#160;nm</a>&#160;– 2005</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/45_nm_process" title="45 nm process">45&#160;nm</a>&#160;– 2007</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/32_nm_process" title="32 nm process">32&#160;nm</a>&#160;– 2009</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/28_nm_process" title="28 nm process">28&#160;nm</a>&#160;– 2010</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/22_nm_process" title="22 nm process">22&#160;nm</a>&#160;– 2012</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/14_nm_process" title="14 nm process">14&#160;nm</a>&#160;– 2014</li> <li><span style="visibility:hidden;color:transparent;">0</span><a href="/wiki/10_nm_process" title="10 nm process">10&#160;nm</a>&#160;– 2016</li> <li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/7_nm_process" title="7 nm process">7&#160;nm</a>&#160;– 2018</li> <li><span style="visibility:hidden;color:transparent;">00</span><a class="mw-selflink selflink">5&#160;nm</a>&#160;– 2020</li> <li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/3_nm_process" title="3 nm process">3&#160;nm</a>&#160;– 2022</li></ul> </div></td> </tr><tr><td class="sidebar-content plainlist" style="text-align:left;"> <div style="padding-left:14px;">Future <ul><li><span style="visibility:hidden;color:transparent;">00</span><a href="/wiki/2_nm_process" title="2 nm process">2&#160;nm</a>&#160;~ 2025</li></ul> </div></td> </tr><tr><td class="sidebar-content plainlist" style="text-align:left;"> <div style="padding-right:5px; padding-left:5px;"><hr /><div class="paragraphbreak" style="margin-top:0.5em"></div> <ul><li><a href="/wiki/Die_shrink#Half-shrink" title="Die shrink">Half-nodes</a></li> <li><a href="/wiki/Transistor_count#Transistor_density" title="Transistor count">Density</a></li> <li><a href="/wiki/CMOS" title="CMOS">CMOS</a></li> <li><a href="/wiki/Semiconductor_device" title="Semiconductor device">Device</a> (<a href="/wiki/Multigate_device" title="Multigate device">multi-gate</a>)</li> <li><a href="/wiki/Moore%27s_law" title="Moore&#39;s law">Moore's law</a></li> <li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Semiconductor" title="Semiconductor">Semiconductor</a></li> <li><a href="/wiki/Semiconductor_industry" title="Semiconductor industry">Industry</a></li> <li><a href="/wiki/Nanoelectronics" title="Nanoelectronics">Nanoelectronics</a></li></ul> </div></td> </tr><tr><td class="sidebar-below" style="padding-right: 0.5em; font-weight: normal; text-align: right; font-size: 115%"> <div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Semiconductor_manufacturing_processes" title="Template:Semiconductor manufacturing processes"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Semiconductor_manufacturing_processes" title="Template talk:Semiconductor manufacturing processes"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Semiconductor_manufacturing_processes" title="Special:EditPage/Template:Semiconductor manufacturing processes"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <p>In <a href="/wiki/Semiconductor_manufacturing" class="mw-redirect" title="Semiconductor manufacturing">semiconductor manufacturing</a>, the <a href="/wiki/International_Roadmap_for_Devices_and_Systems" title="International Roadmap for Devices and Systems">International Roadmap for Devices and Systems</a> defines the <b>"5&#160;nm" process</b> as the <a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> <a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">technology node</a> following the <a href="/wiki/7_nm_process" title="7 nm process">"7 nm"</a> node. In 2020, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> and <a href="/wiki/TSMC" title="TSMC">TSMC</a> entered volume production of "5&#160;nm" chips, manufactured for companies including <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a>, <a href="/wiki/Huawei" title="Huawei">Huawei</a>, <a href="/wiki/Mediatek" class="mw-redirect" title="Mediatek">Mediatek</a>, <a href="/wiki/Qualcomm" title="Qualcomm">Qualcomm</a> and <a href="/wiki/Marvell_Technology_Group" class="mw-redirect" title="Marvell Technology Group">Marvell</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">&#91;</span>1<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">&#91;</span>2<span class="cite-bracket">&#93;</span></a></sup> </p><p>The term "5 nm" does not indicate that any physical feature (such as gate length, metal pitch or gate pitch) of the transistors is five <a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nanometers</a> in size. Historically, the number used in the name of a technology node represented the gate length, but it started deviating from the actual length to smaller numbers (by <a href="/wiki/Intel" title="Intel">Intel</a>) around 2011.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">&#91;</span>3<span class="cite-bracket">&#93;</span></a></sup> According to the projections contained in the 2021 update of the <a href="/wiki/International_Roadmap_for_Devices_and_Systems" title="International Roadmap for Devices and Systems">International Roadmap for Devices and Systems</a> published by IEEE Standards Association Industry Connection, the 5 nm node is expected to have a gate length of 18nm, a contacted gate pitch of 51nm, and a tightest metal pitch of 30nm.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">&#91;</span>4<span class="cite-bracket">&#93;</span></a></sup> In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous <a href="/wiki/7_nm_process" title="7 nm process">7 nm process</a>.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">&#91;</span>5<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">&#91;</span>6<span class="cite-bracket">&#93;</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Background">Background</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=2" title="Edit section: Background"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Quantum_tunnelling" title="Quantum tunnelling">Quantum tunnelling</a> effects through the gate oxide layer on "7&#160;nm" and "5&#160;nm" <a href="/wiki/Transistor" title="Transistor">transistors</a> became increasingly difficult to manage using existing semiconductor processes.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">&#91;</span>7<span class="cite-bracket">&#93;</span></a></sup> Single-transistor devices below 7&#160;nm were first demonstrated by researchers in the early 2000s. In 2002, an <a href="/wiki/IBM" title="IBM">IBM</a> research team including Bruce Doris, Omer Dokumaci, <a href="/wiki/Meikei_Ieong" title="Meikei Ieong">Meikei Ieong</a> and Anda Mocuta fabricated a <a href="/wiki/7_nm_process#Technology_demos" title="7 nm process">6-nanometre</a> <a href="/wiki/Silicon-on-insulator" class="mw-redirect" title="Silicon-on-insulator">silicon-on-insulator</a> (SOI) MOSFET.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">&#91;</span>8<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">&#91;</span>9<span class="cite-bracket">&#93;</span></a></sup> </p><p>In 2003, a Japanese research team at <a href="/wiki/NEC" title="NEC">NEC</a>, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5&#160;nm MOSFET.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">&#91;</span>10<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">&#91;</span>11<span class="cite-bracket">&#93;</span></a></sup> </p><p>In 2015, <a href="/wiki/IMEC" title="IMEC">IMEC</a> and <a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a> fabricated 5&#160;nm test chips. The fabricated test chips were not fully functional devices, but rather are to evaluate patterning of <a href="/wiki/Interconnects_(integrated_circuits)" class="mw-redirect" title="Interconnects (integrated circuits)">interconnect</a> layers.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">&#91;</span>12<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">&#91;</span>13<span class="cite-bracket">&#93;</span></a></sup> </p><p>In 2015, <a href="/wiki/Intel" title="Intel">Intel</a> described a lateral nanowire (or gate-all-around) FET concept for the "5&#160;nm" node.<sup id="cite_ref-semiengineering_2016Jan_14-0" class="reference"><a href="#cite_note-semiengineering_2016Jan-14"><span class="cite-bracket">&#91;</span>14<span class="cite-bracket">&#93;</span></a></sup> </p><p>In 2017, <a href="/wiki/IBM" title="IBM">IBM</a> revealed that it had created "5&#160;nm" <a href="/wiki/Silicon" title="Silicon">silicon</a> chips,<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">&#91;</span>15<span class="cite-bracket">&#93;</span></a></sup> using silicon nanosheets in a <i><a href="/wiki/Gate-all-around" class="mw-redirect" title="Gate-all-around">gate-all-around</a></i> configuration (GAAFET), a break from the usual <a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50&#160;mm<sup>2</sup> and had 600 million transistors per mm<sup>2</sup>, for a total of 30 billion transistors (1667&#160;nm<sup>2</sup> per transistor or 41&#160;nm actual transistor spacing).<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">&#91;</span>16<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">&#91;</span>17<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Commercialization">Commercialization</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=3" title="Edit section: Commercialization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In April 2019, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> announced they had been offering their "5&#160;nm" process (5LPE) tools to their customers since 2018 Q4.<sup id="cite_ref-anandtech-samsung_18-0" class="reference"><a href="#cite_note-anandtech-samsung-18"><span class="cite-bracket">&#91;</span>18<span class="cite-bracket">&#93;</span></a></sup> In April 2019, TSMC announced that their "5&#160;nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use <a href="/wiki/Extreme_ultraviolet_lithography" title="Extreme ultraviolet lithography">EUVL</a> on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.<sup id="cite_ref-tsmc_19-0" class="reference"><a href="#cite_note-tsmc-19"><span class="cite-bracket">&#91;</span>19<span class="cite-bracket">&#93;</span></a></sup> For the expected 28&#160;nm minimum metal pitch, <a href="/wiki/Extreme_ultraviolet_lithography#Use_with_multiple-patterning" title="Extreme ultraviolet lithography">SALELE</a> is the proposed best patterning method.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">&#91;</span>20<span class="cite-bracket">&#93;</span></a></sup> </p><p>For their "5&#160;nm" process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">&#91;</span>21<span class="cite-bracket">&#93;</span></a></sup> </p><p>In October 2019, TSMC reportedly started sampling 5&#160;nm <a href="/wiki/Apple_A14" title="Apple A14">A14 processors for Apple</a>.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">&#91;</span>22<span class="cite-bracket">&#93;</span></a></sup> At the 2020 IEEE IEDM conference, TSMC reported their 5&#160;nm process had 1.84x higher density than their 7nm process.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">&#91;</span>23<span class="cite-bracket">&#93;</span></a></sup> At IEDM 2019, TSMC revealed two versions of 5&#160;nm, a DUV version with a 5.5-track cell, and an (official) EUV version with a 6-track cell.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">&#91;</span>24<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">&#91;</span>25<span class="cite-bracket">&#93;</span></a></sup> </p><p>In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their "5&#160;nm" test chips with a die size of 17.92&#160;mm<sup>2</sup>.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">&#91;</span>26<span class="cite-bracket">&#93;</span></a></sup> In mid 2020 TSMC claimed its (N5) "5&#160;nm" process offered 1.8x the density of its "7&#160;nm" N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">&#91;</span>27<span class="cite-bracket">&#93;</span></a></sup> </p><p>On 13 October 2020, Apple announced a new <a href="/wiki/IPhone_12" title="IPhone 12">iPhone 12</a> lineup using the <a href="/wiki/Apple_A14" title="Apple A14">A14</a>. Together with the <a href="/wiki/Huawei_Mate_40" title="Huawei Mate 40">Huawei Mate 40</a> lineup using the <a href="/wiki/HiSilicon#Kirin_9000_&amp;_Kirin_9000E" title="HiSilicon">HiSilicon Kirin 9000</a>, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's "5&#160;nm" node. Later, on 10 November 2020, Apple also revealed three new Mac models using the <a href="/wiki/Apple_M1" title="Apple M1">Apple M1</a>, another 5&#160;nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm<sup>2</sup>.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">&#91;</span>28<span class="cite-bracket">&#93;</span></a></sup> </p><p>In October 2021, TSMC introduced a new member of its "5&#160;nm" process family: N4P. Compared to N5, the node offered 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expected first tapeouts by the second half of 2022.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">&#91;</span>29<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">&#91;</span>30<span class="cite-bracket">&#93;</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The date of the event predicted near this tag has passed. (February 2024)">needs update</span></a></i>&#93;</sup> </p><p>In December 2021, TSMC announced a new member of its "5&#160;nm" process family designed for HPC applications: N4X. The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process was expected at that time to<sup class="noprint Inline-Template" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The date of the event predicted near this tag has passed. (February 2024)">needs update</span></a></i>&#93;</sup> offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2&#160;V and supply voltage in excess of 1.2&#160;V. TSMC, at that time, said that they expected<sup class="noprint Inline-Template" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The date of the event predicted near this tag has passed. (February 2024)">needs update</span></a></i>&#93;</sup> N4X to enter risk production by the first half of 2023.<sup id="cite_ref-n4x_pr_31-0" class="reference"><a href="#cite_note-n4x_pr-31"><span class="cite-bracket">&#91;</span>31<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-n4x_blog_32-0" class="reference"><a href="#cite_note-n4x_blog-32"><span class="cite-bracket">&#91;</span>32<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-n4x_at_33-0" class="reference"><a href="#cite_note-n4x_at-33"><span class="cite-bracket">&#91;</span>33<span class="cite-bracket">&#93;</span></a></sup> </p><p>In June 2022, Intel presented some details about the Intel 4 process (known as "7&#160;nm" before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as "10&#160;nm" ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 was Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.<sup id="cite_ref-intel4_at_34-0" class="reference"><a href="#cite_note-intel4_at-34"><span class="cite-bracket">&#91;</span>34<span class="cite-bracket">&#93;</span></a></sup> Intel 4 has contacted gate pitch of 50&#160;nm, both fin and minimum metal pitch of 30&#160;nm, and library height of 240&#160;nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">&#91;</span>35<span class="cite-bracket">&#93;</span></a></sup> The process was optimized for HPC applications and supported voltage from &lt;0.65 V to &gt;1.3 V. WikiChip's transistor density estimate for Intel 4 was 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell had scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.<sup id="cite_ref-intel4_wikichip_36-0" class="reference"><a href="#cite_note-intel4_wikichip-36"><span class="cite-bracket">&#91;</span>36<span class="cite-bracket">&#93;</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The date of the event predicted near this tag has passed. (February 2024)">needs update</span></a></i>&#93;</sup> </p><p>On 27 September 2022, <a href="/wiki/AMD" title="AMD">AMD</a> officially launched their <a href="/wiki/Ryzen_7000" class="mw-redirect" title="Ryzen 7000">Ryzen 7000</a> series of central processing units, based on the TSMC N5 process and <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> microarchitecture.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">&#91;</span>37<span class="cite-bracket">&#93;</span></a></sup> Zen 4 marked the first utilization of the 5&#160;nm process for x86-based desktop processors. In December 2022 AMD also launched the <a href="/wiki/Radeon_RX_7000_series" title="Radeon RX 7000 series">Radeon RX 7000 series</a> of graphics processing units based on <a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a>, which also used the TSMC N5 process.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">&#91;</span>38<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Nodes">Nodes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=4" title="Edit section: Nodes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align:center"> <caption>5&#160;nm </caption> <tbody><tr> <th> </th> <th colspan="2"><a href="/wiki/International_Roadmap_for_Devices_and_Systems" title="International Roadmap for Devices and Systems">IRDS</a> roadmap 2017<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">&#91;</span>39<span class="cite-bracket">&#93;</span></a></sup> </th> <th colspan="2"><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a><sup id="cite_ref-5nm_40-0" class="reference"><a href="#cite_note-5nm-40"><span class="cite-bracket">&#91;</span>40<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">&#91;</span>41<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-Samsung_5_nm_and_4_nm_Update_42-0" class="reference"><a href="#cite_note-Samsung_5_nm_and_4_nm_Update-42"><span class="cite-bracket">&#91;</span>42<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-5_nm_lithography_process_43-0" class="reference"><a href="#cite_note-5_nm_lithography_process-43"><span class="cite-bracket">&#91;</span>43<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-Samsung_44-0" class="reference"><a href="#cite_note-Samsung-44"><span class="cite-bracket">&#91;</span>44<span class="cite-bracket">&#93;</span></a></sup> </th> <th colspan="3"><a href="/wiki/TSMC" title="TSMC">TSMC</a><sup id="cite_ref-5nm_40-1" class="reference"><a href="#cite_note-5nm-40"><span class="cite-bracket">&#91;</span>40<span class="cite-bracket">&#93;</span></a></sup> </th></tr> <tr> <th>Process name </th> <td>7&#160;nm </td> <td>5&#160;nm </td> <td>5LPE </td> <td>5LPP </td> <td>N5 </td> <td>N5P </td> <td>4N<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">&#91;</span>45<span class="cite-bracket">&#93;</span></a></sup> </td></tr> <tr> <th>Transistor density (MTr/mm<sup>2</sup>) </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td>126.9<sup id="cite_ref-Samsung_44-1" class="reference"><a href="#cite_note-Samsung-44"><span class="cite-bracket">&#91;</span>44<span class="cite-bracket">&#93;</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2">138.2<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">&#91;</span>46<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">&#91;</span>47<span class="cite-bracket">&#93;</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Unknown </td></tr> <tr> <th>SRAM bit-cell size (μm<sup>2</sup>) </th> <td>0.027<sup id="cite_ref-mm2_48-0" class="reference"><a href="#cite_note-mm2-48"><span class="cite-bracket">&#91;</span>48<span class="cite-bracket">&#93;</span></a></sup> </td> <td>0.020<sup id="cite_ref-mm2_48-1" class="reference"><a href="#cite_note-mm2-48"><span class="cite-bracket">&#91;</span>48<span class="cite-bracket">&#93;</span></a></sup> </td> <td colspan="2">0.0262<sup id="cite_ref-BitS_49-0" class="reference"><a href="#cite_note-BitS-49"><span class="cite-bracket">&#91;</span>49<span class="cite-bracket">&#93;</span></a></sup> </td> <td colspan="2">0.021<sup id="cite_ref-BitS_49-1" class="reference"><a href="#cite_note-BitS-49"><span class="cite-bracket">&#91;</span>49<span class="cite-bracket">&#93;</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Unknown </td></tr> <tr> <th>Transistor gate pitch (nm) </th> <td>48 </td> <td>42 </td> <td colspan="2">57 </td> <td colspan="2">51 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Unknown </td></tr> <tr> <th>Interconnect pitch (nm) </th> <td>28 </td> <td>24 </td> <td>36 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2">28<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">&#91;</span>50<span class="cite-bracket">&#93;</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Unknown </td></tr> <tr> <th>Release status </th> <td>2019 </td> <td>2021 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2018 risk production<sup id="cite_ref-anandtech-samsung_18-1" class="reference"><a href="#cite_note-anandtech-samsung-18"><span class="cite-bracket">&#91;</span>18<span class="cite-bracket">&#93;</span></a></sup><br />2020 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2022 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2019 risk production<sup id="cite_ref-tsmc_19-1" class="reference"><a href="#cite_note-tsmc-19"><span class="cite-bracket">&#91;</span>19<span class="cite-bracket">&#93;</span></a></sup><br />2020 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2020 risk production<br />2021 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2022 production </td></tr> </tbody></table> <div class="mw-heading mw-heading2"><h2 id="4_nm_process_nodes">4 nm process nodes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=5" title="Edit section: 4 nm process nodes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align:center"> <tbody><tr> <th> </th> <th colspan="5"><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a><sup id="cite_ref-5nm_40-2" class="reference"><a href="#cite_note-5nm-40"><span class="cite-bracket">&#91;</span>40<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-Samsung_5_nm_and_4_nm_Update_42-1" class="reference"><a href="#cite_note-Samsung_5_nm_and_4_nm_Update-42"><span class="cite-bracket">&#91;</span>42<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-5_nm_lithography_process_43-1" class="reference"><a href="#cite_note-5_nm_lithography_process-43"><span class="cite-bracket">&#91;</span>43<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-Samsung_44-2" class="reference"><a href="#cite_note-Samsung-44"><span class="cite-bracket">&#91;</span>44<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">&#91;</span>51<span class="cite-bracket">&#93;</span></a></sup> </th> <th colspan="4"><a href="/wiki/TSMC" title="TSMC">TSMC</a> </th> <th><a href="/wiki/Intel" title="Intel">Intel</a><sup id="cite_ref-intel_rm_2025_52-0" class="reference"><a href="#cite_note-intel_rm_2025-52"><span class="cite-bracket">&#91;</span>52<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-intel4_at_34-1" class="reference"><a href="#cite_note-intel4_at-34"><span class="cite-bracket">&#91;</span>34<span class="cite-bracket">&#93;</span></a></sup> </th></tr> <tr> <th>Process name </th> <td>4LPE<br />SF4E</td> <td>4LPP<br />SF4</td> <td>4LPP+<br />SF4P</td> <td>4HPC<br />SF4X</td> <td>4LPA<br />SF4U </td> <td>N4</td> <td>N4P</td> <td>N4X<sup id="cite_ref-n4x_pr_31-1" class="reference"><a href="#cite_note-n4x_pr-31"><span class="cite-bracket">&#91;</span>31<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-n4x_blog_32-1" class="reference"><a href="#cite_note-n4x_blog-32"><span class="cite-bracket">&#91;</span>32<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-n4x_at_33-1" class="reference"><a href="#cite_note-n4x_at-33"><span class="cite-bracket">&#91;</span>33<span class="cite-bracket">&#93;</span></a></sup></td> <td>N4C<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">&#91;</span>53<span class="cite-bracket">&#93;</span></a></sup> </td> <td>4<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">&#91;</span>54<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">&#91;</span>55<span class="cite-bracket">&#93;</span></a></sup> </td></tr> <tr> <th>Transistor density (MTr/mm<sup>2</sup>) </th> <td colspan="2">137<sup id="cite_ref-Samsung_44-3" class="reference"><a href="#cite_note-Samsung-44"><span class="cite-bracket">&#91;</span>44<span class="cite-bracket">&#93;</span></a></sup></td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2">143.7<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">&#91;</span>56<span class="cite-bracket">&#93;</span></a></sup></td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td>123.4<sup id="cite_ref-intel4_wikichip_36-1" class="reference"><a href="#cite_note-intel4_wikichip-36"><span class="cite-bracket">&#91;</span>36<span class="cite-bracket">&#93;</span></a></sup> </td></tr> <tr> <th>SRAM bit-cell size (μm<sup>2</sup>) </th> <td colspan="2">0.0262<sup id="cite_ref-BitS_49-2" class="reference"><a href="#cite_note-BitS-49"><span class="cite-bracket">&#91;</span>49<span class="cite-bracket">&#93;</span></a></sup></td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td>0.024<sup id="cite_ref-BitS_49-3" class="reference"><a href="#cite_note-BitS-49"><span class="cite-bracket">&#91;</span>49<span class="cite-bracket">&#93;</span></a></sup> </td></tr> <tr> <th>Transistor gate pitch (nm) </th> <td colspan="2">57</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2">51</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td>50 </td></tr> <tr> <th>Interconnect pitch (nm) </th> <td colspan="2">32</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td colspan="2">28</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Un­known">Un­known </td> <td>30 </td></tr> <tr> <th>Release status </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2020 risk production<br />2021 production</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2022 production</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2023 production</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">2024 production</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">2025 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2021 risk production<br />2022 production</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2022 risk production<br />2022 production</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Risk production by H1 2023<br />2024 production</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">2025 production </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">2022 risk production<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">&#91;</span>57<span class="cite-bracket">&#93;</span></a></sup><br />2023 production<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">&#91;</span>58<span class="cite-bracket">&#93;</span></a></sup> </td></tr> </tbody></table> <p>Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">&#91;</span>59<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">&#91;</span>60<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Beyond_4_nm">Beyond 4&#160;nm</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=6" title="Edit section: Beyond 4 nm"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/3_nm_process" title="3 nm process">3&#160;nm process</a></div> <p>"3&#160;nm" is the usual term for the next node after "5&#160;nm". As of 2023<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=5_nm_process&amp;action=edit">&#91;update&#93;</a></sup>, <a href="/wiki/TSMC" title="TSMC">TSMC</a> has started producing chips for select customers, while <a href="/wiki/Samsung" title="Samsung">Samsung</a> and <a href="/wiki/Intel" title="Intel">Intel</a> have plans for 2024.<sup id="cite_ref-intel_rm_2025_52-1" class="reference"><a href="#cite_note-intel_rm_2025-52"><span class="cite-bracket">&#91;</span>52<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">&#91;</span>61<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">&#91;</span>62<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">&#91;</span>63<span class="cite-bracket">&#93;</span></a></sup> </p><p>"3.5&#160;nm" has also been given as a name for the first node beyond "5&#160;nm".<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">&#91;</span>64<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=7" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output 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a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output 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International Electron Devices Meeting. pp.&#160;267–270. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FIEDM.2002.1175829">10.1109/IEDM.2002.1175829</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a>&#160;<a href="/wiki/Special:BookSources/0-7803-7462-2" title="Special:BookSources/0-7803-7462-2"><bdi>0-7803-7462-2</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a>&#160;<a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:10151651">10151651</a>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&amp;rft.genre=conference&amp;rft.btitle=Extreme+scaling+with+ultra-thin+Si+channel+MOSFETs&amp;rft.pages=267-270&amp;rft.date=2002-12&amp;rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A10151651%23id-name%3DS2CID&amp;rft_id=info%3Adoi%2F10.1109%2FIEDM.2002.1175829&amp;rft.isbn=0-7803-7462-2&amp;rft.aulast=Doris&amp;rft.aufirst=Bruce+B.&amp;rft.au=Dokumaci%2C+Omer+H.&amp;rft.au=Ieong%2C+Meikei+K.&amp;rft.au=Mocuta%2C+Anda&amp;rft.au=Zhang%2C+Ying&amp;rft.au=Kanarsky%2C+Thomas+S.&amp;rft.au=Roy%2C+R.+A.&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.thefreelibrary.com/NEC+test-produces+world%27s+smallest+transistor.-a0111295563">"NEC test-produces world's smallest transistor"</a>. <i>Thefreelibrary.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170415012122/https://www.thefreelibrary.com/NEC+test-produces+world%27s+smallest+transistor.-a0111295563">Archived</a> from the original on 15 April 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">7 December</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Thefreelibrary.com&amp;rft.atitle=NEC+test-produces+world%27s+smallest+transistor&amp;rft_id=http%3A%2F%2Fwww.thefreelibrary.com%2FNEC%2Btest-produces%2Bworld%2527s%2Bsmallest%2Btransistor.-a0111295563&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWakabayashiYamagamiIkezawaOgura2003" class="citation conference cs1">Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). <i>Sub-10-nm planar-bulk-CMOS devices using lateral junction control</i>. IEEE International Electron Devices Meeting 2003. pp.&#160;20.7.1–20.7.3. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FIEDM.2003.1269446">10.1109/IEDM.2003.1269446</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a>&#160;<a href="/wiki/Special:BookSources/0-7803-7872-5" title="Special:BookSources/0-7803-7872-5"><bdi>0-7803-7872-5</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a>&#160;<a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:2100267">2100267</a>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&amp;rft.genre=conference&amp;rft.btitle=Sub-10-nm+planar-bulk-CMOS+devices+using+lateral+junction+control&amp;rft.pages=20.7.1-20.7.3&amp;rft.date=2003-12&amp;rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A2100267%23id-name%3DS2CID&amp;rft_id=info%3Adoi%2F10.1109%2FIEDM.2003.1269446&amp;rft.isbn=0-7803-7872-5&amp;rft.aulast=Wakabayashi&amp;rft.aufirst=Hitoshi&amp;rft.au=Yamagami%2C+Shigeharu&amp;rft.au=Ikezawa%2C+Nobuyuki&amp;rft.au=Ogura%2C+Atsushi&amp;rft.au=Narihiro%2C+Mitsuru&amp;rft.au=Arai%2C+K.&amp;rft.au=Ochiai%2C+Y.&amp;rft.au=Takeuchi%2C+K.&amp;rft.au=Yamamoto%2C+T.&amp;rft.au=Mogami%2C+T.&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://semiwiki.com/eda/cadence/5080-imec-and-cadence-disclose-5nm-test-chip/">"IMEC and Cadence Disclose 5nm Test Chip"</a>. <i>Semiwiki.com</i>. 4 July 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">4 July</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Semiwiki.com&amp;rft.atitle=IMEC+and+Cadence+Disclose+5nm+Test+Chip&amp;rft.date=2023-07-04&amp;rft_id=https%3A%2F%2Fsemiwiki.com%2Feda%2Fcadence%2F5080-imec-and-cadence-disclose-5nm-test-chip%2F&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20151126115543/http://www.semi.org/en/node/55926">"The Roadmap to 5nm: Convergence of Many Solutions Needed"</a>. <i>Semi.org</i>. Archived from <a rel="nofollow" class="external text" href="http://www.semi.org/en/node/55926">the original</a> on 26 November 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">25 November</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Semi.org&amp;rft.atitle=The+Roadmap+to+5nm%3A+Convergence+of+Many+Solutions+Needed&amp;rft_id=http%3A%2F%2Fwww.semi.org%2Fen%2Fnode%2F55926&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-semiengineering_2016Jan-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-semiengineering_2016Jan_14-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMark_LaPedus2016" class="citation web cs1">Mark LaPedus (20 January 2016). <a rel="nofollow" class="external text" href="http://semiengineering.com/5nm-fab-challenges/">"5nm Fab Challenges"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160127230827/http://semiengineering.com/5nm-fab-challenges/">Archived</a> from the original on 27 January 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">22 January</span> 2016</span>. <q>Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).</q></cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&amp;rft.genre=unknown&amp;rft.btitle=5nm+Fab+Challenges&amp;rft.date=2016-01-20&amp;rft.au=Mark+LaPedus&amp;rft_id=http%3A%2F%2Fsemiengineering.com%2F5nm-fab-challenges%2F&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSebastian2017" class="citation web cs1">Sebastian, Anthony (5 June 2017). <a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2017/06/ibm-5nm-chip/">"IBM unveils world's first 5nm chip"</a>. <i>Ars Technica</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170605202822/https://arstechnica.com/gadgets/2017/06/ibm-5nm-chip/">Archived</a> from the original on 5 June 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">5 June</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Ars+Technica&amp;rft.atitle=IBM+unveils+world%27s+first+5nm+chip&amp;rft.date=2017-06-05&amp;rft.aulast=Sebastian&amp;rft.aufirst=Anthony&amp;rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2017%2F06%2Fibm-5nm-chip%2F&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHuiming2017" class="citation web cs1">Huiming, Bu (5 June 2017). <a rel="nofollow" class="external text" href="https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/">"5 nanometer transistors inching their way into chips"</a>. <i><a href="/wiki/IBM" title="IBM">IBM</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210609002051/https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/">Archived</a> from the original on 9 June 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">9 June</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=IBM&amp;rft.atitle=5+nanometer+transistors+inching+their+way+into+chips&amp;rft.date=2017-06-05&amp;rft.aulast=Huiming&amp;rft.aufirst=Bu&amp;rft_id=https%3A%2F%2Fwww.ibm.com%2Fblogs%2Fthink%2F2017%2F06%2F5-nanometer-transistors%2F&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://uk.pcmag.com/news/89652/ibm-figures-out-how-to-make-5nm-chips">"IBM Figures Out How to Make 5nm Chips"</a>. <i>Uk.pcmag.com</i>. 5 June 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171203054459/http://uk.pcmag.com/news/89652/ibm-figures-out-how-to-make-5nm-chips">Archived</a> from the original on 3 December 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">7 December</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Uk.pcmag.com&amp;rft.atitle=IBM+Figures+Out+How+to+Make+5nm+Chips&amp;rft.date=2017-06-05&amp;rft_id=http%3A%2F%2Fuk.pcmag.com%2Fnews%2F89652%2Fibm-figures-out-how-to-make-5nm-chips&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-anandtech-samsung-18"><span class="mw-cite-backlink">^ <a href="#cite_ref-anandtech-samsung_18-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-anandtech-samsung_18-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShilov" class="citation web cs1">Shilov, Anton. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology">"Samsung Completes Development of 5nm EUV Process Technology"</a>. <i><a href="/wiki/AnandTech" title="AnandTech">AnandTech</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190420144452/https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology">Archived</a> from the original on 20 April 2019<span class="reference-accessdate">. Retrieved <span class="nowrap">31 May</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=AnandTech&amp;rft.atitle=Samsung+Completes+Development+of+5nm+EUV+Process+Technology&amp;rft.aulast=Shilov&amp;rft.aufirst=Anton&amp;rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14231%2Fsamsung-completes-development-of-5-nm-euv-process-technology&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-tsmc-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-tsmc_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-tsmc_19-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://pr.tsmc.com/english/news/1987">"TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology"</a> (Press release). TSMC. 3 April 2019.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&amp;rft.genre=unknown&amp;rft.btitle=TSMC+and+OIP+Ecosystem+Partners+Deliver+Industry%27s+First+Complete+Design+Infrastructure+for+5nm+Process+Technology&amp;rft.pub=TSMC&amp;rft.date=2019-04-03&amp;rft_id=https%3A%2F%2Fpr.tsmc.com%2Fenglish%2Fnews%2F1987&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen">"SALELE Double Patterning for 7nm and 5nm Nodes"</a>. <i><a href="/wiki/LinkedIn" title="LinkedIn">LinkedIn</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210920235246/https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen">Archived</a> from the original on 20 September 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">25 March</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=LinkedIn&amp;rft.atitle=SALELE+Double+Patterning+for+7nm+and+5nm+Nodes&amp;rft_id=https%3A%2F%2Fwww.linkedin.com%2Fpulse%2Fsalele-double-patterning-7nm-5nm-nodes-frederick-chen&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJaehwan_KimJin_KimByungchul_ShinSangah_Lee2020" class="citation conference cs1">Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella; Frank E. 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Retrieved <span class="nowrap">27 July</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=AnandTech&amp;rft.atitle=TSMC+Update%3A+2nm+in+Development%2C+3nm+and+4nm+on+Track+for+2022&amp;rft.aulast=Shilov&amp;rft.aufirst=Anton&amp;rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16639%2Ftsmc-update-2nm-in-development-3nm-4nm-on-track-for-2022&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> <li id="cite_note-64"><span class="mw-cite-backlink"><b><a href="#cite_ref-64">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.eetimes.com/document.asp?doc_id=1331185">"15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon"</a>. <i><a href="/wiki/EE_Times" title="EE Times">EE Times</a></i>. 16 January 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180628100622/https://www.eetimes.com/document.asp?doc_id=1331185">Archived</a> from the original on 28 June 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">4 June</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=EE+Times&amp;rft.atitle=15+Views+from+a+Silicon+Summit%3A+Macro+to+nano+perspectives+of+chip+horizon&amp;rft.date=2017-01-16&amp;rft_id=https%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1331185&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3A5+nm+process" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=5_nm_process&amp;action=edit&amp;section=8" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/5_nm_lithography_process">5 nm lithography process</a></li></ul> <table class="wikitable" style="margin:0.5em auto; font-size:95%; clear: both;"> <tbody><tr> <td style="width: 30%; text-align: center;">Preceded&#160;by<br /><b><a href="/wiki/7_nm_process" title="7 nm process">"7&#160;nm"</a> (<a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a>)</b> </td> <td style="text-align: center;"><b><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">semiconductor device fabrication</a> process</b> </td> <td style="width: 30%; text-align: center;">Succeeded&#160;by<br /><b><a href="/wiki/3_nm_process" title="3 nm process">"3&#160;nm"</a> (<a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a>/<a href="/wiki/GAAFET" class="mw-redirect" title="GAAFET">GAAFET</a>)</b> </td></tr></tbody></table> <!-- NewPP limit report Parsed by mw‐web.eqiad.main‐559c9fd9f4‐c5wvg Cached time: 20241126123014 Cache expiry: 2592000 Reduced expiry: false Complications: [vary‐revision‐sha1, show‐toc] CPU time usage: 0.751 seconds Real time usage: 0.897 seconds Preprocessor visited node count: 4595/1000000 Post‐expand include size: 145820/2097152 bytes Template argument size: 4034/2097152 bytes Highest expansion depth: 15/100 Expensive parser function count: 5/500 Unstrip recursion depth: 1/20 Unstrip post‐expand size: 233539/5000000 bytes Lua time usage: 0.467/10.000 seconds Lua memory usage: 6507385/52428800 bytes Number of Wikibase entities loaded: 0/400 --> <!-- Transclusion expansion time report (%,ms,calls,template) 100.00% 814.555 1 -total 50.52% 411.485 1 Template:Reflist 32.24% 262.604 47 Template:Cite_web 15.82% 128.836 1 Template:Semiconductor_manufacturing_processes 15.26% 124.303 1 Template:Sidebar 11.94% 97.266 1 Template:Short_description 8.55% 69.669 4 Template:And_then_what 7.58% 61.750 1 Template:Navbar 6.56% 53.417 4 Template:Fix 6.17% 50.275 2 Template:Pagetype --> <!-- Saved in parser cache with key enwiki:pcache:31882635:|#|:idhash:canonical and timestamp 20241126123014 and revision id 1254163077. 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