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MOSFET</title> <meta name="description" content="Search results for: PDSOI MOSFET"> <meta name="keywords" content="PDSOI MOSFET"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none navbar-toggler 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id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="PDSOI MOSFET"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 44</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: PDSOI MOSFET</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">44</span> Simulation of High Performance Nanoscale Partially Depleted SOI n-MOSFET Transistors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fatima%20Zohra%20Rahou">Fatima Zohra Rahou</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Guen%20Bouazza"> A. Guen Bouazza</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Bouazza"> B. Bouazza</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SOI%20technology" title="SOI technology">SOI technology</a>, <a href="https://publications.waset.org/abstracts/search?q=PDSOI%20MOSFET" title=" PDSOI MOSFET"> PDSOI MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=FDSOI%20MOSFET" title=" FDSOI MOSFET"> FDSOI MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=kink%20effect" title=" kink effect"> kink effect</a> </p> <a href="https://publications.waset.org/abstracts/61667/simulation-of-high-performance-nanoscale-partially-depleted-soi-n-mosfet-transistors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/61667.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">258</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">43</span> The Experience with SiC MOSFET and Buck Converter Snubber Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Petr%20Vaculik">Petr Vaculik</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SiC" title="SiC">SiC</a>, <a href="https://publications.waset.org/abstracts/search?q=Si" title=" Si"> Si</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=IGBT" title=" IGBT"> IGBT</a>, <a href="https://publications.waset.org/abstracts/search?q=SBD" title=" SBD"> SBD</a>, <a href="https://publications.waset.org/abstracts/search?q=RC%20snubber" title=" RC snubber"> RC snubber</a> </p> <a href="https://publications.waset.org/abstracts/3291/the-experience-with-sic-mosfet-and-buck-converter-snubber-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/3291.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">484</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">42</span> Power MOSFET Models Including Quasi-Saturation Effect</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelghafour%20Galadi">Abdelghafour Galadi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=power%20MOSFET" title="power MOSFET">power MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=drift%20layer" title=" drift layer"> drift layer</a>, <a href="https://publications.waset.org/abstracts/search?q=quasi-saturation%20effect" title=" quasi-saturation effect"> quasi-saturation effect</a>, <a href="https://publications.waset.org/abstracts/search?q=SPICE%20model" title=" SPICE model"> SPICE model</a> </p> <a href="https://publications.waset.org/abstracts/54686/power-mosfet-models-including-quasi-saturation-effect" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/54686.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">194</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">41</span> High Performance of Square GAA SOI MOSFET Using High-k Dielectric with Metal Gate</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fatima%20Zohra%20Rahou">Fatima Zohra Rahou</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Guen%20Bouazza"> A. Guen Bouazza</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Bouazza"> B. Bouazza</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Multi-gate SOI MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with a scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high -k dielectric materials as oxide layer at different places in MOSFET structures. One of the most important multi-gate structures is square GAA SOI MOSFET that is a strong candidate for the next generation nanoscale devices; show an even stronger control of short channel effects. In this paper, GAA SOI MOSFET structure with using high -k dielectrics materials Al2O3 (k~9), HfO2 (k~20), La2O3 (k~30) and metal gate TiN are simulated by using 3-D device simulator DevEdit and Atlas of SILVACO TCAD tools. Square GAA SOI MOSFET transistor with High-k HfO2 gate dielectrics and TiN metal gate exhibits significant improvements performances compared to Al2O3 and La2O3 dielectrics for the same structure. Simulation results of GAA SOI MOSFET transistor with HfO2 dielectric show the increase in saturation current and Ion/Ioff ratio while leakage current, subthreshold slope and DIBL effect are decreased. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=technology%20SOI" title="technology SOI">technology SOI</a>, <a href="https://publications.waset.org/abstracts/search?q=short-channel%20effects%20%28SCEs%29" title=" short-channel effects (SCEs)"> short-channel effects (SCEs)</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-gate%20SOI%20MOSFET" title=" multi-gate SOI MOSFET"> multi-gate SOI MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=square%20GAA%20SOI%20MOSFET" title=" square GAA SOI MOSFET"> square GAA SOI MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=high-k%20dielectric" title=" high-k dielectric"> high-k dielectric</a>, <a href="https://publications.waset.org/abstracts/search?q=Silvaco%20software" title=" Silvaco software "> Silvaco software </a> </p> <a href="https://publications.waset.org/abstracts/38250/high-performance-of-square-gaa-soi-mosfet-using-high-k-dielectric-with-metal-gate" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38250.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">262</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">40</span> Analysis of Scaling Effects on Analog/RF Performance of Nanowire Gate-All-Around MOSFET</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Dheeraj%20Sharma">Dheeraj Sharma</a>, <a href="https://publications.waset.org/abstracts/search?q=Santosh%20Kumar%20Vishvakarma"> Santosh Kumar Vishvakarma</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Gate-All-Around%20MOSFET" title="Gate-All-Around MOSFET">Gate-All-Around MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=GAA" title=" GAA"> GAA</a>, <a href="https://publications.waset.org/abstracts/search?q=output%20resistance" title=" output resistance"> output resistance</a>, <a href="https://publications.waset.org/abstracts/search?q=transconductance%20generation%20factor" title=" transconductance generation factor"> transconductance generation factor</a>, <a href="https://publications.waset.org/abstracts/search?q=intrinsic%20gain" title=" intrinsic gain"> intrinsic gain</a>, <a href="https://publications.waset.org/abstracts/search?q=cutoff%20frequency" title=" cutoff frequency"> cutoff frequency</a>, <a href="https://publications.waset.org/abstracts/search?q=fT" title=" fT"> fT</a> </p> <a href="https://publications.waset.org/abstracts/28209/analysis-of-scaling-effects-on-analogrf-performance-of-nanowire-gate-all-around-mosfet" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28209.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">397</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">39</span> Design Ultra Fast Gate Drive Board for Silicon Carbide MOSFET Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Syakirin%20O.%20Yong">Syakirin O. Yong</a>, <a href="https://publications.waset.org/abstracts/search?q=Nasrudin%20A.%20Rahim"> Nasrudin A. Rahim</a>, <a href="https://publications.waset.org/abstracts/search?q=Bilal%20M.%20Eid"> Bilal M. Eid</a>, <a href="https://publications.waset.org/abstracts/search?q=Buray%20Tankut"> Buray Tankut</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The aim of this paper is to develop an ultra-fast gate driver for Silicon Carbide (SiC) based switching device applications such as AC/DC DC/AC converters. Wide bandgap semiconductors such as SiC switches are growing rapidly nowadays due to their numerous capabilities such as faster switching, higher power density and higher voltage level. Wide band-gap switches can work properly on high frequencies such 50-250 kHz which is very useful for many power electronic applications such as solar inverters. Increasing the frequency minimizes the output filter size and system complexity however, this causes huge spike between MOSFET’s drain and source leg which leads to the failure of MOSFET if the voltage rating is exceeded. This paper investigates and concludes the optimum design for a gate drive board for SiC MOSFET switches without causing spikes and noises. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=PV%20system" title="PV system">PV system</a>, <a href="https://publications.waset.org/abstracts/search?q=lithium-ion" title=" lithium-ion"> lithium-ion</a>, <a href="https://publications.waset.org/abstracts/search?q=charger" title=" charger"> charger</a>, <a href="https://publications.waset.org/abstracts/search?q=constant%20current" title=" constant current"> constant current</a>, <a href="https://publications.waset.org/abstracts/search?q=constant%20voltage" title=" constant voltage"> constant voltage</a>, <a href="https://publications.waset.org/abstracts/search?q=renewable%20energy" title=" renewable energy"> renewable energy</a> </p> <a href="https://publications.waset.org/abstracts/146295/design-ultra-fast-gate-drive-board-for-silicon-carbide-mosfet-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/146295.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">156</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">38</span> Gate Voltage Controlled Humidity Sensing Using MOSFET of VO2 Particles</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.%20A.%20Akande">A. A. Akande</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20P.%20Dhonge"> B. P. Dhonge</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20W.%20Mwakikunga"> B. W. Mwakikunga</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20G.%20J.%20Machatine"> A. G. J. Machatine</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH<sub>4</sub>VO<sub>3</sub> precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO<sub>2</sub> (B) with V<sub>2</sub>O<sub>5 </sub>and an amorphous phase. The BET surface area is found to be 67.67 m<sup>2</sup>/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO<sub>2</sub> sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO<sub>2</sub> sensors which normally show response and recovery times of the order of 5 minutes (300 s). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=VO2" title="VO2">VO2</a>, <a href="https://publications.waset.org/abstracts/search?q=VO2%28B%29" title=" VO2(B)"> VO2(B)</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=gate%20voltage" title=" gate voltage"> gate voltage</a>, <a href="https://publications.waset.org/abstracts/search?q=humidity%20sensor" title=" humidity sensor"> humidity sensor</a> </p> <a href="https://publications.waset.org/abstracts/60921/gate-voltage-controlled-humidity-sensing-using-mosfet-of-vo2-particles" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/60921.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">322</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">37</span> 2 Stage CMOS Regulated Cascode Distributed Amplifier Design Based On Inductive Coupling Technique in Submicron CMOS Process</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kittipong%20Tripetch">Kittipong Tripetch</a>, <a href="https://publications.waset.org/abstracts/search?q=Nobuhiko%20Nakano"> Nobuhiko Nakano</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20regulated%20cascode%20distributed%20amplifier" title="CMOS regulated cascode distributed amplifier">CMOS regulated cascode distributed amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=silicon%20transformer%20modeling%20with%20polynomial" title=" silicon transformer modeling with polynomial"> silicon transformer modeling with polynomial</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power%20consumption" title=" low power consumption"> low power consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=distribute%20amplification%20technique" title=" distribute amplification technique"> distribute amplification technique</a> </p> <a href="https://publications.waset.org/abstracts/24466/2-stage-cmos-regulated-cascode-distributed-amplifier-design-based-on-inductive-coupling-technique-in-submicron-cmos-process" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/24466.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">512</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">36</span> A Double Epilayer PSGT Trench Power MOSFETs for Low to Medium Voltage Power Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Alok%20Kumar%20Kamal">Alok Kumar Kamal</a>, <a href="https://publications.waset.org/abstracts/search?q=Vinod%20Kumar"> Vinod Kumar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The trench gate MOSFET has shown itself as the most appropriate power device for low to medium voltage power applications due to its lowest possible ON resistance among all power semiconductor devices. In this research work a double-epilayer PSGT structure using a thin layer of N+ polysilicon as gate material. The total ON-state resistance (RON) of UMOSFET can be reduced by optimizing the epilayer thickness. The optimized structure of Double-Epilayer exhibits a 25.8% reduction in the ON-state resistance at Vgs=5V and improving the switching characteristics by reducing the Reverse transfer capacitance (Cgd) by 7.4%. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Miller-capacitance" title="Miller-capacitance">Miller-capacitance</a>, <a href="https://publications.waset.org/abstracts/search?q=double-Epilayer%3Bswitching%20characteristics" title=" double-Epilayer;switching characteristics"> double-Epilayer;switching characteristics</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20trench%20MOSFET%20%28U-MOSFET%29" title=" power trench MOSFET (U-MOSFET)"> power trench MOSFET (U-MOSFET)</a>, <a href="https://publications.waset.org/abstracts/search?q=on-state%20resistance" title=" on-state resistance"> on-state resistance</a>, <a href="https://publications.waset.org/abstracts/search?q=blocking%20voltage" title=" blocking voltage"> blocking voltage</a> </p> <a href="https://publications.waset.org/abstracts/183038/a-double-epilayer-psgt-trench-power-mosfets-for-low-to-medium-voltage-power-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/183038.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">73</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">35</span> Pulsed Laser Single Event Transients in 0.18 μM Partially-Depleted Silicon-On-Insulator Device</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=MeiBo">MeiBo</a>, <a href="https://publications.waset.org/abstracts/search?q=ZhaoXing"> ZhaoXing</a>, <a href="https://publications.waset.org/abstracts/search?q=LuoLei"> LuoLei</a>, <a href="https://publications.waset.org/abstracts/search?q=YuQingkui"> YuQingkui</a>, <a href="https://publications.waset.org/abstracts/search?q=TangMin"> TangMin</a>, <a href="https://publications.waset.org/abstracts/search?q=HanZhengsheng"> HanZhengsheng</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Single Event Transients (SETs) were investigated on 0.18μm PDSOI transistors and 100 series CMOS inverter chain using pulse laser. The effect of different laser energy and device bias for waveform on SET was characterized experimentally, as well as the generation and propagation of SET in inverter chain. In this paper, the effects of struck transistors type and struck locations on SETs were investigated. The results showed that when irradiate NMOSFETs from 100th to 2nd stages, the SET pulse width measured at the output terminal increased from 287.4 ps to 472.9 ps; and when irradiate PMOSFETs from 99th to 1st stages, the SET pulse width increased from 287.4 ps to 472.9 ps. When struck locations were close to the output of the chain, the SET pulse was narrow; however, when struck nodes were close to the input, the SET pulse was broadening. SET pulses were progressively broadened up when propagating along inverter chains. The SET pulse broadening is independent of the type of struck transistors. Through analysis, history effect induced threshold voltage hysteresis in PDSOI is the reason of pulse broadening. The positive pulse observed by oscilloscope, contrary to the expected results, is because of charging and discharging of capacitor. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=single%20event%20transients" title="single event transients">single event transients</a>, <a href="https://publications.waset.org/abstracts/search?q=pulse%20laser" title=" pulse laser"> pulse laser</a>, <a href="https://publications.waset.org/abstracts/search?q=partially-depleted%20silicon-on-insulator" title=" partially-depleted silicon-on-insulator"> partially-depleted silicon-on-insulator</a>, <a href="https://publications.waset.org/abstracts/search?q=propagation-induced%20pulse%20broadening%20effect" title=" propagation-induced pulse broadening effect"> propagation-induced pulse broadening effect</a> </p> <a href="https://publications.waset.org/abstracts/34850/pulsed-laser-single-event-transients-in-018-mm-partially-depleted-silicon-on-insulator-device" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/34850.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">412</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">34</span> Influence of Temperature on Properties of MOSFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Azizi%20Cherifa">Azizi Cherifa</a>, <a href="https://publications.waset.org/abstracts/search?q=O.%20Benzaoui"> O. Benzaoui </a> </p> <p class="card-text"><strong>Abstract:</strong></p> The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=temperature" title="temperature">temperature</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=mobility" title=" mobility"> mobility</a>, <a href="https://publications.waset.org/abstracts/search?q=transistor" title=" transistor"> transistor</a> </p> <a href="https://publications.waset.org/abstracts/42385/influence-of-temperature-on-properties-of-mosfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/42385.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">346</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">33</span> Optimisation of Photovoltaic Array with DC-DC Converter Groups</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fatma%20Soltani">Fatma Soltani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In power electronics the DC-DC converters or choppers are now employed in large areas, particularly in the field of electricity generation by wind and solar energy conversion. Photovoltaic generators (GPV) can deliver maximum power for a point on the characteristic P = f (Vpv), called maximum power point (MPP), or climatic variations, entraiment fluctuation PPM. To remedy this problem is interposed between the generator and receiver a DC-DC converter. The converter is usually used a simple MOSFET chopper. However, the MOSFET can be applied in the field of low power when you need a high switching frequency but becomes highly dissipative when should block large voltages For PV generators medium and high power, the use of IGBT chopper is by far the most recommended. To reduce stress on semiconductor components using several choppers series connected in parallel is known as interleaved chopper. These choppers lead to rotas. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=converter%20DC-DC%20entrelaced%01%02%01" title="converter DC-DC entrelaced">converter DC-DC entrelaced</a>, <a href="https://publications.waset.org/abstracts/search?q=photovoltaic%20generators" title=" photovoltaic generators"> photovoltaic generators</a>, <a href="https://publications.waset.org/abstracts/search?q=IGBT" title=" IGBT"> IGBT</a>, <a href="https://publications.waset.org/abstracts/search?q=optimisation" title=" optimisation"> optimisation</a> </p> <a href="https://publications.waset.org/abstracts/21869/optimisation-of-photovoltaic-array-with-dc-dc-converter-groups" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21869.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">539</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">32</span> Analysis and Design of Single Switch Mosfet Dimmer for AC Driven Lamp</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.Pandeeswari">S.Pandeeswari</a>, <a href="https://publications.waset.org/abstracts/search?q=Raju%20Padma"> Raju Padma </a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper a new solution to implement and control single-stage electronic ballast based on the integration of a buck-boost power factor correction stage and a half bridge resonant inverter is presented. The control signals are obtained using the inverter resonant current by means of a saturable transformer. Core saturation is used to control the required dead time between the control pulses on both switches. The turn-on time of one of the inverter switches is controlled to provide proper cathode preheating during the lamp ignition process. No special integrated circuits are required to control the ballast and the total number of components is minimized. Analysis and basic design of phase cut dimmer. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=MOSFET%20dimmer" title="MOSFET dimmer">MOSFET dimmer</a>, <a href="https://publications.waset.org/abstracts/search?q=PIC%2016F877A" title=" PIC 16F877A"> PIC 16F877A</a>, <a href="https://publications.waset.org/abstracts/search?q=voltage%20regulator" title=" voltage regulator"> voltage regulator</a>, <a href="https://publications.waset.org/abstracts/search?q=bridge%20rectifier" title=" bridge rectifier"> bridge rectifier</a> </p> <a href="https://publications.waset.org/abstracts/27910/analysis-and-design-of-single-switch-mosfet-dimmer-for-ac-driven-lamp" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/27910.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">379</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">31</span> Efficient Control of Brushless DC Motors with Pulse Width Modulation</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Shahzadi">S. Shahzadi</a>, <a href="https://publications.waset.org/abstracts/search?q=J.%20Rizk"> J. Rizk</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper describes the pulse width modulated control of a three phase, 4 polar DC brushless motor. To implement this practically the Atmel’s AVR ATmega 328 microcontroller embedded on an Arduino Eleven board is utilized. The microcontroller programming is done in an open source Arduino IDE development environment. The programming logic effectively manipulated a six MOSFET bridge which was used to energize the stator windings as per control requirements. The results obtained showed accurate, precise and efficient pulse width modulated operation. Another advantage offered by this pulse width modulated control was the efficient speed control of the motor. By varying the time intervals between successive commutations, faster energizing of the stator windings was possible thereby leading to quicker rotor alignment with these energized phases and faster revolutions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=brushless%20DC%20motors" title="brushless DC motors">brushless DC motors</a>, <a href="https://publications.waset.org/abstracts/search?q=commutation" title=" commutation"> commutation</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=PWM" title=" PWM"> PWM</a> </p> <a href="https://publications.waset.org/abstracts/32239/efficient-control-of-brushless-dc-motors-with-pulse-width-modulation" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32239.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">512</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">30</span> Replacing MOSFETs with Single Electron Transistors (SET) to Reduce Power Consumption of an Inverter Circuit</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ahmed%20Shariful%20Alam">Ahmed Shariful Alam</a>, <a href="https://publications.waset.org/abstracts/search?q=Abu%20Hena%20M.%20Mustafa%20Kamal"> Abu Hena M. Mustafa Kamal</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20Abdul%20Rahman"> M. Abdul Rahman</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20Nasmus%20Sakib%20Khan%20Shabbir"> M. Nasmus Sakib Khan Shabbir</a>, <a href="https://publications.waset.org/abstracts/search?q=Atiqul%20Islam"> Atiqul Islam</a> </p> <p class="card-text"><strong>Abstract:</strong></p> According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. <em>35mV</em> supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was <em>3.5V</em>. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ITRS" title="ITRS">ITRS</a>, <a href="https://publications.waset.org/abstracts/search?q=enhancement%20type%20MOSFET" title=" enhancement type MOSFET"> enhancement type MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=island" title=" island"> island</a>, <a href="https://publications.waset.org/abstracts/search?q=DC%20analysis" title=" DC analysis"> DC analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=transient%20analysis" title=" transient analysis"> transient analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20consumption" title=" power consumption"> power consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=background%20charge%20co-tunneling" title=" background charge co-tunneling"> background charge co-tunneling</a> </p> <a href="https://publications.waset.org/abstracts/17949/replacing-mosfets-with-single-electron-transistors-set-to-reduce-power-consumption-of-an-inverter-circuit" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/17949.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">526</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">29</span> Integration of a Load Switch with DC/DC Buck Converter for Power Distribution in Low Cost Educational Nanosatellite</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Bentoutou%20Houari">Bentoutou Houari</a>, <a href="https://publications.waset.org/abstracts/search?q=Boutte%20Aissa"> Boutte Aissa</a>, <a href="https://publications.waset.org/abstracts/search?q=Belaidi%20El%20Yazid"> Belaidi El Yazid</a>, <a href="https://publications.waset.org/abstracts/search?q=Limam%20Lakhdar"> Limam Lakhdar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The integration of a load switch with a DC/DC buck converter using LM2596 for power distribution in low-cost educational nanosatellites is a technique that aims to efficiently manage the power distribution system in these small spacecraft. The converter is based on the LM2596 regulator and designed to step down the input voltage of +16.8V to +12V, +5V, and +3.3V output, which are suitable for the nanosatellite's various subsystems. The load switch is based on MOSFET and is used to turn on or off the power supply to a particular load and protect the nanosatellite from power surges. A prototype of a +12V DC/DC buck converter with a high side load switch has been realized and tested, which meets our requirements and shows a good efficiency of 89%. In addition, the prototype features a capacitor between the source and gate of the MOSFET, which has effectively reduced the inrush current, demonstrating the effectiveness of this approach in reducing surges of current when the load is connected. The output current and voltage were measured at 0.7A and 11.89V, respectively, making this design suitable for use in low-cost educational nanosatellites. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DC%2FDC%20buck%20converter" title="DC/DC buck converter">DC/DC buck converter</a>, <a href="https://publications.waset.org/abstracts/search?q=load%20switch" title=" load switch"> load switch</a>, <a href="https://publications.waset.org/abstracts/search?q=LM2596" title=" LM2596"> LM2596</a>, <a href="https://publications.waset.org/abstracts/search?q=electrical%20power%20subsystems" title=" electrical power subsystems"> electrical power subsystems</a>, <a href="https://publications.waset.org/abstracts/search?q=nanosatellite" title=" nanosatellite"> nanosatellite</a>, <a href="https://publications.waset.org/abstracts/search?q=inrush%20current" title=" inrush current"> inrush current</a> </p> <a href="https://publications.waset.org/abstracts/166405/integration-of-a-load-switch-with-dcdc-buck-converter-for-power-distribution-in-low-cost-educational-nanosatellite" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/166405.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">101</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">28</span> The DC Behavioural Electrothermal Model of Silicon Carbide Power MOSFETs under SPICE</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Lakrim%20Abderrazak">Lakrim Abderrazak</a>, <a href="https://publications.waset.org/abstracts/search?q=Tahri%20Driss"> Tahri Driss</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a new behavioural electrothermal model of power Silicon Carbide (SiC) MOSFET under SPICE. This model is based on the MOS model level 1 of SPICE, in which phenomena such as Drain Leakage Current IDSS, On-State Resistance RDSon, gate Threshold voltage VGSth, the transconductance (gfs), I-V Characteristics Body diode, temperature-dependent and self-heating are included and represented using behavioural blocks ABM (Analog Behavioural Models) of Spice library. This ultimately makes this model flexible and easily can be integrated into the various Spice -based simulation softwares. The internal junction temperature of the component is calculated on the basis of the thermal model through the electric power dissipated inside and its thermal impedance in the form of the localized Foster canonical network. The model parameters are extracted from manufacturers' data (curves data sheets) using polynomial interpolation with the method of simulated annealing (S A) and weighted least squares (WLS). This model takes into account the various important phenomena within transistor. The effectiveness of the presented model has been verified by Spice simulation results and as well as by data measurement for SiC MOS transistor C2M0025120D CREE (1200V, 90A). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SiC%20power%20MOSFET" title="SiC power MOSFET">SiC power MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=DC%20electro-thermal%20model" title=" DC electro-thermal model"> DC electro-thermal model</a>, <a href="https://publications.waset.org/abstracts/search?q=ABM%20Spice%20library" title=" ABM Spice library"> ABM Spice library</a>, <a href="https://publications.waset.org/abstracts/search?q=SPICE%20modelling" title=" SPICE modelling"> SPICE modelling</a>, <a href="https://publications.waset.org/abstracts/search?q=behavioural%20model" title=" behavioural model"> behavioural model</a>, <a href="https://publications.waset.org/abstracts/search?q=C2M0025120D%20CREE." title=" C2M0025120D CREE."> C2M0025120D CREE.</a> </p> <a href="https://publications.waset.org/abstracts/20601/the-dc-behavioural-electrothermal-model-of-silicon-carbide-power-mosfets-under-spice" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20601.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">581</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">27</span> 3D Simulation and Modeling of Magnetic-Sensitive on n-type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DGMOSFET)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=M.%20Kessi">M. Kessi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=single-gate%20MOSFET" title="single-gate MOSFET">single-gate MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=magnetic%20field" title=" magnetic field"> magnetic field</a>, <a href="https://publications.waset.org/abstracts/search?q=hall%20field" title=" hall field"> hall field</a>, <a href="https://publications.waset.org/abstracts/search?q=Lorentz%20force" title=" Lorentz force"> Lorentz force</a> </p> <a href="https://publications.waset.org/abstracts/142674/3d-simulation-and-modeling-of-magnetic-sensitive-on-n-type-double-gate-metal-oxide-semiconductor-field-effect-transistor-dgmosfet" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/142674.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">181</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">26</span> Application of Carbon Nanotube and Nanowire FET Devices in Future VLSI</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Saurabh%20Chaudhury">Saurabh Chaudhury</a>, <a href="https://publications.waset.org/abstracts/search?q=Sanjeet%20Kumar%20Sinha"> Sanjeet Kumar Sinha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The MOSFET has been the main building block in high performance and low power VLSI chips for the last several decades. Device scaling is fundamental to technological advancements, which allows more devices to be integrated on a single die providing greater functionality per chip. Ultimately, the goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consumes less power. Scaling continued following Moore's law initially and now we see an exponential growth in today's nano scaled chip. However, device scaling to deep nano meter regime leads to exponential increase in leakage currents and excessive heat generation. Moreover, fabrication process variability causing a limitation to further scaling. Researchers believe that with a mix of chemistry, physics, and engineering, nano electronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nano tube (CNT) and nano wires (NW) based FETs have been analyzed and characterized in laboratory and also been demonstrated as prototypes. This work presents an extensive simulation based study and analysis of CNTFET and NW-FET devices and comparison of the results with conventional MOSFET. From this study, we can conclude that these devices have got some excellent properties and favorable characteristics which will definitely lead the future semiconductor devices in post silicon era. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=carbon%20nanotube" title="carbon nanotube">carbon nanotube</a>, <a href="https://publications.waset.org/abstracts/search?q=nanowire%20FET" title=" nanowire FET"> nanowire FET</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=nanoscaled%20devices" title=" nanoscaled devices"> nanoscaled devices</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI" title=" VLSI"> VLSI</a> </p> <a href="https://publications.waset.org/abstracts/15828/application-of-carbon-nanotube-and-nanowire-fet-devices-in-future-vlsi" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/15828.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">411</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">25</span> Proton Irradiation Testing on Commercial Enhancement Mode GaN Power Transistor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=L.%20Boyaci">L. Boyaci</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Two basic equipment of electrical power subsystem of space satellites are Power Conditioning Unit (PCU) and Power Distribution Unit (PDU). Today, the main switching element used in power equipment in satellites is silicon (Si) based radiation-hardened MOSFET. GaNFETs have superior performances over MOSFETs in terms of their conduction and switching characteristics. GaNFET has started to take MOSFET’s place in many applications in industry especially by virtue of its switching performances. If GaNFET can also be used in equipment for space applications, this would be great revolution for future space power subsystem designs. In this study, the effect of proton irradiation on Gallium Nitride based power transistors was investigated. Four commercial enhancement mode GaN power transistors from Efficient Power Conversion Corporation (EPC) are irradiated with 30MeV protons while devices are switching. Flux of 8.2x10⁹ protons/cm²/s is applied for 12.5 seconds to reach ultimate fluence of 10¹¹ protons/cm². Vgs-Ids characteristics are measured and recorded for each device before, during and after irradiation. It was observed that if there would be destructive events. Proton induced permanent damage on devices is not observed. All the devices remained healthy and continued to operate. For two of these devices, further irradiation is applied with same flux for 30 minutes up to a total fluence level of 1.476x10¹³ protons/cm². We observed that GaNFETs are fully functional under this high level of radiation and no destructive events and irreversible failures took place for transistors. Results reveal that irradiated GaNFET in this experiment has radiation tolerance under proton testing and very important candidate for being one of the future power switching element in space. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=enhancement%20mode%20GaN%20power%20transistors" title="enhancement mode GaN power transistors">enhancement mode GaN power transistors</a>, <a href="https://publications.waset.org/abstracts/search?q=proton%20irradiation%20effects" title=" proton irradiation effects"> proton irradiation effects</a>, <a href="https://publications.waset.org/abstracts/search?q=radiation%20tolerance" title=" radiation tolerance"> radiation tolerance</a> </p> <a href="https://publications.waset.org/abstracts/98492/proton-irradiation-testing-on-commercial-enhancement-mode-gan-power-transistor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/98492.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">152</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">24</span> Electronics Thermal Management Driven Design of an IP65-Rated Motor Inverter</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sachin%20Kamble">Sachin Kamble</a>, <a href="https://publications.waset.org/abstracts/search?q=Raghothama%20Anekal"> Raghothama Anekal</a>, <a href="https://publications.waset.org/abstracts/search?q=Shivakumar%20Bhavi"> Shivakumar Bhavi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Thermal management of electronic components packaged inside an IP65 rated enclosure is of prime importance in industrial applications. Electrical enclosure protects the multiple board configurations such as inverter, power, controller board components, busbars, and various power dissipating components from harsh environments. Industrial environments often experience relatively warm ambient conditions, and the electronic components housed in the enclosure dissipate heat, due to which the enclosures and the components require thermal management as well as reduction of internal ambient temperatures. Design of Experiments based thermal simulation approach with MOSFET arrangement, Heat sink design, Enclosure Volume, Copper and Aluminum Spreader, Power density, and Printed Circuit Board (PCB) type were considered to optimize air temperature inside the IP65 enclosure to ensure conducive operating temperature for controller board and electronic components through the different modes of heat transfer viz. conduction, natural convection and radiation using Ansys ICEPAK. MOSFET’s with the parallel arrangement, IP65 enclosure molded heat sink with rectangular fins on both enclosures, specific enclosure volume to satisfy the power density, Copper spreader to conduct heat to the enclosure, optimized power density value and selecting Aluminum clad PCB which improves the heat transfer were the contributors towards achieving a conducive operating temperature inside the IP-65 rated Motor Inverter enclosure. A reduction of 52 ℃ was achieved in internal ambient temperature inside the IP65 enclosure between baseline and final design parameters, which met the operative temperature requirements of the electronic components inside the IP-65 rated Motor Inverter. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ansys%20ICEPAK" title="Ansys ICEPAK">Ansys ICEPAK</a>, <a href="https://publications.waset.org/abstracts/search?q=aluminium%20clad%20PCB" title=" aluminium clad PCB"> aluminium clad PCB</a>, <a href="https://publications.waset.org/abstracts/search?q=IP%2065%20enclosure" title=" IP 65 enclosure"> IP 65 enclosure</a>, <a href="https://publications.waset.org/abstracts/search?q=motor%20inverter" title=" motor inverter"> motor inverter</a>, <a href="https://publications.waset.org/abstracts/search?q=thermal%20simulation" title=" thermal simulation"> thermal simulation</a> </p> <a href="https://publications.waset.org/abstracts/130619/electronics-thermal-management-driven-design-of-an-ip65-rated-motor-inverter" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/130619.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">122</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">23</span> A Low-Voltage Synchronous Command for JFET Rectifiers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=P.%20Monginaud">P. Monginaud</a>, <a href="https://publications.waset.org/abstracts/search?q=J.%20C.%20Baudey"> J. C. Baudey </a> </p> <p class="card-text"><strong>Abstract:</strong></p> The synchronous, low-voltage command for JFET Rectifiers has many applications: indeed, replacing the traditional diodes by these components allows enhanced performances in gain, linearity and phase shift. We introduce here a new bridge, including JFET associated with pull-down, bipolar command systems, and double-purpose logic gates. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=synchronous" title="synchronous">synchronous</a>, <a href="https://publications.waset.org/abstracts/search?q=rectifier" title=" rectifier"> rectifier</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=JFET" title=" JFET"> JFET</a>, <a href="https://publications.waset.org/abstracts/search?q=bipolar%20command%20system" title=" bipolar command system"> bipolar command system</a>, <a href="https://publications.waset.org/abstracts/search?q=push-pull%20circuits" title=" push-pull circuits"> push-pull circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=double-purpose%20logic%20gates" title=" double-purpose logic gates"> double-purpose logic gates</a> </p> <a href="https://publications.waset.org/abstracts/4289/a-low-voltage-synchronous-command-for-jfet-rectifiers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/4289.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">365</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">22</span> A Physically-Based Analytical Model for Reduced Surface Field Laterally Double Diffused MOSFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=M.%20Abouelatta">M. Abouelatta</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Shaker"> A. Shaker</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20El-Banna"> M. El-Banna</a>, <a href="https://publications.waset.org/abstracts/search?q=G.%20T.%20Sayah"> G. T. Sayah</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Gontrand"> C. Gontrand</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Zekry"> A. Zekry</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a methodology for physically modeling the intrinsic MOS part and the drift region of the n-channel Laterally Double-diffused MOSFET (LDMOS) is presented. The basic physical effects like velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are taken into consideration. The analytical model is implemented using MATLAB. A comparison of the simulations from technology computer aided design (TCAD) and that from the proposed analytical model, at room temperature, shows a satisfactory accuracy which is less than 5% for the whole voltage domain. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=LDMOS" title="LDMOS">LDMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=MATLAB" title=" MATLAB"> MATLAB</a>, <a href="https://publications.waset.org/abstracts/search?q=RESURF" title=" RESURF"> RESURF</a>, <a href="https://publications.waset.org/abstracts/search?q=modeling" title=" modeling"> modeling</a>, <a href="https://publications.waset.org/abstracts/search?q=TCAD" title=" TCAD"> TCAD</a> </p> <a href="https://publications.waset.org/abstracts/73261/a-physically-based-analytical-model-for-reduced-surface-field-laterally-double-diffused-mosfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/73261.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">199</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">21</span> Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100 nm Technologies</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zina%20Saheb">Zina Saheb</a>, <a href="https://publications.waset.org/abstracts/search?q=Ezz%20El-Masry"> Ezz El-Masry</a> </p> <p class="card-text"><strong>Abstract:</strong></p> As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20transistor" title="CMOS transistor">CMOS transistor</a>, <a href="https://publications.waset.org/abstracts/search?q=direct-tunneling%20current" title=" direct-tunneling current"> direct-tunneling current</a>, <a href="https://publications.waset.org/abstracts/search?q=floating-gate" title=" floating-gate"> floating-gate</a>, <a href="https://publications.waset.org/abstracts/search?q=gate-leakage%20current" title=" gate-leakage current"> gate-leakage current</a>, <a href="https://publications.waset.org/abstracts/search?q=simulation%20model" title=" simulation model"> simulation model</a> </p> <a href="https://publications.waset.org/abstracts/30655/practical-simulation-model-of-floating-gate-mos-transistor-in-sub-100-nm-technologies" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/30655.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">529</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">20</span> A Single Switch High Step-Up DC/DC Converter with Zero Current Switching Condition</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rahil%20Samani">Rahil Samani</a>, <a href="https://publications.waset.org/abstracts/search?q=Saeed%20Soleimani"> Saeed Soleimani</a>, <a href="https://publications.waset.org/abstracts/search?q=Ehsan%20Adib"> Ehsan Adib</a>, <a href="https://publications.waset.org/abstracts/search?q=Majid%20Pahlevani"> Majid Pahlevani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents an inverting high step-up DC/DC converter. Basically, this high step-up DC/DC converter is an appealing interface for solar applications. The proposed topology takes advantage of using coupled inductors. Due to the leakage inductances of these coupled inductors, the power MOSFET has the zero current switching (ZCS) condition, which results in decreased switching losses. This will substantially improve the overall efficiency of the power converter. Furthermore, employing coupled inductors has led to a higher voltage gain. Theoretical analysis and experimental results of a 100W 20V/220V prototype are presented to verify the superior performance of the proposed DC/DC converter. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=coupled%20inductors" title="coupled inductors">coupled inductors</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20step-up%20DC%2FDC%20converter" title=" high step-up DC/DC converter"> high step-up DC/DC converter</a>, <a href="https://publications.waset.org/abstracts/search?q=zero-current%20switching" title=" zero-current switching"> zero-current switching</a>, <a href="https://publications.waset.org/abstracts/search?q=Cuk%20converter" title=" Cuk converter"> Cuk converter</a>, <a href="https://publications.waset.org/abstracts/search?q=SEPIC%20converter" title=" SEPIC converter"> SEPIC converter</a> </p> <a href="https://publications.waset.org/abstracts/107674/a-single-switch-high-step-up-dcdc-converter-with-zero-current-switching-condition" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/107674.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">719</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">19</span> AC Voltage Regulators Using Single Phase Matrix Converter</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nagaraju%20Jarugu">Nagaraju Jarugu</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20R.%20Narendra"> B. R. Narendra</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper focused on boost rectification by Single Phase Matrix Converter with fewer numbers of switches. The conventional matrix converter consists of 4 bidirectional switches, i.e. 8 set of IGBT/MOSFET with anti-parallel diodes. In this proposed matrix converter, only six switches are used. The switch commutation arrangements are also carried out in this work. The SPMC topology has many advantages as a minimal passive device use. It is very flexible and it can be used as a lot of converters. The gate pulses to the switches are provided by the PWM techniques. The duty ratio of the switches based on Pulse Width Modulation (PWM) technique was used to produce the output waveform of the circuit, simply by turning ON and OFF the switches. The simulation results using MATLAB/Simulink were provided to validate the feasibility of this proposed method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=single%20phase%20matrix%20converter" title="single phase matrix converter">single phase matrix converter</a>, <a href="https://publications.waset.org/abstracts/search?q=reduced%20switches" title=" reduced switches"> reduced switches</a>, <a href="https://publications.waset.org/abstracts/search?q=AC%20voltage%20regulators" title=" AC voltage regulators"> AC voltage regulators</a>, <a href="https://publications.waset.org/abstracts/search?q=boost%20rectifier%20operation" title=" boost rectifier operation"> boost rectifier operation</a> </p> <a href="https://publications.waset.org/abstracts/31741/ac-voltage-regulators-using-single-phase-matrix-converter" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/31741.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1188</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">18</span> The Design of PFM Mode DC-DC Converter with DT-CMOS Switch</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jae-Chang%20Kwak">Jae-Chang Kwak</a>, <a href="https://publications.waset.org/abstracts/search?q=Yong-Seo%20Koo"> Yong-Seo Koo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DT-CMOS" title="DT-CMOS">DT-CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=PMIC" title=" PMIC"> PMIC</a>, <a href="https://publications.waset.org/abstracts/search?q=PFM" title=" PFM"> PFM</a>, <a href="https://publications.waset.org/abstracts/search?q=DC-DC%20converter" title=" DC-DC converter"> DC-DC converter</a> </p> <a href="https://publications.waset.org/abstracts/11839/the-design-of-pfm-mode-dc-dc-converter-with-dt-cmos-switch" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/11839.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">451</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">17</span> Novel Approach to Design of a Class-EJ Power Amplifier Using High Power Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=F.%20Rahmani">F. Rahmani</a>, <a href="https://publications.waset.org/abstracts/search?q=F.%20Razaghian"> F. Razaghian</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20R.%20Kashaninia"> A. R. Kashaninia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=power%20amplifier%20%28PA%29" title="power amplifier (PA)">power amplifier (PA)</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20power" title=" high power"> high power</a>, <a href="https://publications.waset.org/abstracts/search?q=class-J%20and%20%20%20class-E" title=" class-J and class-E"> class-J and class-E</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20efficiency" title=" high efficiency "> high efficiency </a> </p> <a href="https://publications.waset.org/abstracts/25917/novel-approach-to-design-of-a-class-ej-power-amplifier-using-high-power-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25917.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">492</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">16</span> GE as a Channel Material in P-Type MOSFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Slimani">S. Slimani</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Djellouli"> B. Djellouli</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials like Ge is a very promising material due to its high mobility and is being considered to replace Si in the channel to achieve higher drive currents and switching speeds .Various approaches to circumvent the scaling limits to benchmark the performance of nanoscale MOSFETS with different channel materials, the optimized structure is simulated within nextnano in order to highlight the quantum effects on DG MOSFETs when Si is replaced by Ge and SiO2 is replaced by ZrO2 and HfO2as the gate dielectric. The results have shown that Ge MOSFET have the highest mobility and high permittivity oxides serve to maintain high drive current. The simulations show significant improvements compared with DGMOSFET using SiO2 gate dielectric and Si channel. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=high%20mobility" title="high mobility">high mobility</a>, <a href="https://publications.waset.org/abstracts/search?q=high-k" title=" high-k"> high-k</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20effects" title=" quantum effects"> quantum effects</a>, <a href="https://publications.waset.org/abstracts/search?q=SOI-DGMOSFET" title=" SOI-DGMOSFET"> SOI-DGMOSFET</a> </p> <a href="https://publications.waset.org/abstracts/33935/ge-as-a-channel-material-in-p-type-mosfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/33935.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">367</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">15</span> Characterization of the MOSkin Dosimeter for Accumulated Dose Assessment in Computed Tomography</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Lenon%20M.%20Pereira">Lenon M. Pereira</a>, <a href="https://publications.waset.org/abstracts/search?q=Helen%20J.%20Khoury"> Helen J. Khoury</a>, <a href="https://publications.waset.org/abstracts/search?q=Marcos%20E.%20A.%20Andrade"> Marcos E. A. Andrade</a>, <a href="https://publications.waset.org/abstracts/search?q=Dean%20L.%20Cutajar"> Dean L. Cutajar</a>, <a href="https://publications.waset.org/abstracts/search?q=Vinicius%20S.%20M.%20Barros"> Vinicius S. M. Barros</a>, <a href="https://publications.waset.org/abstracts/search?q=Anatoly%20B.%20Rozenfeld"> Anatoly B. Rozenfeld</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the increase of beam widths and the advent of multiple-slice and helical scanners, concerns related to the current dose measurement protocols and instrumentation in computed tomography (CT) have arisen. The current methodology of dose evaluation, which is based on the measurement of the integral of a single slice dose profile using a 100 mm long cylinder ionization chamber (Ca,100 and CPPMA, 100), has been shown to be inadequate for wide beams as it does not collect enough of the scatter-tails to make an accurate measurement. In addition, a long ionization chamber does not offer a good representation of the dose profile when tube current modulation is used. An alternative approach has been suggested by translating smaller detectors through the beam plane and assessing the accumulated dose trough the integral of the dose profile, which can be done for any arbitrary length in phantoms or in the air. For this purpose, a MOSFET dosimeter of small dosimetric volume was used. One of its recently designed versions is known as the MOSkin, which is developed by the Centre for Medical Radiation Physics at the University of Wollongong, and measures the radiation dose at a water equivalent depth of 0.07 mm, allowing the evaluation of skin dose when placed at the surface, or internal point doses when placed within a phantom. Thus, the aim of this research was to characterize the response of the MOSkin dosimeter for X-ray CT beams and to evaluate its application for the accumulated dose assessment. Initially, tests using an industrial x-ray unit were carried out at the Laboratory of Ionization Radiation Metrology (LMRI) of Federal University of Pernambuco, in order to investigate the sensitivity, energy dependence, angular dependence, and reproducibility of the dose response for the device for the standard radiation qualities RQT 8, RQT 9 and RQT 10. Finally, the MOSkin was used for the accumulated dose evaluation of scans using a Philips Brilliance 6 CT unit, with comparisons made between the CPPMA,100 value assessed with a pencil ionization chamber (PTW Freiburg TW 30009). Both dosimeters were placed in the center of a PMMA head phantom (diameter of 16 cm) and exposed in the axial mode with collimation of 9 mm, 250 mAs and 120 kV. The results have shown that the MOSkin response was linear with doses in the CT range and reproducible (98.52%). The sensitivity for a single MOSkin in mV/cGy was as follows: 9.208, 7.691 and 6.723 for the RQT 8, RQT 9 and RQT 10 beams qualities respectively. The energy dependence varied up to a factor of ±1.19 among those energies and angular dependence was not greater than 7.78% within the angle range from 0 to 90 degrees. The accumulated dose and the CPMMA, 100 value were 3,97 and 3,79 cGy respectively, which were statistically equivalent within the 95% confidence level. The MOSkin was shown to be a good alternative for CT dose profile measurements and more than adequate to provide accumulated dose assessments for CT procedures. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=computed%20tomography%20dosimetry" title="computed tomography dosimetry">computed tomography dosimetry</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSkin" title=" MOSkin"> MOSkin</a>, <a href="https://publications.waset.org/abstracts/search?q=semiconductor%20dosimetry" title=" semiconductor dosimetry"> semiconductor dosimetry</a> </p> <a href="https://publications.waset.org/abstracts/50043/characterization-of-the-moskin-dosimeter-for-accumulated-dose-assessment-in-computed-tomography" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/50043.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">311</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=PDSOI%20MOSFET&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=PDSOI%20MOSFET&page=2" rel="next">&rsaquo;</a></li> </ul> </div> </main> <footer> <div id="infolinks" class="pt-3 pb-2"> <div class="container"> <div style="background-color:#f5f5f5;" class="p-3"> <div class="row"> <div class="col-md-2"> <ul class="list-unstyled"> About <li><a href="https://waset.org/page/support">About Us</a></li> <li><a href="https://waset.org/page/support#legal-information">Legal</a></li> <li><a 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