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id="toc-Types" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Types"> <div class="vector-toc-text"> 2 Types </div> </a> <ul id="toc-Types-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_cell" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Memory_cell"> <div class="vector-toc-text"> 3 Memory cell </div> </a> <ul id="toc-Memory_cell-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Addressing" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Addressing"> <div class="vector-toc-text"> 4 Addressing </div> </a> <ul id="toc-Addressing-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_hierarchy" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Memory_hierarchy"> <div class="vector-toc-text"> 5 Memory hierarchy </div> </a> <ul id="toc-Memory_hierarchy-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Other_uses_of_RAM" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Other_uses_of_RAM"> <div class="vector-toc-text"> 6 Other uses of RAM </div> </a> <button aria-controls="toc-Other_uses_of_RAM-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Other uses of RAM subsection </button> <ul id="toc-Other_uses_of_RAM-sublist" class="vector-toc-list"> <li id="toc-Virtual_memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Virtual_memory"> <div class="vector-toc-text"> 6.1 Virtual memory </div> </a> <ul id="toc-Virtual_memory-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-RAM_disk" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#RAM_disk"> <div class="vector-toc-text"> 6.2 RAM disk </div> </a> <ul id="toc-RAM_disk-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Shadow_RAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Shadow_RAM"> <div class="vector-toc-text"> 6.3 Shadow RAM </div> </a> <ul id="toc-Shadow_RAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Memory_wall" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Memory_wall"> <div class="vector-toc-text"> 7 Memory wall </div> </a> <ul id="toc-Memory_wall-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Timeline" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Timeline"> <div class="vector-toc-text"> 8 Timeline </div> </a> <button aria-controls="toc-Timeline-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Timeline subsection </button> <ul id="toc-Timeline-sublist" class="vector-toc-list"> <li id="toc-SRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SRAM"> <div class="vector-toc-text"> 8.1 SRAM </div> </a> <ul id="toc-SRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DRAM"> <div class="vector-toc-text"> 8.2 DRAM </div> </a> <ul id="toc-DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SDRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SDRAM"> <div class="vector-toc-text"> 8.3 SDRAM </div> </a> <ul id="toc-SDRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SGRAM_and_HBM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SGRAM_and_HBM"> <div class="vector-toc-text"> 8.4 SGRAM and HBM </div> </a> <ul id="toc-SGRAM_and_HBM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 9 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 10 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 11 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" > Toggle the table of contents </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading">Random-access memory</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 104 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-104" aria-hidden="true" > 104 languages </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-af mw-list-item"><a href="https://af.wikipedia.org/wiki/Ewetoeganklike_geheue" title="Ewetoeganklike geheue – Afrikaans" lang="af" hreflang="af" data-title="Ewetoeganklike geheue" data-language-autonym="Afrikaans" data-language-local-name="Afrikaans" class="interlanguage-link-target">Afrikaans</a></li><li class="interlanguage-link interwiki-als mw-list-item"><a href="https://als.wikipedia.org/wiki/Random-Access_Memory" title="Random-Access Memory – Alemannic" lang="gsw" hreflang="gsw" data-title="Random-Access Memory" data-language-autonym="Alemannisch" data-language-local-name="Alemannic" class="interlanguage-link-target">Alemannisch</a></li><li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B0%D8%A7%D9%83%D8%B1%D8%A9_%D8%A7%D9%84%D9%88%D8%B5%D9%88%D9%84_%D8%A7%D9%84%D8%B9%D8%B4%D9%88%D8%A7%D8%A6%D9%8A" title="ذاكرة الوصول العشوائي – Arabic" lang="ar" hreflang="ar" data-title="ذاكرة الوصول العشوائي" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target">العربية</a></li><li class="interlanguage-link interwiki-an mw-list-item"><a href="https://an.wikipedia.org/wiki/RAM" title="RAM – Aragonese" lang="an" hreflang="an" data-title="RAM" data-language-autonym="Aragonés" data-language-local-name="Aragonese" class="interlanguage-link-target">Aragonés</a></li><li class="interlanguage-link interwiki-ast mw-list-item"><a href="https://ast.wikipedia.org/wiki/Memoria_d%27accesu_aleatoriu" title="Memoria d'accesu aleatoriu – Asturian" lang="ast" hreflang="ast" data-title="Memoria d'accesu aleatoriu" data-language-autonym="Asturianu" data-language-local-name="Asturian" class="interlanguage-link-target">Asturianu</a></li><li class="interlanguage-link interwiki-awa mw-list-item"><a href="https://awa.wikipedia.org/wiki/%E0%A4%B0%E0%A5%88%E0%A4%AE" title="रैम – Awadhi" lang="awa" hreflang="awa" data-title="रैम" data-language-autonym="अवधी" data-language-local-name="Awadhi" class="interlanguage-link-target">अवधी</a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/Operativ_yadda%C5%9F_qur%C4%9Fusu" title="Operativ yaddaş qurğusu – Azerbaijani" lang="az" hreflang="az" data-title="Operativ yaddaş qurğusu" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target">Azərbaycanca</a></li><li class="interlanguage-link interwiki-azb mw-list-item"><a href="https://azb.wikipedia.org/wiki/%D8%B1%D9%85_(%D8%A8%DB%8C%D9%84%DA%AF%DB%8C%E2%80%8C%D8%B3%D8%A7%DB%8C%D8%A7%D8%B1)" title="رم (بیلگی‌سایار) – South Azerbaijani" lang="azb" hreflang="azb" data-title="رم (بیلگی‌سایار)" data-language-autonym="تۆرکجه" data-language-local-name="South Azerbaijani" class="interlanguage-link-target">تۆرکجه</a></li><li class="interlanguage-link interwiki-bn mw-list-item"><a href="https://bn.wikipedia.org/wiki/%E0%A6%B0%E2%80%8D%E0%A7%8D%E0%A6%AF%E0%A6%BE%E0%A6%A8%E0%A7%8D%E0%A6%A1%E0%A6%AE_%E0%A6%85%E0%A7%8D%E0%A6%AF%E0%A6%BE%E0%A6%95%E0%A7%8D%E0%A6%B8%E0%A7%87%E0%A6%B8_%E0%A6%AE%E0%A7%87%E0%A6%AE%E0%A7%8B%E0%A6%B0%E0%A6%BF" title="র‍্যান্ডম অ্যাক্সেস মেমোরি – Bangla" lang="bn" hreflang="bn" data-title="র‍্যান্ডম অ্যাক্সেস মেমোরি" data-language-autonym="বাংলা" data-language-local-name="Bangla" class="interlanguage-link-target">বাংলা</a></li><li class="interlanguage-link interwiki-zh-min-nan mw-list-item"><a href="https://zh-min-nan.wikipedia.org/wiki/RAM" title="RAM – Minnan" lang="nan" hreflang="nan" data-title="RAM" data-language-autonym="閩南語 / Bân-lâm-gú" data-language-local-name="Minnan" class="interlanguage-link-target">閩南語 / Bân-lâm-gú</a></li><li class="interlanguage-link interwiki-be mw-list-item"><a href="https://be.wikipedia.org/wiki/%D0%9F%D0%B0%D0%BC%D1%8F%D1%86%D1%8C_%D0%B7_%D0%B0%D0%B4%D0%B2%D0%BE%D0%BB%D1%8C%D0%BD%D1%8B%D0%BC_%D0%B4%D0%BE%D1%81%D1%82%D1%83%D0%BF%D0%B0%D0%BC" title="Памяць з адвольным доступам – Belarusian" lang="be" hreflang="be" data-title="Памяць з адвольным доступам" data-language-autonym="Беларуская" data-language-local-name="Belarusian" class="interlanguage-link-target">Беларуская</a></li><li class="interlanguage-link interwiki-be-x-old mw-list-item"><a href="https://be-tarask.wikipedia.org/wiki/%D0%9F%D0%B0%D0%BC%D1%8F%D1%86%D1%8C_%D0%B7_%D0%B0%D0%B4%D0%B2%D0%BE%D0%BB%D1%8C%D0%BD%D1%8B%D0%BC_%D0%B4%D0%BE%D1%81%D1%82%D1%83%D0%BF%D0%B0%D0%BC" title="Памяць з адвольным доступам – Belarusian (Taraškievica orthography)" lang="be-tarask" hreflang="be-tarask" data-title="Памяць з адвольным доступам" data-language-autonym="Беларуская (тарашкевіца)" data-language-local-name="Belarusian (Taraškievica orthography)" class="interlanguage-link-target">Беларуская (тарашкевіца)</a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%9F%D0%B0%D0%BC%D0%B5%D1%82_%D1%81_%D0%BF%D1%80%D0%BE%D0%B8%D0%B7%D0%B2%D0%BE%D0%BB%D0%B5%D0%BD_%D0%B4%D0%BE%D1%81%D1%82%D1%8A%D0%BF" title="Памет с произволен достъп – Bulgarian" lang="bg" hreflang="bg" data-title="Памет с произволен достъп" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target">Български</a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/RAM" title="RAM – Bosnian" lang="bs" hreflang="bs" data-title="RAM" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target">Bosanski</a></li><li class="interlanguage-link interwiki-br mw-list-item"><a href="https://br.wikipedia.org/wiki/Memor_bev" title="Memor bev – Breton" lang="br" hreflang="br" data-title="Memor bev" data-language-autonym="Brezhoneg" data-language-local-name="Breton" class="interlanguage-link-target">Brezhoneg</a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Mem%C3%B2ria_d%27acc%C3%A9s_aleatori" title="Memòria d'accés aleatori – Catalan" lang="ca" hreflang="ca" data-title="Memòria d'accés aleatori" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target">Català</a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/RAM" title="RAM – Czech" lang="cs" hreflang="cs" data-title="RAM" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target">Čeština</a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/RAM" title="RAM – Danish" lang="da" hreflang="da" data-title="RAM" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target">Dansk</a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Random-Access_Memory" title="Random-Access Memory – German" lang="de" hreflang="de" data-title="Random-Access Memory" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target">Deutsch</a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Muutm%C3%A4lu" title="Muutmälu – Estonian" lang="et" hreflang="et" data-title="Muutmälu" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target">Eesti</a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/%CE%9C%CE%BD%CE%AE%CE%BC%CE%B7_%CF%84%CF%85%CF%87%CE%B1%CE%AF%CE%B1%CF%82_%CF%80%CF%81%CE%BF%CF%83%CF%80%CE%AD%CE%BB%CE%B1%CF%83%CE%B7%CF%82" title="Μνήμη τυχαίας προσπέλασης – Greek" lang="el" hreflang="el" data-title="Μνήμη τυχαίας προσπέλασης" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target">Ελληνικά</a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Memoria_de_acceso_aleatorio" title="Memoria de acceso aleatorio – Spanish" lang="es" hreflang="es" data-title="Memoria de acceso aleatorio" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target">Español</a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/%C4%88efmemoro" title="Ĉefmemoro – Esperanto" lang="eo" hreflang="eo" data-title="Ĉefmemoro" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target">Esperanto</a></li><li class="interlanguage-link interwiki-ext mw-list-item"><a href="https://ext.wikipedia.org/wiki/RAM" title="RAM – Extremaduran" lang="ext" hreflang="ext" data-title="RAM" data-language-autonym="Estremeñu" data-language-local-name="Extremaduran" class="interlanguage-link-target">Estremeñu</a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/Random_Access_Memory" title="Random Access Memory – Basque" lang="eu" hreflang="eu" data-title="Random Access Memory" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target">Euskara</a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%AD%D8%A7%D9%81%D8%B8%D9%87_%D8%AF%D8%B3%D8%AA%D8%B1%D8%B3%DB%8C_%D8%AA%D8%B5%D8%A7%D8%AF%D9%81%DB%8C" title="حافظه دسترسی تصادفی – Persian" lang="fa" hreflang="fa" data-title="حافظه دسترسی تصادفی" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target">فارسی</a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/M%C3%A9moire_vive" title="Mémoire vive – French" lang="fr" hreflang="fr" data-title="Mémoire vive" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target">Français</a></li><li class="interlanguage-link interwiki-fy mw-list-item"><a href="https://fy.wikipedia.org/wiki/Wurk%C3%BBnth%C3%A2ld" title="Wurkûnthâld – Western Frisian" lang="fy" hreflang="fy" data-title="Wurkûnthâld" data-language-autonym="Frysk" data-language-local-name="Western Frisian" class="interlanguage-link-target">Frysk</a></li><li class="interlanguage-link interwiki-fur mw-list-item"><a href="https://fur.wikipedia.org/wiki/RAM" title="RAM – Friulian" lang="fur" hreflang="fur" data-title="RAM" data-language-autonym="Furlan" data-language-local-name="Friulian" class="interlanguage-link-target">Furlan</a></li><li class="interlanguage-link interwiki-ga mw-list-item"><a href="https://ga.wikipedia.org/wiki/Cuimhne_randamrochtana" title="Cuimhne randamrochtana – Irish" lang="ga" hreflang="ga" data-title="Cuimhne randamrochtana" data-language-autonym="Gaeilge" data-language-local-name="Irish" class="interlanguage-link-target">Gaeilge</a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/Memoria_de_acceso_aleatorio" title="Memoria de acceso aleatorio – Galician" lang="gl" hreflang="gl" data-title="Memoria de acceso aleatorio" data-language-autonym="Galego" data-language-local-name="Galician" class="interlanguage-link-target">Galego</a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%9E%9C%EB%8D%A4_%EC%95%A1%EC%84%B8%EC%8A%A4_%EB%A9%94%EB%AA%A8%EB%A6%AC" title="랜덤 액세스 메모리 – Korean" lang="ko" hreflang="ko" data-title="랜덤 액세스 메모리" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target">한국어</a></li><li class="interlanguage-link interwiki-ha mw-list-item"><a href="https://ha.wikipedia.org/wiki/RAM" title="RAM – Hausa" lang="ha" hreflang="ha" data-title="RAM" data-language-autonym="Hausa" data-language-local-name="Hausa" class="interlanguage-link-target">Hausa</a></li><li class="interlanguage-link interwiki-hy mw-list-item"><a href="https://hy.wikipedia.org/wiki/%D5%95%D5%BA%D5%A5%D6%80%D5%A1%D5%BF%D5%AB%D5%BE_%D5%B0%D5%AB%D5%B7%D5%B8%D5%B2%D5%B8%D6%82%D5%A9%D5%B5%D5%B8%D6%82%D5%B6" title="Օպերատիվ հիշողություն – Armenian" lang="hy" hreflang="hy" data-title="Օպերատիվ հիշողություն" data-language-autonym="Հայերեն" data-language-local-name="Armenian" class="interlanguage-link-target">Հայերեն</a></li><li class="interlanguage-link interwiki-hi mw-list-item"><a href="https://hi.wikipedia.org/wiki/%E0%A4%B0%E0%A5%88%E0%A4%82%E0%A4%A1%E0%A4%AE_%E0%A4%8F%E0%A4%95%E0%A5%8D%E0%A4%B8%E0%A5%88%E0%A4%B8_%E0%A4%AE%E0%A5%88%E0%A4%AE%E0%A5%8B%E0%A4%B0%E0%A5%80" title="रैंडम एक्सैस मैमोरी – Hindi" lang="hi" hreflang="hi" data-title="रैंडम एक्सैस मैमोरी" data-language-autonym="हिन्दी" data-language-local-name="Hindi" class="interlanguage-link-target">हिन्दी</a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/RAM" title="RAM – Croatian" lang="hr" hreflang="hr" data-title="RAM" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target">Hrvatski</a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Memori_akses_acak" title="Memori akses acak – Indonesian" lang="id" hreflang="id" data-title="Memori akses acak" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target">Bahasa Indonesia</a></li><li class="interlanguage-link interwiki-is mw-list-item"><a href="https://is.wikipedia.org/wiki/RAM" title="RAM – Icelandic" lang="is" hreflang="is" data-title="RAM" data-language-autonym="Íslenska" data-language-local-name="Icelandic" class="interlanguage-link-target">Íslenska</a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/RAM" title="RAM – Italian" lang="it" hreflang="it" data-title="RAM" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target">Italiano</a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%96%D7%99%D7%9B%D7%A8%D7%95%D7%9F_%D7%92%D7%99%D7%A9%D7%94_%D7%90%D7%A7%D7%A8%D7%90%D7%99%D7%AA" title="זיכרון גישה אקראית – Hebrew" lang="he" hreflang="he" data-title="זיכרון גישה אקראית" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target">עברית</a></li><li class="interlanguage-link interwiki-jv mw-list-item"><a href="https://jv.wikipedia.org/wiki/RAM" title="RAM – Javanese" lang="jv" hreflang="jv" data-title="RAM" data-language-autonym="Jawa" data-language-local-name="Javanese" class="interlanguage-link-target">Jawa</a></li><li class="interlanguage-link interwiki-ka mw-list-item"><a href="https://ka.wikipedia.org/wiki/%E1%83%9D%E1%83%9E%E1%83%94%E1%83%A0%E1%83%90%E1%83%A2%E1%83%98%E1%83%A3%E1%83%9A%E1%83%98_%E1%83%9B%E1%83%94%E1%83%AE%E1%83%A1%E1%83%98%E1%83%94%E1%83%A0%E1%83%94%E1%83%91%E1%83%90" title="ოპერატიული მეხსიერება – Georgian" lang="ka" hreflang="ka" data-title="ოპერატიული მეხსიერება" data-language-autonym="ქართული" data-language-local-name="Georgian" class="interlanguage-link-target">ქართული</a></li><li class="interlanguage-link interwiki-kk mw-list-item"><a href="https://kk.wikipedia.org/wiki/%D0%96%D0%B5%D0%B4%D0%B5%D0%BB_%D0%B6%D0%B0%D0%B4%D1%82%D0%B0%D1%83_%D2%9B%D2%B1%D1%80%D1%8B%D0%BB%D2%93%D1%8B%D1%81%D1%8B" title="Жедел жадтау құрылғысы – Kazakh" lang="kk" hreflang="kk" data-title="Жедел жадтау құрылғысы" data-language-autonym="Қазақша" data-language-local-name="Kazakh" class="interlanguage-link-target">Қазақша</a></li><li class="interlanguage-link interwiki-sw mw-list-item"><a href="https://sw.wikipedia.org/wiki/KUFINA" title="KUFINA – Swahili" lang="sw" hreflang="sw" data-title="KUFINA" data-language-autonym="Kiswahili" data-language-local-name="Swahili" class="interlanguage-link-target">Kiswahili</a></li><li class="interlanguage-link interwiki-ku mw-list-item"><a href="https://ku.wikipedia.org/wiki/RAM" title="RAM – Kurdish" lang="ku" hreflang="ku" data-title="RAM" data-language-autonym="Kurdî" data-language-local-name="Kurdish" class="interlanguage-link-target">Kurdî</a></li><li class="interlanguage-link interwiki-ky mw-list-item"><a href="https://ky.wikipedia.org/wiki/%D0%A2%D1%83%D1%88%D0%BA%D0%B5%D0%BB%D0%B4%D0%B8_%D0%B6%D0%B5%D1%82%D0%BA%D0%B8_%D1%8D%D1%81%D0%B8" title="Тушкелди жетки эси – Kyrgyz" lang="ky" hreflang="ky" data-title="Тушкелди жетки эси" data-language-autonym="Кыргызча" data-language-local-name="Kyrgyz" class="interlanguage-link-target">Кыргызча</a></li><li class="interlanguage-link interwiki-la mw-list-item"><a href="https://la.wikipedia.org/wiki/Memoria_volatilis" title="Memoria volatilis – Latin" lang="la" hreflang="la" data-title="Memoria volatilis" data-language-autonym="Latina" data-language-local-name="Latin" class="interlanguage-link-target">Latina</a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/Br%C4%ABvpiek%C4%BCuves_atmi%C5%86a" title="Brīvpiekļuves atmiņa – Latvian" lang="lv" hreflang="lv" data-title="Brīvpiekļuves atmiņa" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target">Latviešu</a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/Laisvosios_prieigos_atmintis" title="Laisvosios prieigos atmintis – Lithuanian" lang="lt" hreflang="lt" data-title="Laisvosios prieigos atmintis" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target">Lietuvių</a></li><li class="interlanguage-link interwiki-lmo mw-list-item"><a href="https://lmo.wikipedia.org/wiki/RAM" title="RAM – Lombard" lang="lmo" hreflang="lmo" data-title="RAM" data-language-autonym="Lombard" data-language-local-name="Lombard" class="interlanguage-link-target">Lombard</a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/RAM" title="RAM – Hungarian" lang="hu" hreflang="hu" data-title="RAM" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target">Magyar</a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/RAM_%D0%BC%D0%B5%D0%BC%D0%BE%D1%80%D0%B8%D1%98%D0%B0" title="RAM меморија – Macedonian" lang="mk" hreflang="mk" data-title="RAM меморија" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target">Македонски</a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%B1%E0%B4%BE%E0%B5%BB%E0%B4%A1%E0%B4%82_%E0%B4%86%E0%B4%95%E0%B5%8D%E0%B4%B8%E0%B4%B8%E0%B5%8D_%E0%B4%AE%E0%B5%86%E0%B4%AE%E0%B5%8D%E0%B4%AE%E0%B4%B1%E0%B4%BF" title="റാൻഡം ആക്സസ് മെമ്മറി – Malayalam" lang="ml" hreflang="ml" data-title="റാൻഡം ആക്സസ് മെമ്മറി" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target">മലയാളം</a></li><li class="interlanguage-link interwiki-mr mw-list-item"><a href="https://mr.wikipedia.org/wiki/%E0%A4%B0%E0%A5%85%E0%A4%AE" title="रॅम – Marathi" lang="mr" hreflang="mr" data-title="रॅम" data-language-autonym="मराठी" data-language-local-name="Marathi" class="interlanguage-link-target">मराठी</a></li><li class="interlanguage-link interwiki-xmf mw-list-item"><a href="https://xmf.wikipedia.org/wiki/%E1%83%9D%E1%83%9E%E1%83%94%E1%83%A0%E1%83%90%E1%83%A2%E1%83%98%E1%83%A3%E1%83%9A%E1%83%98_%E1%83%A8%E1%83%95%E1%83%94%E1%83%9C%E1%83%90" title="ოპერატიული შვენა – Mingrelian" lang="xmf" hreflang="xmf" data-title="ოპერატიული შვენა" data-language-autonym="მარგალური" data-language-local-name="Mingrelian" class="interlanguage-link-target">მარგალური</a></li><li class="interlanguage-link interwiki-arz mw-list-item"><a href="https://arz.wikipedia.org/wiki/%D8%B1%D8%A7%D9%85" title="رام – Egyptian Arabic" lang="arz" hreflang="arz" data-title="رام" data-language-autonym="مصرى" data-language-local-name="Egyptian Arabic" class="interlanguage-link-target">مصرى</a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/Ingatan_capaian_rawak" title="Ingatan capaian rawak – Malay" lang="ms" hreflang="ms" data-title="Ingatan capaian rawak" data-language-autonym="Bahasa Melayu" data-language-local-name="Malay" class="interlanguage-link-target">Bahasa Melayu</a></li><li class="interlanguage-link interwiki-mn mw-list-item"><a href="https://mn.wikipedia.org/wiki/%D0%A8%D1%83%D1%83%D1%80%D1%85%D0%B0%D0%B9_%D1%81%D0%B0%D0%BD%D0%B0%D1%85_%D0%BE%D0%B9" title="Шуурхай санах ой – Mongolian" lang="mn" hreflang="mn" data-title="Шуурхай санах ой" data-language-autonym="Монгол" data-language-local-name="Mongolian" class="interlanguage-link-target">Монгол</a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Random-access_memory" title="Random-access memory – Dutch" lang="nl" hreflang="nl" data-title="Random-access memory" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target">Nederlands</a></li><li class="interlanguage-link interwiki-ne mw-list-item"><a href="https://ne.wikipedia.org/wiki/%E0%A4%B0%E0%A5%8D%E2%80%8D%E0%A4%AF%E0%A4%BE%E0%A4%A8%E0%A5%8D%E0%A4%A1%E0%A4%AE_%E0%A4%8F%E0%A4%95%E0%A5%8D%E0%A4%B8%E0%A5%87%E0%A4%B8_%E0%A4%AE%E0%A5%87%E0%A4%AE%E0%A5%8B%E0%A4%B0%E0%A5%80" title="र्‍यान्डम एक्सेस मेमोरी – Nepali" lang="ne" hreflang="ne" data-title="र्‍यान्डम एक्सेस मेमोरी" data-language-autonym="नेपाली" data-language-local-name="Nepali" class="interlanguage-link-target">नेपाली</a></li><li class="interlanguage-link interwiki-new mw-list-item"><a href="https://new.wikipedia.org/wiki/%E0%A4%B0%E0%A4%BE%E0%A4%AE%E0%A5%8D_(%E0%A4%B8%E0%A4%A8%E0%A5%8D_%E0%A5%A8%E0%A5%A6%E0%A5%A6%E0%A5%AB%E0%A4%AF%E0%A4%BE_%E0%A4%B8%E0%A4%82%E0%A4%95%E0%A4%BF%E0%A4%AA%E0%A4%BE)" title="राम् (सन् २००५या संकिपा) – Newari" lang="new" hreflang="new" data-title="राम् (सन् २००५या संकिपा)" data-language-autonym="नेपाल भाषा" data-language-local-name="Newari" class="interlanguage-link-target">नेपाल भाषा</a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Random_Access_Memory" title="Random Access Memory – Japanese" lang="ja" hreflang="ja" data-title="Random Access Memory" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target">日本語</a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Hovedminne" title="Hovedminne – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Hovedminne" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target">Norsk bokmål</a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/Random_Access_Memory" title="Random Access Memory – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="Random Access Memory" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target">Norsk nynorsk</a></li><li class="interlanguage-link interwiki-oc mw-list-item"><a href="https://oc.wikipedia.org/wiki/Mem%C3%B2ria_d%27acc%C3%A8s_aleat%C3%B2ri" title="Memòria d'accès aleatòri – Occitan" lang="oc" hreflang="oc" data-title="Memòria d'accès aleatòri" data-language-autonym="Occitan" data-language-local-name="Occitan" class="interlanguage-link-target">Occitan</a></li><li class="interlanguage-link interwiki-mhr mw-list-item"><a href="https://mhr.wikipedia.org/wiki/%D0%9A%D0%9E%D0%A8" title="КОШ – Eastern Mari" lang="mhr" hreflang="mhr" data-title="КОШ" data-language-autonym="Олык марий" data-language-local-name="Eastern Mari" class="interlanguage-link-target">Олык марий</a></li><li class="interlanguage-link interwiki-uz mw-list-item"><a href="https://uz.wikipedia.org/wiki/Tezkor_xotira" title="Tezkor xotira – Uzbek" lang="uz" hreflang="uz" data-title="Tezkor xotira" data-language-autonym="Oʻzbekcha / ўзбекча" data-language-local-name="Uzbek" class="interlanguage-link-target">Oʻzbekcha / ўзбекча</a></li><li class="interlanguage-link interwiki-pa mw-list-item"><a href="https://pa.wikipedia.org/wiki/%E0%A8%B0%E0%A9%88%E0%A8%82%E0%A8%A1%E0%A8%AE_%E0%A8%90%E0%A8%95%E0%A8%B8%E0%A9%88%E0%A8%B8_%E0%A8%AE%E0%A9%88%E0%A8%AE%E0%A8%B0%E0%A9%80" title="ਰੈਂਡਮ ਐਕਸੈਸ ਮੈਮਰੀ – Punjabi" lang="pa" hreflang="pa" data-title="ਰੈਂਡਮ ਐਕਸੈਸ ਮੈਮਰੀ" data-language-autonym="ਪੰਜਾਬੀ" data-language-local-name="Punjabi" class="interlanguage-link-target">ਪੰਜਾਬੀ</a></li><li class="interlanguage-link interwiki-pnb mw-list-item"><a href="https://pnb.wikipedia.org/wiki/%D8%B1%DB%8C%D9%85" title="ریم – Western Punjabi" lang="pnb" hreflang="pnb" data-title="ریم" data-language-autonym="پنجابی" data-language-local-name="Western Punjabi" class="interlanguage-link-target">پنجابی</a></li><li class="interlanguage-link interwiki-ps mw-list-item"><a href="https://ps.wikipedia.org/wiki/%D8%B1%D9%85" title="رم – Pashto" lang="ps" hreflang="ps" data-title="رم" data-language-autonym="پښتو" data-language-local-name="Pashto" class="interlanguage-link-target">پښتو</a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/RAM" title="RAM – Polish" lang="pl" hreflang="pl" data-title="RAM" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target">Polski</a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Mem%C3%B3ria_de_acesso_aleat%C3%B3rio" title="Memória de acesso aleatório – Portuguese" lang="pt" hreflang="pt" data-title="Memória de acesso aleatório" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target">Português</a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Memorie_cu_acces_aleator" title="Memorie cu acces aleator – Romanian" lang="ro" hreflang="ro" data-title="Memorie cu acces aleator" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target">Română</a></li><li class="interlanguage-link interwiki-rue mw-list-item"><a href="https://rue.wikipedia.org/wiki/%D0%9E%D0%BF%D0%B5%D1%80%D0%B0%D1%87%D0%BD%D0%B0_%D0%BF%D0%B0%D0%BC%D1%8F%D1%82%D1%8C" title="Операчна память – Rusyn" lang="rue" hreflang="rue" data-title="Операчна память" data-language-autonym="Русиньскый" data-language-local-name="Rusyn" class="interlanguage-link-target">Русиньскый</a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%97%D0%B0%D0%BF%D0%BE%D0%BC%D0%B8%D0%BD%D0%B0%D1%8E%D1%89%D0%B5%D0%B5_%D1%83%D1%81%D1%82%D1%80%D0%BE%D0%B9%D1%81%D1%82%D0%B2%D0%BE_%D1%81_%D0%BF%D1%80%D0%BE%D0%B8%D0%B7%D0%B2%D0%BE%D0%BB%D1%8C%D0%BD%D1%8B%D0%BC_%D0%B4%D0%BE%D1%81%D1%82%D1%83%D0%BF%D0%BE%D0%BC" title="Запоминающее устройство с произвольным доступом – Russian" lang="ru" hreflang="ru" data-title="Запоминающее устройство с произвольным доступом" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target">Русский</a></li><li class="interlanguage-link interwiki-sah mw-list-item"><a href="https://sah.wikipedia.org/wiki/RAM" title="RAM – Yakut" lang="sah" hreflang="sah" data-title="RAM" data-language-autonym="Саха тыла" data-language-local-name="Yakut" class="interlanguage-link-target">Саха тыла</a></li><li class="interlanguage-link interwiki-sc mw-list-item"><a href="https://sc.wikipedia.org/wiki/Mem%C3%B2ria_a_atzessu_casuale" title="Memòria a atzessu casuale – Sardinian" lang="sc" hreflang="sc" data-title="Memòria a atzessu casuale" data-language-autonym="Sardu" data-language-local-name="Sardinian" class="interlanguage-link-target">Sardu</a></li><li class="interlanguage-link interwiki-sco mw-list-item"><a href="https://sco.wikipedia.org/wiki/Random-access_memory" title="Random-access memory – Scots" lang="sco" hreflang="sco" data-title="Random-access memory" data-language-autonym="Scots" data-language-local-name="Scots" class="interlanguage-link-target">Scots</a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/Kujtes%C3%AB_me_hyrje_t%C3%AB_rast%C3%ABsishme" title="Kujtesë me hyrje të rastësishme – Albanian" lang="sq" hreflang="sq" data-title="Kujtesë me hyrje të rastësishme" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target">Shqip</a></li><li class="interlanguage-link interwiki-si mw-list-item"><a href="https://si.wikipedia.org/wiki/%E0%B7%83%E0%B7%83%E0%B6%B8%E0%B7%8A%E0%B6%B7%E0%B7%8F%E0%B7%80%E0%B7%93_%E0%B6%B4%E0%B7%8A%E2%80%8D%E0%B6%BB%E0%B7%80%E0%B7%9A%E0%B7%81_%E0%B6%B8%E0%B6%AD%E0%B6%9A%E0%B6%BA" title="සසම්භාවී ප්‍රවේශ මතකය – Sinhala" lang="si" hreflang="si" data-title="සසම්භාවී ප්‍රවේශ මතකය" data-language-autonym="සිංහල" data-language-local-name="Sinhala" class="interlanguage-link-target">සිංහල</a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Random-access_memory" title="Random-access memory – Simple English" lang="en-simple" hreflang="en-simple" data-title="Random-access memory" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target">Simple English</a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Pam%C3%A4%C5%A5_s_priamym_pr%C3%ADstupom" title="Pamäť s priamym prístupom – Slovak" lang="sk" hreflang="sk" data-title="Pamäť s priamym prístupom" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target">Slovenčina</a></li><li class="interlanguage-link interwiki-sl mw-list-item"><a href="https://sl.wikipedia.org/wiki/Bralno-pisalni_pomnilnik" title="Bralno-pisalni pomnilnik – Slovenian" lang="sl" hreflang="sl" data-title="Bralno-pisalni pomnilnik" data-language-autonym="Slovenščina" data-language-local-name="Slovenian" class="interlanguage-link-target">Slovenščina</a></li><li class="interlanguage-link interwiki-ckb mw-list-item"><a href="https://ckb.wikipedia.org/wiki/%D8%A8%DB%8C%D8%B1%DA%AF%DB%95%DB%8C_%D8%AF%DB%95%D8%B3%D8%AA%D9%BE%DB%8E%DA%AF%DB%95%DB%8C%D8%B4%D8%AA%D9%86-%D8%A8%DB%95%DA%BE%DB%95%DA%B5%DA%A9%DB%95%D9%88%D8%AA" title="بیرگەی دەستپێگەیشتن-بەھەڵکەوت – Central Kurdish" lang="ckb" hreflang="ckb" data-title="بیرگەی دەستپێگەیشتن-بەھەڵکەوت" data-language-autonym="کوردی" data-language-local-name="Central Kurdish" class="interlanguage-link-target">کوردی</a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/RAM" title="RAM – Serbian" lang="sr" hreflang="sr" data-title="RAM" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target">Српски / srpski</a></li><li class="interlanguage-link interwiki-sh mw-list-item"><a href="https://sh.wikipedia.org/wiki/RAM" title="RAM – Serbo-Croatian" lang="sh" hreflang="sh" data-title="RAM" data-language-autonym="Srpskohrvatski / српскохрватски" data-language-local-name="Serbo-Croatian" class="interlanguage-link-target">Srpskohrvatski / српскохрватски</a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Hajasaantimuisti" title="Hajasaantimuisti – Finnish" lang="fi" hreflang="fi" data-title="Hajasaantimuisti" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target">Suomi</a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Random-access_memory" title="Random-access memory – Swedish" lang="sv" hreflang="sv" data-title="Random-access memory" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target">Svenska</a></li><li class="interlanguage-link interwiki-tl mw-list-item"><a href="https://tl.wikipedia.org/wiki/Random_access_memory" title="Random access memory – Tagalog" lang="tl" hreflang="tl" data-title="Random access memory" data-language-autonym="Tagalog" data-language-local-name="Tagalog" class="interlanguage-link-target">Tagalog</a></li><li class="interlanguage-link interwiki-ta mw-list-item"><a href="https://ta.wikipedia.org/wiki/%E0%AE%A8%E0%AF%87%E0%AE%B0%E0%AE%9F%E0%AE%BF_%E0%AE%85%E0%AE%A3%E0%AF%81%E0%AE%95%E0%AE%B2%E0%AF%8D_%E0%AE%A8%E0%AE%BF%E0%AE%A9%E0%AF%88%E0%AE%B5%E0%AE%95%E0%AE%AE%E0%AF%8D" title="நேரடி அணுகல் நினைவகம் – Tamil" lang="ta" hreflang="ta" data-title="நேரடி அணுகல் நினைவகம்" data-language-autonym="தமிழ்" data-language-local-name="Tamil" class="interlanguage-link-target">தமிழ்</a></li><li class="interlanguage-link interwiki-te mw-list-item"><a href="https://te.wikipedia.org/wiki/%E0%B0%B0%E0%B0%BE%E0%B0%82%E0%B0%A1%E0%B0%AE%E0%B1%8D_%E0%B0%8F%E0%B0%95%E0%B1%8D%E0%B0%B8%E0%B1%86%E0%B0%B8%E0%B1%8D_%E0%B0%AE%E0%B1%86%E0%B0%AE%E0%B0%B0%E0%B1%80" title="రాండమ్ ఏక్సెస్ మెమరీ – Telugu" lang="te" hreflang="te" data-title="రాండమ్ ఏక్సెస్ మెమరీ" data-language-autonym="తెలుగు" data-language-local-name="Telugu" class="interlanguage-link-target">తెలుగు</a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%AB%E0%B8%99%E0%B9%88%E0%B8%A7%E0%B8%A2%E0%B8%84%E0%B8%A7%E0%B8%B2%E0%B8%A1%E0%B8%88%E0%B8%B3%E0%B9%80%E0%B8%82%E0%B9%89%E0%B8%B2%E0%B8%96%E0%B8%B6%E0%B8%87%E0%B9%82%E0%B8%94%E0%B8%A2%E0%B8%AA%E0%B8%B8%E0%B9%88%E0%B8%A1" title="หน่วยความจำเข้าถึงโดยสุ่ม – Thai" lang="th" hreflang="th" data-title="หน่วยความจำเข้าถึงโดยสุ่ม" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target">ไทย</a></li><li class="interlanguage-link interwiki-tg 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data-title="Пам'ять з довільним доступом" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target">Українська</a></li><li class="interlanguage-link interwiki-ur mw-list-item"><a href="https://ur.wikipedia.org/wiki/%D8%B1%DB%8C%D9%86%DA%88%D9%85_%D8%A7%DB%8C%DA%A9%D8%B3%D8%B3_%D9%85%DB%8C%D9%85%D9%88%D8%B1%DB%8C" title="رینڈم ایکسس میموری – Urdu" lang="ur" hreflang="ur" data-title="رینڈم ایکسس میموری" data-language-autonym="اردو" data-language-local-name="Urdu" class="interlanguage-link-target">اردو</a></li><li class="interlanguage-link interwiki-vec mw-list-item"><a href="https://vec.wikipedia.org/wiki/RAM" title="RAM – Venetian" lang="vec" hreflang="vec" data-title="RAM" data-language-autonym="Vèneto" data-language-local-name="Venetian" class="interlanguage-link-target">Vèneto</a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/RAM" title="RAM – Vietnamese" lang="vi" hreflang="vi" data-title="RAM" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target">Tiếng Việt</a></li><li class="interlanguage-link interwiki-war mw-list-item"><a href="https://war.wikipedia.org/wiki/RAM" title="RAM – Waray" lang="war" hreflang="war" data-title="RAM" data-language-autonym="Winaray" data-language-local-name="Waray" class="interlanguage-link-target">Winaray</a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/%E9%9A%8F%E6%9C%BA%E5%AD%98%E5%8F%96%E5%AD%98%E5%82%A8%E5%99%A8" title="随机存取存储器 – Wu" lang="wuu" hreflang="wuu" data-title="随机存取存储器" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target">吴语</a></li><li class="interlanguage-link interwiki-yi mw-list-item"><a href="https://yi.wikipedia.org/wiki/RAM_%D7%96%D7%99%D7%9B%D7%A8%D7%95%D7%9F" title="RAM זיכרון – Yiddish" lang="yi" hreflang="yi" data-title="RAM זיכרון" data-language-autonym="ייִדיש" data-language-local-name="Yiddish" class="interlanguage-link-target">ייִדיש</a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/RAM" title="RAM – Cantonese" lang="yue" hreflang="yue" data-title="RAM" data-language-autonym="粵語" data-language-local-name="Cantonese" class="interlanguage-link-target">粵語</a></li><li class="interlanguage-link interwiki-diq mw-list-item"><a href="https://diq.wikipedia.org/wiki/RAM" title="RAM – Zazaki" lang="diq" hreflang="diq" data-title="RAM" data-language-autonym="Zazaki" data-language-local-name="Zazaki" class="interlanguage-link-target">Zazaki</a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E9%9A%8F%E6%9C%BA%E5%AD%98%E5%82%A8%E5%99%A8" title="随机存储器 – Chinese" lang="zh" hreflang="zh" data-title="随机存储器" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target">中文</a></li> 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data-file-width="512" data-file-height="512" /></a></div></div> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle">(Redirected from <a href="/w/index.php?title=Random_Access_Memory&redirect=no" class="mw-redirect" title="Random Access Memory">Random Access Memory</a>)</div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Form of computer data storage</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"RAM" redirects here. For other uses, see <a href="/wiki/RAM_(disambiguation)" class="mw-redirect mw-disambig" title="RAM (disambiguation)">RAM (disambiguation)</a>.</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/Random_Access_Memories" title="Random Access Memories">Random Access Memories</a> or <a href="/wiki/Random-access_machine" title="Random-access machine">Random-access machine</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output 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.sidebar{width:22em;float:right;clear:right;margin:0.5em 0 1em 1em;background:var(--background-color-neutral-subtle,#f8f9fa);border:1px solid var(--border-color-base,#a2a9b1);padding:0.2em;text-align:center;line-height:1.4em;font-size:88%;border-collapse:collapse;display:table}body.skin-minerva .mw-parser-output .sidebar{display:table!important;float:right!important;margin:0.5em 0 1em 1em!important}.mw-parser-output .sidebar-subgroup{width:100%;margin:0;border-spacing:0}.mw-parser-output .sidebar-left{float:left;clear:left;margin:0.5em 1em 1em 0}.mw-parser-output .sidebar-none{float:none;clear:both;margin:0.5em 1em 1em 0}.mw-parser-output .sidebar-outer-title{padding:0 0.4em 0.2em;font-size:125%;line-height:1.2em;font-weight:bold}.mw-parser-output .sidebar-top-image{padding:0.4em}.mw-parser-output .sidebar-top-caption,.mw-parser-output .sidebar-pretitle-with-top-image,.mw-parser-output .sidebar-caption{padding:0.2em 0.4em 0;line-height:1.2em}.mw-parser-output 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.sidebar-list-title-c{padding:0 0.4em;text-align:center;margin:0 3.3em}@media(max-width:640px){body.mediawiki .mw-parser-output .sidebar{width:100%!important;clear:both;float:none!important;margin-left:0!important;margin-right:0!important}}body.skin--responsive .mw-parser-output .sidebar a>img{max-width:none!important}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar sidebar-collapse nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="/wiki/Computer_memory" title="Computer memory">Computer memory</a> and <a href="/wiki/Computer_data_storage" title="Computer data storage">data storage</a> types</th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">General</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Memory_coherence" title="Memory coherence">Memory coherence</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></li> <li><a href="/wiki/Memory_access_pattern" title="Memory access pattern">Memory access pattern</a></li> <li><a href="/wiki/Memory_map" title="Memory map">Memory map</a></li> <li><a href="/wiki/Computer_data_storage#Secondary_storage" title="Computer data storage">Secondary storage</a></li> <li><a href="/wiki/Semiconductor_memory" title="Semiconductor memory">MOS memory</a> <ul><li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">floating-gate</a></li></ul></li> <li><a href="/wiki/Continuous_availability" title="Continuous availability">Continuous availability</a></li> <li><a href="/wiki/Areal_density_(computer_storage)" class="mw-redirect" title="Areal density (computer storage)">Areal density (computer storage)</a></li> <li><a href="/wiki/Block_(data_storage)" title="Block (data storage)">Block (data storage)</a></li> <li><a href="/wiki/Object_storage" title="Object storage">Object storage</a></li> <li><a href="/wiki/Direct-attached_storage" title="Direct-attached storage">Direct-attached storage</a></li> <li><a href="/wiki/Network-attached_storage" title="Network-attached storage">Network-attached storage</a> <ul><li><a href="/wiki/Storage_area_network" title="Storage area network">Storage area network</a></li> <li><a href="/wiki/Block-level_storage" title="Block-level storage">Block-level storage</a></li></ul></li> <li><a href="/wiki/Single-instance_storage" title="Single-instance storage">Single-instance storage</a></li> <li><a href="/wiki/Data" title="Data">Data</a></li> <li><a href="/wiki/Data_model" title="Data model">Structured data</a></li> <li><a href="/wiki/Unstructured_data" title="Unstructured data">Unstructured data</a></li> <li><a href="/wiki/Big_data" title="Big data">Big data</a></li> <li><a href="/wiki/Metadata" title="Metadata">Metadata</a></li> <li><a href="/wiki/Data_compression" title="Data compression">Data compression</a></li> <li><a href="/wiki/Data_corruption" title="Data corruption">Data corruption</a></li> <li><a href="/wiki/Data_cleansing" title="Data cleansing">Data cleansing</a></li> <li><a href="/wiki/Data_degradation" title="Data degradation">Data degradation</a></li> <li><a href="/wiki/Data_integrity" title="Data integrity">Data integrity</a></li> <li><a href="/wiki/Data_security" title="Data security">Data security</a></li> <li><a href="/wiki/Data_validation" title="Data validation">Data validation</a></li> <li><a href="/wiki/Data_validation_and_reconciliation" title="Data validation and reconciliation">Data validation and reconciliation</a></li> <li><a href="/wiki/Data_recovery" title="Data recovery">Data recovery</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Storage</a></li> <li><a href="/wiki/Data_cluster" class="mw-redirect" title="Data cluster">Data cluster</a></li> <li><a href="/wiki/Directory_(computing)" title="Directory (computing)">Directory</a></li> <li><a href="/wiki/Shared_resource" title="Shared resource">Shared resource</a></li> <li><a href="/wiki/File_sharing" title="File sharing">File sharing</a></li> <li><a href="/wiki/File_system" title="File system">File system</a></li> <li><a href="/wiki/Clustered_file_system" title="Clustered file system">Clustered file system</a></li> <li><a href="/wiki/Clustered_file_system#Distributed_file_systems" title="Clustered file system">Distributed file system</a></li> <li><a href="/wiki/Distributed_file_system_for_cloud" title="Distributed file system for cloud">Distributed file system for cloud</a></li> <li><a href="/wiki/Distributed_data_store" title="Distributed data store">Distributed data store</a></li> <li><a href="/wiki/Distributed_database" title="Distributed database">Distributed database</a></li> <li><a href="/wiki/Database" title="Database">Database</a></li> <li><a href="/wiki/Data_bank" title="Data bank">Data bank</a></li> <li><a href="/wiki/Data_storage" title="Data storage">Data storage</a></li> <li><a href="/wiki/Data_store" title="Data store">Data store</a></li> <li><a href="/wiki/Data_deduplication" title="Data deduplication">Data deduplication</a></li> <li><a href="/wiki/Data_structure" title="Data structure">Data structure</a></li> <li><a href="/wiki/Data_redundancy" title="Data redundancy">Data redundancy</a></li> <li><a href="/wiki/Replication_(computing)" title="Replication (computing)">Replication (computing)</a></li> <li><a href="/wiki/Memory_refresh" title="Memory refresh">Memory refresh</a></li> <li><a href="/wiki/Storage_record" title="Storage record">Storage record</a></li> <li><a href="/wiki/Information_repository" title="Information repository">Information repository</a></li> <li><a href="/wiki/Knowledge_base" title="Knowledge base">Knowledge base</a></li> <li><a href="/wiki/Computer_file" title="Computer file">Computer file</a></li> <li><a href="/wiki/Object_file" title="Object file">Object file</a></li> <li><a href="/wiki/File_deletion" title="File deletion">File deletion</a></li> <li><a href="/wiki/File_copying" title="File copying">File copying</a></li> <li><a href="/wiki/Backup" title="Backup">Backup</a></li> <li><a href="/wiki/Core_dump" title="Core dump">Core dump</a></li> <li><a href="/wiki/Hex_dump" title="Hex dump">Hex dump</a></li> <li><a href="/wiki/Data_communication" title="Data communication">Data communication</a></li> <li><a href="/wiki/Information_transfer" title="Information transfer">Information transfer</a></li> <li><a href="/wiki/Temporary_file" title="Temporary file">Temporary file</a></li> <li><a href="/wiki/Copy_protection" title="Copy protection">Copy protection</a></li> <li><a href="/wiki/Digital_rights_management" title="Digital rights management">Digital rights management</a></li> <li><a href="/wiki/Volume_(computing)" title="Volume (computing)">Volume (computing)</a></li> <li><a href="/wiki/Boot_sector" title="Boot sector">Boot sector</a></li> <li><a href="/wiki/Master_boot_record" title="Master boot record">Master boot record</a></li> <li><a href="/wiki/Volume_boot_record" title="Volume boot record">Volume boot record</a></li> <li><a href="/wiki/Disk_array" title="Disk array">Disk array</a></li> <li><a href="/wiki/Disk_image" title="Disk image">Disk image</a></li> <li><a href="/wiki/Disk_mirroring" title="Disk mirroring">Disk mirroring</a></li> <li><a href="/wiki/Disk_aggregation" title="Disk aggregation">Disk aggregation</a></li> <li><a href="/wiki/Disk_partitioning" title="Disk partitioning">Disk partitioning</a></li> <li><a href="/wiki/Memory_segmentation" title="Memory segmentation">Memory segmentation</a></li> <li><a href="/wiki/Locality_of_reference" title="Locality of reference">Locality of reference</a></li> <li><a href="/wiki/Logical_disk" title="Logical disk">Logical disk</a></li> <li><a href="/wiki/Storage_virtualization" title="Storage virtualization">Storage virtualization</a></li> <li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Memory-mapped_file" title="Memory-mapped file">Memory-mapped file</a></li> <li><a href="/wiki/Software_entropy" class="mw-redirect" title="Software entropy">Software entropy</a></li> <li><a href="/wiki/Software_rot" title="Software rot">Software rot</a></li> <li><a href="/wiki/In-memory_database" title="In-memory database">In-memory database</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory processing</a></li> <li><a href="/wiki/Persistence_(computer_science)" title="Persistence (computer science)">Persistence (computer science)</a></li> <li><a href="/wiki/Persistent_data_structure" title="Persistent data structure">Persistent data structure</a></li> <li><a href="/wiki/RAID" title="RAID">RAID</a></li> <li><a href="/wiki/Non-RAID_drive_architectures" title="Non-RAID drive architectures">Non-RAID drive architectures</a></li> <li><a href="/wiki/Memory_paging" title="Memory paging">Memory paging</a></li> <li><a href="/wiki/Bank_switching" title="Bank switching">Bank switching</a></li> <li><a href="/wiki/Grid_computing" title="Grid computing">Grid computing</a></li> <li><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a></li> <li><a href="/wiki/Cloud_storage" title="Cloud storage">Cloud storage</a></li> <li><a href="/wiki/Fog_computing" title="Fog computing">Fog computing</a></li> <li><a href="/wiki/Edge_computing" title="Edge computing">Edge computing</a></li> <li><a href="/wiki/Dew_computing" title="Dew computing">Dew computing</a></li> <li><a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a></li> <li><a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a></li> <li><a href="/wiki/Mark_Kryder#Kryder's_law_projection" title="Mark Kryder">Kryder's law</a></li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Volatile_memory" title="Volatile memory">Volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a class="mw-selflink selflink">RAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Cache_(computing)#HARDWARE" title="Cache (computing)">Hardware cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li></ul></li> <li><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> <ul><li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Synchronous_Graphics_RAM_(SGRAM)" title="Synchronous dynamic random-access memory">SGRAM</a></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a></li> <li><a href="/wiki/Quad_Data_Rate_SRAM" title="Quad Data Rate SRAM">QDRSRAM</a></li> <li><a href="/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM" title="Dynamic random-access memory">EDO DRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a></li> <li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a></li></ul></li> <li><a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> <ul><li><a href="/wiki/1T-SRAM" title="1T-SRAM">1T-SRAM</a></li></ul></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">QRAM</a></li> <li><a href="/wiki/Content-addressable_memory" title="Content-addressable memory">Content-addressable memory</a> (CAM)</li> <li><a href="/wiki/Computational_RAM" title="Computational RAM">Computational RAM</a></li> <li><a href="/wiki/Video_random_access_memory" class="mw-redirect" title="Video random access memory">VRAM</a></li> <li><a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">Dual-ported RAM</a> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">Video RAM (dual-ported DRAM)</a></li></ul></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Williams_tube" title="Williams tube">Williams–Kilburn tube</a> (1946–1947)</li> <li><a href="/wiki/Delay-line_memory" title="Delay-line memory">Delay-line memory</a> (1947)</li> <li><a href="/wiki/Mellon_optical_memory" title="Mellon optical memory">Mellon optical memory</a> (1951)</li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a> (1952)</li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/T-RAM" title="T-RAM">T-RAM</a> (2009)</li> <li><a href="/wiki/Z-RAM" title="Z-RAM">Z-RAM</a> (2002–2010)</li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">Non-volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Diode_matrix" title="Diode matrix">Diode matrix</a></li> <li><a href="/wiki/Read-only_memory#Factory-programmed" title="Read-only memory">MROM</a></li> <li><a href="/wiki/Programmable_ROM" title="Programmable ROM">PROM</a> <ul><li><a href="/wiki/EPROM" title="EPROM">EPROM</a></li> <li><a href="/wiki/EEPROM" title="EEPROM">EEPROM</a></li></ul></li> <li><a href="/wiki/ROM_cartridge" title="ROM cartridge">ROM cartridge</a></li> <li><a href="/wiki/Solid-state_storage" title="Solid-state storage">Solid-state storage</a> (SSS) <ul><li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> is used in:</li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state drive</a> (SSD)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">Solid-state hybrid drive</a> (SSHD)</li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li> <li><a href="/wiki/IBM_FlashSystem" title="IBM FlashSystem">IBM FlashSystem</a></li> <li><a href="/wiki/Flash_Core_Module" title="Flash Core Module">Flash Core Module</a></li></ul></li> <li><a href="/wiki/Memory_card" title="Memory card">Memory card</a> <ul><li><a href="/wiki/Memory_Stick" title="Memory Stick">Memory Stick</a></li> <li><a href="/wiki/CompactFlash" title="CompactFlash">CompactFlash</a></li> <li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/MultiMediaCard" title="MultiMediaCard">MultiMediaCard</a></li> <li><a href="/wiki/SD_card" title="SD card">SD card</a></li> <li><a href="/wiki/SIM_card" title="SIM card">SIM card</a></li> <li><a href="/wiki/SmartMedia" title="SmartMedia">SmartMedia</a></li> <li><a href="/wiki/Universal_Flash_Storage" title="Universal Flash Storage">Universal Flash Storage</a></li> <li><a href="/wiki/SxS" title="SxS">SxS</a></li> <li><a href="/wiki/MicroP2" title="MicroP2">MicroP2</a></li> <li><a href="/wiki/XQD_card" title="XQD card">XQD card</a></li></ul></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">Programmable metallization cell</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Phase-change_memory" title="Phase-change memory">PCM</a> (<a href="/wiki/3D_XPoint" title="3D XPoint">3D XPoint</a>)</li> <li><a href="/wiki/Magnetoresistive_RAM" title="Magnetoresistive RAM">MRAM</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">Electrochemical RAM</a> (ECRAM)</li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">Nano-RAM</a></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Early-stage <a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FeRAM</a></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Fe_FET" title="Fe FET">FeFET memory</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Analog_recording" title="Analog recording">Analog recording</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Phonograph_cylinder" title="Phonograph cylinder">Phonograph cylinder</a></li> <li><a href="/wiki/Phonograph_record" title="Phonograph record">Phonograph record</a></li> <li><a href="/wiki/Quadruplex_videotape" title="Quadruplex videotape">Quadruplex videotape</a></li> <li><a href="/wiki/Vision_Electronic_Recording_Apparatus" title="Vision Electronic Recording Apparatus">Vision Electronic Recording Apparatus</a></li> <li><a href="/wiki/Magnetic_recording" class="mw-redirect" title="Magnetic recording">Magnetic recording</a> <ul><li><a href="/wiki/Magnetic_storage" title="Magnetic storage">Magnetic storage</a></li> <li><a href="/wiki/Magnetic_tape" title="Magnetic tape">Magnetic tape</a></li> <li><a href="/wiki/Magnetic-tape_data_storage" title="Magnetic-tape data storage">Magnetic-tape data storage</a></li> <li><a href="/wiki/Tape_drive" title="Tape drive">Tape drive</a></li> <li><a href="/wiki/Tape_library" title="Tape library">Tape library</a></li> <li><a href="/wiki/Digital_Data_Storage" title="Digital Data Storage">Digital Data Storage</a> (DDS)</li> <li><a href="/wiki/Videotape" title="Videotape">Videotape</a></li> <li><a href="/wiki/Videocassette" class="mw-redirect" title="Videocassette">Videocassette</a></li> <li><a href="/wiki/Cassette_tape" title="Cassette tape">Cassette tape</a></li> <li><a href="/wiki/Linear_Tape-Open" title="Linear Tape-Open">Linear Tape-Open</a></li> <li><a href="/wiki/Betamax" title="Betamax">Betamax</a></li> <li><a href="/wiki/8_mm_video_format" title="8 mm video format">8 mm video format</a></li> <li><a href="/wiki/DV_(video_format)" title="DV (video format)">DV</a></li> <li><a href="/wiki/MiniDV" class="mw-redirect" title="MiniDV">MiniDV</a></li> <li><a href="/wiki/MicroMV" title="MicroMV">MicroMV</a></li> <li><a href="/wiki/U-matic" title="U-matic">U-matic</a></li> <li><a href="/wiki/VHS" title="VHS">VHS</a></li> <li><a href="/wiki/S-VHS" title="S-VHS">S-VHS</a></li> <li><a href="/wiki/VHS-C" title="VHS-C">VHS-C</a></li> <li><a href="/wiki/D-VHS" title="D-VHS">D-VHS</a></li></ul></li> <li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">Hard disk drive</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Optical_storage" title="Optical storage">Optical</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/3D_optical_data_storage" title="3D optical data storage">3D optical data storage</a> <ul><li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a></li> <li><a href="/wiki/LaserDisc" title="LaserDisc">LaserDisc</a></li> <li><a href="/wiki/Compact_Disc_Digital_Audio" title="Compact Disc Digital Audio">Compact Disc Digital Audio</a> (CDDA)</li> <li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/CD_Video" title="CD Video">CD Video</a></li> <li><a href="/wiki/CD-R" title="CD-R">CD-R</a></li> <li><a href="/wiki/CD-RW" title="CD-RW">CD-RW</a></li> <li><a href="/wiki/Video_CD" title="Video CD">Video CD</a></li> <li><a href="/wiki/Super_Video_CD" title="Super Video CD">Super Video CD</a></li> <li><a href="/wiki/Mini_CD" title="Mini CD">Mini CD</a></li> <li><a href="/wiki/Nintendo_optical_discs" title="Nintendo optical discs">Nintendo optical discs</a></li> <li><a href="/wiki/CD-ROM" title="CD-ROM">CD-ROM</a></li> <li><a href="/wiki/Hyper_CD-ROM" title="Hyper CD-ROM">Hyper CD-ROM</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/DVD_recordable#DVD+R_and_DVD+RW_(DVD_"plus")" title="DVD recordable">DVD+R</a></li> <li><a href="/wiki/DVD-Video" title="DVD-Video">DVD-Video</a></li> <li><a href="/wiki/DVD_card" title="DVD card">DVD card</a></li> <li><a href="/wiki/DVD-RAM" title="DVD-RAM">DVD-RAM</a></li> <li><a href="/wiki/MiniDVD" title="MiniDVD">MiniDVD</a></li> <li><a href="/wiki/HD_DVD" title="HD DVD">HD DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li> <li><a href="/wiki/Ultra_HD_Blu-ray" title="Ultra HD Blu-ray">Ultra HD Blu-ray</a></li> <li><a href="/wiki/Holographic_Versatile_Disc" title="Holographic Versatile Disc">Holographic Versatile Disc</a></li></ul></li> <li><a href="/wiki/Write_once_read_many" title="Write once read many">WORM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">In development</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li> <li><a href="/wiki/Racetrack_memory" title="Racetrack memory">Racetrack memory</a></li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">NRAM</a></li> <li><a href="/wiki/Millipede_memory" title="Millipede memory">Millipede memory</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">ECRAM</a></li> <li><a href="/wiki/Patterned_media" title="Patterned media">Patterned media</a></li> <li><a href="/wiki/Holographic_data_storage" title="Holographic data storage">Holographic data storage</a> <ul><li><a href="/wiki/Electronic_quantum_holography" title="Electronic quantum holography">Electronic quantum holography</a></li></ul></li> <li><a href="/wiki/5D_optical_data_storage" title="5D optical data storage">5D optical data storage</a></li> <li><a href="/wiki/DNA_digital_data_storage" title="DNA digital data storage">DNA digital data storage</a></li> <li><a href="/wiki/Universal_memory" title="Universal memory">Universal memory</a></li> <li><a href="/wiki/Time_crystal" title="Time crystal">Time crystal</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">Quantum memory</a></li> <li><a href="/wiki/UltraRAM" title="UltraRAM">UltraRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Paper_data_storage" title="Paper data storage">Paper data storage</a> (1725)</li> <li><a href="/wiki/Punched_card" title="Punched card">Punched card</a> (1725)</li> <li><a href="/wiki/Punched_tape" title="Punched tape">Punched tape</a> (1725)</li> <li><a href="/wiki/Plugboard" title="Plugboard">Plugboard</a></li> <li><a href="/wiki/Drum_memory" title="Drum memory">Drum memory</a> (1932)</li> <li><a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">Magnetic-core memory</a> (1949)</li> <li><a href="/wiki/Plated-wire_memory" title="Plated-wire memory">Plated-wire memory</a> (1957)</li> <li><a href="/wiki/Core_rope_memory" title="Core rope memory">Core rope memory</a> (1960s)</li> <li><a href="/wiki/Thin-film_memory" title="Thin-film memory">Thin-film memory</a> (1962)</li> <li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a> (1962)</li> <li><a href="/wiki/Twistor_memory" title="Twistor memory">Twistor memory</a> (~1968)</li> <li><a href="/wiki/Bubble_memory" title="Bubble memory">Bubble memory</a> (~1970)</li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a> (1971)</li></ul></div></div></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Memory_types" title="Template:Memory types"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Memory_types" title="Template talk:Memory types"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Memory_types" title="Special:EditPage/Template:Memory types"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Electronic_Memory.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c3/Electronic_Memory.jpg/220px-Electronic_Memory.jpg" decoding="async" width="220" height="179" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c3/Electronic_Memory.jpg/330px-Electronic_Memory.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c3/Electronic_Memory.jpg/440px-Electronic_Memory.jpg 2x" data-file-width="1563" data-file-height="1269" /></a><figcaption> A 64 bit memory chip die, the SP95 Phase 2 buffer memory produced at IBM mid-1960s, versus <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">memory core iron rings</a></figcaption></figure> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Swissbit_2GB_PC2-5300U-555.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/db/Swissbit_2GB_PC2-5300U-555.jpg/220px-Swissbit_2GB_PC2-5300U-555.jpg" decoding="async" width="220" height="115" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/db/Swissbit_2GB_PC2-5300U-555.jpg/330px-Swissbit_2GB_PC2-5300U-555.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/db/Swissbit_2GB_PC2-5300U-555.jpg/440px-Swissbit_2GB_PC2-5300U-555.jpg 2x" data-file-width="3938" data-file-height="2054" /></a><figcaption>Example of <a href="/wiki/Read/write_memory" class="mw-redirect" title="Read/write memory">writable</a> <a href="/wiki/Volatile_memory" title="Volatile memory">volatile</a> random-access memory: Synchronous <a href="/wiki/Dynamic_RAM" class="mw-redirect" title="Dynamic RAM">dynamic RAM</a> <a href="/wiki/DIMM" title="DIMM">modules</a>, primarily used as main memory in <a href="/wiki/Personal_computers" class="mw-redirect" title="Personal computers">personal computers</a>, <a href="/wiki/Workstation" title="Workstation">workstations</a>, and <a href="/wiki/Server_(computing)" title="Server (computing)">servers</a>.</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Random_Access_Memory_HyperX.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Random_Access_Memory_HyperX.jpg/220px-Random_Access_Memory_HyperX.jpg" decoding="async" width="220" height="124" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Random_Access_Memory_HyperX.jpg/330px-Random_Access_Memory_HyperX.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Random_Access_Memory_HyperX.jpg/440px-Random_Access_Memory_HyperX.jpg 2x" data-file-width="1920" data-file-height="1080" /></a><figcaption>8GB <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM stick with a white <a href="/wiki/Heatsink" class="mw-redirect" title="Heatsink">heatsink</a></figcaption></figure> Random-access memory (RAM; <a href="/wiki/Help:IPA/English" title="Help:IPA/English">/ræm/</a>) is a form of <a href="/wiki/Computer_memory" title="Computer memory">electronic computer memory</a> that can be read and changed in any order, typically used to store working <a href="/wiki/Data_(computing)" class="mw-redirect" title="Data (computing)">data</a> and <a href="/wiki/Machine_code" title="Machine code">machine code</a>.<a href="#cite_note-1">[1]</a><a href="#cite_note-2">[2]</a> A <a href="/wiki/Random-access" class="mw-redirect" title="Random-access">random-access</a> memory device allows data items to be <a href="/wiki/Read_(computer)" class="mw-redirect" title="Read (computer)">read</a> or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as <a href="/wiki/Hard_disk" class="mw-redirect" title="Hard disk">hard disks</a> and <a href="/wiki/Magnetic_tape_data_storage" class="mw-redirect" title="Magnetic tape data storage">magnetic tape</a>), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement. In today's technology, random-access memory takes the form of <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) chips with <a href="/wiki/MOSFET" title="MOSFET">MOS</a> (metal–oxide–semiconductor) <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">memory cells</a>. RAM is normally associated with <a href="/wiki/Volatile_memory" title="Volatile memory">volatile</a> types of memory where stored information is lost if power is removed. The two main types of volatile random-access <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> are <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM) and <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic random-access memory</a> (DRAM). Non-volatile RAM has also been developed<a href="#cite_note-3">[3]</a> and other types of <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">non-volatile memories</a> allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of <a href="/wiki/ROM" class="mw-redirect" title="ROM">ROM</a> and <a href="/wiki/NOR_flash_memory" class="mw-redirect" title="NOR flash memory">NOR flash memory</a>. The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their <a href="/wiki/IBM_System/360" title="IBM System/360">System/360 Model 95</a> computer, and <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 <a href="/wiki/Electronic_calculator" class="mw-redirect" title="Electronic calculator">electronic calculator</a>, both based on <a href="/wiki/Bipolar_transistor" class="mw-redirect" title="Bipolar transistor">bipolar transistors</a>. While it offered higher speeds than <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">magnetic-core memory</a>, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<a href="#cite_note-4">[4]</a> In 1966, Dr. <a href="/wiki/Robert_Dennard" class="mw-redirect" title="Robert Dennard">Robert Dennard</a> invented modern DRAM architecture in which there's a single MOS transistor per capacitor.<a href="#cite_note-5">[5]</a> The first commercial DRAM IC chip, the 1K <a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a>, was introduced in October 1970. <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a> (SDRAM) was reintroduced with the <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> KM48SL2000 chip in 1992. <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Early_SSA_accounting_operations.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f7/Early_SSA_accounting_operations.jpg/220px-Early_SSA_accounting_operations.jpg" decoding="async" width="220" height="269" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f7/Early_SSA_accounting_operations.jpg/330px-Early_SSA_accounting_operations.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f7/Early_SSA_accounting_operations.jpg/440px-Early_SSA_accounting_operations.jpg 2x" data-file-width="473" data-file-height="578" /></a><figcaption>These IBM <a href="/wiki/Tabulating_machine" title="Tabulating machine">tabulating machines</a> from the mid-1930s used <a href="/wiki/Mechanical_counter" title="Mechanical counter">mechanical counters</a> to store information.</figcaption></figure> Early computers used <a href="/wiki/Relay" title="Relay">relays</a>, <a href="/wiki/Mechanical_counter" title="Mechanical counter">mechanical counters</a><a href="#cite_note-6">[6]</a> or <a href="/wiki/Delay-line_memory" title="Delay-line memory">delay lines</a> for main memory functions. Ultrasonic delay lines were <a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">serial devices</a> which could only reproduce data in the order it was written. <a href="/wiki/Drum_memory" title="Drum memory">Drum memory</a> could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of <a href="/wiki/Triode_vacuum_tube" class="mw-redirect" title="Triode vacuum tube">triode vacuum tubes</a>, and later, out of <a href="/wiki/Discrete_transistor" class="mw-redirect" title="Discrete transistor">discrete transistors</a>, were used for smaller and faster memories such as <a href="/wiki/Hardware_register" title="Hardware register">registers</a>. Such registers were relatively large and too costly to use for large amounts of data; generally only a few dozen or few hundred bits of such memory could be provided. The first practical form of random-access memory was the <a href="/wiki/Williams_tube" title="Williams tube">Williams tube</a>. It stored data as electrically charged spots on the face of a <a href="/wiki/Cathode-ray_tube" title="Cathode-ray tube">cathode-ray tube</a>. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the <a href="/wiki/Victoria_University_of_Manchester" title="Victoria University of Manchester">University of Manchester</a> in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the <a href="/wiki/Manchester_Baby" title="Manchester Baby">Manchester Baby</a> computer, which first successfully ran a program on 21 June, 1948.<a href="#cite_note-7">[7]</a> In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a <a href="/wiki/Testbed" title="Testbed">testbed</a> to demonstrate the reliability of the memory.<a href="#cite_note-8">[8]</a><a href="#cite_note-9">[9]</a> <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">Magnetic-core memory</a> was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of <a href="/wiki/Computer_memory" title="Computer memory">computer memory</a> until displaced by <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> in <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs) during the early 1970s.<a href="#cite_note-computerhistory1970-10">[10]</a> Prior to the development of integrated <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM) circuits, permanent (or read-only) random-access memory was often constructed using <a href="/wiki/Diode_matrix" title="Diode matrix">diode matrices</a> driven by <a href="/wiki/Address_decoder" title="Address decoder">address decoders</a>, or specially wound <a href="/wiki/Core_rope_memory" title="Core rope memory">core rope memory</a> planes.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">Semiconductor memory</a> appeared in the 1960s with bipolar memory, which used <a href="/wiki/Bipolar_transistor" class="mw-redirect" title="Bipolar transistor">bipolar transistors</a>. Although it was faster, it could not compete with the lower price of magnetic core memory.<a href="#cite_note-computerhistory1966-11">[11]</a> <div class="mw-heading mw-heading3"><h3 id="MOS_RAM">MOS RAM</h3></div> In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<a href="#cite_note-12">[12]</a> Subsequently, in 1960, a team demonstrated a working <a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> at Bell Labs.<a href="#cite_note-13">[13]</a><a href="#cite_note-14">[14]</a> This led to the development of <a href="/wiki/Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">metal–oxide–semiconductor</a> (MOS) memory by John Schmidt at <a href="/wiki/Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a> in 1964.<a href="#cite_note-computerhistory1970-10">[10]</a><a href="#cite_note-15">[15]</a> In addition to higher speeds, MOS <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> was cheaper and consumed less power than magnetic core memory.<a href="#cite_note-computerhistory1970-10">[10]</a> The development of <a href="/wiki/Silicon-gate" class="mw-redirect" title="Silicon-gate">silicon-gate</a> <a href="/wiki/MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> (MOS IC) technology by <a href="/wiki/Federico_Faggin" title="Federico Faggin">Federico Faggin</a> at Fairchild in 1968 enabled the production of MOS <a href="/wiki/Memory_chip" class="mw-redirect" title="Memory chip">memory chips</a>.<a href="#cite_note-16">[16]</a> MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.<a href="#cite_note-computerhistory1970-10">[10]</a> Integrated bipolar <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM) was invented by Robert H. Norman at <a href="/wiki/Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a> in 1963.<a href="#cite_note-17">[17]</a> It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964.<a href="#cite_note-computerhistory1970-10">[10]</a> SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each <a href="/wiki/Bit" title="Bit">bit</a> of data.<a href="#cite_note-ibm100-18">[18]</a> Commercial use of SRAM began in 1965, when <a href="/wiki/IBM" title="IBM">IBM</a> introduced the SP95 memory chip for the <a href="/wiki/IBM_System/360" title="IBM System/360">System/360 Model 95</a>.<a href="#cite_note-computerhistory1966-11">[11]</a> <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away. <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a>'s Toscal BC-1411 <a href="/wiki/Electronic_calculator" class="mw-redirect" title="Electronic calculator">electronic calculator</a>, which was introduced in 1965,<a href="#cite_note-19">[19]</a><a href="#cite_note-bc-spec-20">[20]</a><a href="#cite_note-bc-21">[21]</a> used a form of capacitor-bipolar DRAM, storing 180-bit data on discrete <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">memory cells</a>, consisting of <a href="/wiki/Germanium" title="Germanium">germanium</a> bipolar transistors and capacitors.<a href="#cite_note-bc-spec-20">[20]</a><a href="#cite_note-bc-21">[21]</a> While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then dominant magnetic-core memory.<a href="#cite_note-22">[22]</a> Capacitors had also been used for earlier memory schemes, such as the drum of the <a href="/wiki/Atanasoff%E2%80%93Berry_Computer" class="mw-redirect" title="Atanasoff–Berry Computer">Atanasoff–Berry Computer</a>, the <a href="/wiki/Williams_tube" title="Williams tube">Williams tube</a> and the <a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a>. <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Bundesarchiv_Bild_183-1989-0406-022,_VEB_Carl_Zeiss_Jena,_1-Megabit-Chip.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg/220px-Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg" decoding="async" width="220" height="154" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg/330px-Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg/440px-Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg 2x" data-file-width="791" data-file-height="553" /></a><figcaption>CMOS 1-<a href="/wiki/Megabit" class="mw-redirect" title="Megabit">megabit</a> (Mbit) DRAM chip, one of the last models developed by <a href="/wiki/VEB_Carl_Zeiss_Jena" class="mw-redirect" title="VEB Carl Zeiss Jena">VEB Carl Zeiss Jena</a>, in 1989</figcaption></figure> In 1966, <a href="/wiki/Robert_Dennard" class="mw-redirect" title="Robert Dennard">Robert Dennard</a> invented modern DRAM architecture for which there is a single MOS transistor per capacitor.<a href="#cite_note-ibm100-18">[18]</a> While examining the characteristics of MOS technology, he found it was capable of building <a href="/wiki/Capacitor" title="Capacitor">capacitors</a>, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<a href="#cite_note-ibm100-18">[18]</a> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<a href="#cite_note-Robert_Dennard-23">[23]</a> The first commercial DRAM IC chip was the <a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a>, which was <a href="/wiki/Semiconductor_manufacturing_process" class="mw-redirect" title="Semiconductor manufacturing process">manufactured</a> on an <a href="/wiki/10_%CE%BCm_process" class="mw-redirect" title="10 μm process">8 μm</a> MOS process with a capacity of 1 <a href="/wiki/Kilobit" class="mw-redirect" title="Kilobit">kbit</a>, and was released in 1970.<a href="#cite_note-computerhistory1970-10">[10]</a><a href="#cite_note-Lojek-1103-24">[24]</a><a href="#cite_note-25">[25]</a> The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<a href="#cite_note-26">[26]</a><a href="#cite_note-27">[27]</a> In 1992 Samsung released KM48SL2000, which had a capacity of 16 <a href="/wiki/Mbit" class="mw-redirect" title="Mbit">Mbit</a>.<a href="#cite_note-electronic-design-28">[28]</a><a href="#cite_note-29">[29]</a> and mass-produced in 1993.<a href="#cite_note-electronic-design-28">[28]</a> The first commercial <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> (<a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> SDRAM) memory chip was Samsung's 64 Mbit DDR SDRAM chip, released in June 1998.<a href="#cite_note-30">[30]</a> <a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a> (graphics DDR) is a form of DDR <a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> (synchronous graphics RAM), which was first released by Samsung as a 16 Mbit memory chip in 1998.<a href="#cite_note-31">[31]</a> <div class="mw-heading mw-heading2"><h2 id="Types">Types</h2></div> The two widely used forms of modern RAM are <a href="/wiki/Static_RAM" class="mw-redirect" title="Static RAM">static RAM</a> (SRAM) and <a href="/wiki/Dynamic_RAM" class="mw-redirect" title="Dynamic RAM">dynamic RAM</a> (DRAM). In SRAM, a <a href="/wiki/Bit" title="Bit">bit of data</a> is stored using the state of a six-<a href="/wiki/Transistor" title="Transistor">transistor</a> <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">memory cell</a>, typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as <a href="/wiki/CPU_cache" title="CPU cache">cache memory for the CPU</a>. DRAM stores a bit of data using a transistor and <a href="/wiki/Capacitor" title="Capacitor">capacitor</a> pair (typically a MOSFET and <a href="/wiki/MOS_capacitor" class="mw-redirect" title="MOS capacitor">MOS capacitor</a>, respectively),<a href="#cite_note-32">[32]</a> which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers. Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as <a href="/wiki/EEPROM" title="EEPROM">EEPROM</a> and <a href="/wiki/NOR_flash" class="mw-redirect" title="NOR flash">NOR flash</a>) share properties of both ROM and RAM, enabling data to <a href="/wiki/Persistence_(computer_science)" title="Persistence (computer science)">persist</a> without power and to be updated without requiring special equipment. <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a> (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using <a href="/wiki/Parity_bit" title="Parity bit">parity bits</a> or <a href="/wiki/Error_detection_and_correction#Error-correcting_code" title="Error detection and correction">error correction codes</a>. In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term <a href="/wiki/DVD-RAM" title="DVD-RAM">DVD-RAM</a> is somewhat of a misnomer since, it is not random access; it behaves much like a hard disc drive if somewhat slower. Aside, unlike <a href="/wiki/CD-RW" title="CD-RW">CD-RW</a> or <a href="/wiki/DVD-RW" class="mw-redirect" title="DVD-RW">DVD-RW</a>, DVD-RAM does not need to be erased before reuse. <div class="mw-heading mw-heading2"><h2 id="Memory_cell">Memory cell</h2></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell (computing)</a></div> The memory cell is the fundamental building block of <a href="/wiki/Computer_memory" title="Computer memory">computer memory</a>. The memory cell is an <a href="/wiki/Electronic_circuit" title="Electronic circuit">electronic circuit</a> that stores one <a href="/wiki/Bit" title="Bit">bit</a> of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it. In SRAM, the memory cell is a type of <a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flop</a> circuit, usually implemented using <a href="/wiki/FET" class="mw-redirect" title="FET">FETs</a>. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density. A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM. <table style="text-align:center; margin: 1em auto 1em auto"> <tbody><tr> <td><figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SRAM_Cell_(6_Transistors).svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/SRAM_Cell_%286_Transistors%29.svg/220px-SRAM_Cell_%286_Transistors%29.svg.png" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/SRAM_Cell_%286_Transistors%29.svg/330px-SRAM_Cell_%286_Transistors%29.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/31/SRAM_Cell_%286_Transistors%29.svg/440px-SRAM_Cell_%286_Transistors%29.svg.png 2x" data-file-width="400" data-file-height="300" /></a><figcaption>SRAM cell (6 transistors)</figcaption></figure></td> <td><figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:DRAM_Cell_Structure_(Model_of_Single_Circuit_Cell).PNG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG/220px-DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG" decoding="async" width="220" height="202" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG/330px-DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bd/DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG/440px-DRAM_Cell_Structure_%28Model_of_Single_Circuit_Cell%29.PNG 2x" data-file-width="600" data-file-height="550" /></a><figcaption>DRAM cell (1 transistor and one capacitor)</figcaption></figure> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Addressing">Addressing</h2></div> To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle A_{0},A_{1},...A_{n}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>A</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>0</mn> </mrow> </msub> <mo>,</mo> <msub> <mi>A</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>1</mn> </mrow> </msub> <mo>,</mo> <mo>.</mo> <mo>.</mo> <mo>.</mo> <msub> <mi>A</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>n</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle A_{0},A_{1},...A_{n}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/5f52da9325d1fd575fbdc52435b78b7f5232ecd2" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:13.726ex; height:2.509ex;" alt="{\displaystyle A_{0},A_{1},...A_{n}}">, and for each combination of bits that may be applied to these lines, a set of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two. Usually several memory cells share the same address. For example, a 4 bit "wide" RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed. Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed. RAM is often byte addressable, although it is also possible to make RAM that is word-addressable.<a href="#cite_note-33">[33]</a><a href="#cite_note-34">[34]</a> <div class="mw-heading mw-heading2"><h2 id="Memory_hierarchy">Memory hierarchy</h2></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></div> One can read and over-write data in RAM. Many computer systems have a memory hierarchy consisting of <a href="/wiki/Processor_register" title="Processor register">processor registers</a>, on-<a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> caches, external <a href="/wiki/CPU_cache" title="CPU cache">caches</a>, <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a>, <a href="/wiki/Paging" class="mw-redirect" title="Paging">paging</a> systems and <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a> or <a href="/wiki/Swap_space" class="mw-redirect" title="Swap space">swap space</a> on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different <a href="/wiki/Access_time" title="Access time">access times</a>, violating the original concept behind the random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, <a href="/wiki/Memory_rank" title="Memory rank">rank</a>, channel, or <a href="/wiki/Interleaved_memory" title="Interleaved memory">interleave</a> organization of the components make the access time variable, although not to the extent that access time to rotating <a href="/wiki/Storage_media" class="mw-redirect" title="Storage media">storage media</a> or a tape is variable. The overall goal of using a memory hierarchy is to obtain the fastest possible average access time while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom). In many modern personal computers, the RAM comes in an easily upgraded form of modules called <a href="/wiki/Memory_module" title="Memory module">memory modules</a> or DRAM modules about the size of a few sticks of chewing gum. These can be quickly replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the <a href="/wiki/CPU" class="mw-redirect" title="CPU">CPU</a> and other <a href="/wiki/Integrated_circuit" title="Integrated circuit">ICs</a> on the <a href="/wiki/Motherboard" title="Motherboard">motherboard</a>, as well as in hard-drives, <a href="/wiki/CD-ROM" title="CD-ROM">CD-ROMs</a>, and several other parts of the computer system. <div class="mw-heading mw-heading2"><h2 id="Other_uses_of_RAM">Other uses of RAM</h2></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Samsung-1GB-DDR2-Laptop-RAM.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2c/Samsung-1GB-DDR2-Laptop-RAM.jpg/220px-Samsung-1GB-DDR2-Laptop-RAM.jpg" decoding="async" width="220" height="139" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2c/Samsung-1GB-DDR2-Laptop-RAM.jpg/330px-Samsung-1GB-DDR2-Laptop-RAM.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2c/Samsung-1GB-DDR2-Laptop-RAM.jpg/440px-Samsung-1GB-DDR2-Laptop-RAM.jpg 2x" data-file-width="2840" data-file-height="1800" /></a><figcaption>A <a href="/wiki/SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a> stick of laptop RAM, roughly half the size of <a href="/wiki/DIMM" title="DIMM">desktop RAM</a></figcaption></figure> In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways. <div class="mw-heading mw-heading3"><h3 id="Virtual_memory">Virtual memory</h3></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></div> Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's <a href="/wiki/Hard_drive" class="mw-redirect" title="Hard drive">hard drive</a> is set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging file form the system's total memory. (For example, if a computer has 2 GB (10243 B) of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it.) When the system runs low on physical memory, it can "<a href="/wiki/Paging" class="mw-redirect" title="Paging">swap</a>" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in <a href="/wiki/Thrashing_(computer_science)" title="Thrashing (computer science)">thrashing</a> and generally hampers overall system performance, mainly because hard drives are far slower than RAM. <div class="mw-heading mw-heading3"><h3 id="RAM_disk">RAM disk</h3></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/RAM_drive" title="RAM drive">RAM drive</a></div> Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a <a href="/wiki/RAM_disk" class="mw-redirect" title="RAM disk">RAM disk</a>. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source, or changes to the RAM disk are written out to a nonvolatile disk. The RAM disk is reloaded from the physical disk upon RAM disk initialization. <div class="mw-heading mw-heading3"><h3 id="Shadow_RAM">Shadow RAM</h3></div> Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, is fairly common in both computers and <a href="/wiki/Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a>. As a common example, the <a href="/wiki/BIOS" title="BIOS">BIOS</a> in typical personal computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the <a href="/wiki/Operating_system" title="Operating system">operating system</a> if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.<a href="#cite_note-35">[35]</a> <div class="mw-heading mw-heading2"><h2 id="Memory_wall">Memory wall</h2></div> The 'memory wall is the growing disparity of speed between CPU and the response time of memory (known as <a href="/wiki/Memory_latency" title="Memory latency">memory latency</a>) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries, which is also referred to as bandwidth wall. From 1986 to 2000, <a href="/wiki/CPU" class="mw-redirect" title="CPU">CPU</a> speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming <a href="/wiki/Bottleneck_(engineering)" title="Bottleneck (engineering)">bottleneck</a> in computer performance.<a href="#cite_note-36">[36]</a> Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power. CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. <a href="/wiki/Intel" title="Intel">Intel</a> summarized these causes in a 2005 document.<a href="#cite_note-37">[37]</a> <blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor <a href="/wiki/Leakage_current" class="mw-redirect" title="Leakage current">leakage current</a> increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called <a href="/wiki/Von_Neumann_bottleneck" class="mw-redirect" title="Von Neumann bottleneck">von Neumann bottleneck</a>), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, <a href="/wiki/RC_time_constant#Delay" title="RC time constant">resistance-capacitance</a> (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote> The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"<a href="#cite_note-38">[38]</a> which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014. A different concept is the processor-memory performance gap, which can be addressed by <a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D integrated circuits</a> that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.<a href="#cite_note-39">[39]</a> Memory subsystem design requires a focus on the gap, which is widening over time.<a href="#cite_note-40">[40]</a> The main method of bridging the gap is the use of <a href="/wiki/Cache_(computing)" title="Cache (computing)">caches</a>; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.<a href="#cite_note-41">[41]</a> There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.<a href="#cite_note-42">[42]</a> <a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state hard drives</a> have continued to increase in speed, from ~400 Mbit/s via <a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">SATA3</a> in 2012 up to ~7 GB/s via <a href="/wiki/NVMe" class="mw-redirect" title="NVMe">NVMe</a>/<a href="/wiki/PCIe" class="mw-redirect" title="PCIe">PCIe</a> in 2024, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> 8000MHz capable of 128 GB/s, and modern <a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a> even faster. Fast, cheap, <a href="/wiki/Non-volatile" class="mw-redirect" title="Non-volatile">non-volatile</a> solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in <a href="/wiki/Server_farm" title="Server farm">server farms</a> - 1 <a href="/wiki/Terabyte" class="mw-redirect" title="Terabyte">terabyte</a> of SSD storage can be had for $200, while 1 TB of RAM would cost thousands of dollars.<a href="#cite_note-43">[43]</a><a href="#cite_note-44">[44]</a> <div class="mw-heading mw-heading2"><h2 id="Timeline">Timeline</h2></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Flash_memory#Timeline" title="Flash memory">Flash memory § Timeline</a>, <a href="/wiki/Read-only_memory#Timeline" title="Read-only memory">Read-only memory § Timeline</a>, and <a href="/wiki/Transistor_count#Memory" title="Transistor count">Transistor count § Memory</a></div> <div class="mw-heading mw-heading3"><h3 id="SRAM">SRAM</h3></div> <table class="wikitable sortable" style="text-align:center"> <caption><a href="/wiki/Static_random-access_memory" title="Static random-access memory">Static random-access memory</a> (SRAM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>) </th> <th><a href="/wiki/Access_time" title="Access time">Access time</a> </th> <th>SRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td>March 1963 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/1-bit_computing" title="1-bit computing">1</a> </td> <td>? </td> <td><a href="/wiki/Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar</a> (<a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">cell</a>) </td> <td><a href="/wiki/Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2"><a href="#cite_note-computerhistory1966-11">[11]</a> </td></tr> <tr> <td rowspan="3">1965 </td> <td>? </td> <td><a href="/wiki/8-bit" class="mw-redirect" title="8-bit">8</a> </td> <td>? </td> <td><a href="/wiki/Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar</a> </td> <td><a href="/wiki/IBM" title="IBM">IBM</a> </td> <td>? </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>SP95 </td> <td><a href="/wiki/16-bit" class="mw-redirect" title="16-bit">16</a> </td> <td>? </td> <td>Bipolar </td> <td>IBM </td> <td>? </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-45">[45]</a> </td></tr> <tr> <td>? </td> <td><a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64</a> </td> <td>? </td> <td><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </td> <td>Fairchild </td> <td>? </td> <td><a href="/wiki/PMOS_logic" title="PMOS logic">PMOS</a> </td> <td><a href="#cite_note-Sah1303-46">[46]</a> </td></tr> <tr> <td rowspan="2">1966 </td> <td>TMC3162 </td> <td>16 </td> <td>? </td> <td>Bipolar (<a href="/wiki/Transistor%E2%80%93transistor_logic" title="Transistor–transistor logic">TTL</a>) </td> <td><a href="/wiki/Transitron" class="mw-redirect" title="Transitron">Transitron</a> </td> <td>? </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-computerhistory1970-10">[10]</a> </td></tr> <tr> <td>? </td> <td>? </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td>? </td> <td>? </td> <td><a href="#cite_note-shmj-mos-47">[47]</a> </td></tr> <tr> <td rowspan="3">1968 </td> <td rowspan="3">? </td> <td>64 </td> <td>? </td> <td>MOSFET </td> <td>Fairchild </td> <td>? </td> <td>PMOS </td> <td rowspan="2"><a href="#cite_note-shmj-mos-47">[47]</a> </td></tr> <tr> <td>144 </td> <td>? </td> <td>MOSFET </td> <td>NEC </td> <td>? </td> <td><a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a> </td></tr> <tr> <td><a href="/wiki/512-bit" class="mw-redirect" title="512-bit">512</a> </td> <td>? </td> <td>MOSFET </td> <td>IBM </td> <td>? </td> <td>NMOS </td> <td><a href="#cite_note-Sah1303-46">[46]</a> </td></tr> <tr> <td rowspan="2">1969 </td> <td>? </td> <td><a href="/wiki/128-bit" class="mw-redirect" title="128-bit">128</a> </td> <td>? </td> <td>Bipolar </td> <td>IBM </td> <td>? </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-computerhistory1966-11">[11]</a> </td></tr> <tr> <td>1101 </td> <td><a href="/wiki/256-bit" class="mw-redirect" title="256-bit">256</a> </td> <td>850 <a href="/wiki/Nanosecond" title="Nanosecond">ns</a> </td> <td>MOSFET </td> <td><a href="/wiki/Intel" title="Intel">Intel</a> </td> <td>12,000 <a href="/wiki/Nanometre" title="Nanometre">nm</a> </td> <td>PMOS </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-shmj-1970s-sram-49">[49]</a><a href="#cite_note-Pimbley-50">[50]</a><a href="#cite_note-51">[51]</a> </td></tr> <tr> <td>1972 </td> <td>2102 </td> <td>1 <a href="/wiki/Kilobit" class="mw-redirect" title="Kilobit">kbit</a> </td> <td>? </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td>NMOS </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a> </td></tr> <tr> <td rowspan="2">1974 </td> <td>5101 </td> <td>1 kbit </td> <td>800 ns </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-Intel-1978-3-52">[52]</a> </td></tr> <tr> <td>2102A </td> <td>1 kbit </td> <td>350 ns </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td>NMOS (<a href="/wiki/Depletion-load_NMOS_logic" title="Depletion-load NMOS logic">depletion</a>) </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-53">[53]</a> </td></tr> <tr> <td>1975 </td> <td>2114 </td> <td>4 kbit </td> <td>450 ns </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td>NMOS </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-Intel-1978-3-52">[52]</a> </td></tr> <tr> <td rowspan="2">1976 </td> <td>2115 </td> <td>1 kbit </td> <td>70 ns </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td>NMOS (<a href="/wiki/HMOS" class="mw-redirect" title="HMOS">HMOS</a>) </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-shmj-1970s-sram-49">[49]</a> </td></tr> <tr> <td>2147 </td> <td>4 kbit </td> <td>55 ns </td> <td>MOSFET </td> <td>Intel </td> <td>? </td> <td>NMOS (HMOS) </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-hitachi-cmos-54">[54]</a> </td></tr> <tr> <td>1977 </td> <td>? </td> <td>4 kbit </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </td> <td>? </td> <td>CMOS </td> <td><a href="#cite_note-shmj-1970s-sram-49">[49]</a> </td></tr> <tr> <td rowspan="2">1978 </td> <td>HM6147 </td> <td>4 kbit </td> <td>55 ns </td> <td>MOSFET </td> <td><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> </td> <td><a href="/wiki/3_%CE%BCm_process" title="3 μm process">3,000 nm</a> </td> <td>CMOS (<a href="/wiki/CMOS" title="CMOS">twin-well</a>) </td> <td><a href="#cite_note-hitachi-cmos-54">[54]</a> </td></tr> <tr> <td>TMS4016 </td> <td>16 kbit </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> </td> <td>? </td> <td>NMOS </td> <td><a href="#cite_note-shmj-1970s-sram-49">[49]</a> </td></tr> <tr> <td rowspan="2">1980 </td> <td rowspan="2">? </td> <td>16 kbit </td> <td>? </td> <td>MOSFET </td> <td>Hitachi, Toshiba </td> <td rowspan="2">? </td> <td rowspan="2">CMOS </td> <td rowspan="2"><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>64 kbit </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/Panasonic" title="Panasonic">Matsushita</a> </td></tr> <tr> <td>1981 </td> <td>? </td> <td>16 kbit </td> <td>? </td> <td>MOSFET </td> <td>Texas Instruments </td> <td>2,500 nm </td> <td>NMOS </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>October 1981 </td> <td>? </td> <td>4 kbit </td> <td>18 ns </td> <td>MOSFET </td> <td>Matsushita, Toshiba </td> <td>2,000 nm </td> <td>CMOS </td> <td><a href="#cite_note-56">[56]</a> </td></tr> <tr> <td>1982 </td> <td>? </td> <td>64 kbit </td> <td>? </td> <td>MOSFET </td> <td>Intel </td> <td><a href="/wiki/1.5_%CE%BCm_process" title="1.5 μm process">1,500 nm</a> </td> <td>NMOS (HMOS) </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>February 1983 </td> <td>? </td> <td>64 kbit </td> <td>50 ns </td> <td>MOSFET </td> <td><a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a> </td> <td>? </td> <td>CMOS </td> <td><a href="#cite_note-57">[57]</a> </td></tr> <tr> <td>1984 </td> <td>? </td> <td>256 kbit </td> <td>? </td> <td>MOSFET </td> <td>Toshiba </td> <td>1,200 nm </td> <td>CMOS </td> <td><a href="#cite_note-stol-55">[55]</a><a href="#cite_note-Pimbley-50">[50]</a> </td></tr> <tr> <td>1987 </td> <td>? </td> <td>1 <a href="/wiki/Mbit" class="mw-redirect" title="Mbit">Mbit</a> </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/Sony" title="Sony">Sony</a>, Hitachi, <a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a>, Toshiba </td> <td>? </td> <td>CMOS </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>December 1987 </td> <td>? </td> <td>256 kbit </td> <td>10 ns </td> <td><a href="/wiki/BiMOS" class="mw-redirect" title="BiMOS">BiMOS</a> </td> <td>Texas Instruments </td> <td>800 nm </td> <td><a href="/wiki/BiCMOS" title="BiCMOS">BiCMOS</a> </td> <td><a href="#cite_note-58">[58]</a> </td></tr> <tr> <td>1990 </td> <td>? </td> <td>4 Mbit </td> <td>15–23 ns </td> <td>MOSFET </td> <td>NEC, Toshiba, Hitachi, Mitsubishi </td> <td>? </td> <td rowspan="2">CMOS </td> <td rowspan="2"><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>1992 </td> <td>? </td> <td>16 Mbit </td> <td>12–15 ns </td> <td>MOSFET </td> <td><a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a>, NEC </td> <td>400 nm </td></tr> <tr> <td>December 1994 </td> <td>? </td> <td>512 kbit </td> <td>2.5 ns </td> <td>MOSFET </td> <td>IBM </td> <td>? </td> <td>CMOS (<a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a>) </td> <td><a href="#cite_note-59">[59]</a> </td></tr> <tr> <td rowspan="2">1995 </td> <td rowspan="2">? </td> <td>4 Mbit </td> <td>6 ns </td> <td><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> (<a href="/wiki/Static_random-access_memory" title="Static random-access memory">SyncBurst</a>) </td> <td>Hitachi </td> <td>100 nm </td> <td>CMOS </td> <td><a href="#cite_note-smithsonian-japan-60">[60]</a> </td></tr> <tr> <td>256 Mbit </td> <td>? </td> <td>MOSFET </td> <td><a href="/wiki/SK_Hynix" title="SK Hynix">Hyundai</a> </td> <td>? </td> <td>CMOS </td> <td><a href="#cite_note-hynix90s-61">[61]</a> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="DRAM">DRAM</h3></div> <table class="wikitable sortable" style="text-align:center"> <caption><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>) </th> <th>DRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th data-sort-type="number">Area </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td>1965 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/1_bit" class="mw-redirect" title="1 bit">1 bit</a> </td> <td>DRAM (<a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">cell</a>) </td> <td><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-bc-spec-20">[20]</a><a href="#cite_note-bc-21">[21]</a> </td></tr> <tr> <td>1967 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1 bit </td> <td>DRAM (cell) </td> <td><a href="/wiki/IBM" title="IBM">IBM</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/MOSFET" title="MOSFET">MOS</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-Robert_Dennard-23">[23]</a><a href="#cite_note-shmj-mos-47">[47]</a> </td></tr> <tr> <td>1968 </td> <td>? </td> <td><a href="/wiki/256_bit" class="mw-redirect" title="256 bit">256 bit</a> </td> <td>DRAM (<a href="/wiki/Integrated_circuit" title="Integrated circuit">IC</a>) </td> <td><a href="/wiki/Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild</a> </td> <td>? </td> <td><a href="/wiki/PMOS_logic" title="PMOS logic">PMOS</a> </td> <td>? </td> <td><a href="#cite_note-computerhistory1970-10">[10]</a> </td></tr> <tr> <td>1969 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1 bit </td> <td>DRAM (cell) </td> <td><a href="/wiki/Intel" title="Intel">Intel</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>PMOS </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="#cite_note-shmj-mos-47">[47]</a> </td></tr> <tr> <td rowspan="2">1970 </td> <td><a href="/wiki/Intel_1102" class="mw-redirect" title="Intel 1102">1102</a> </td> <td>1 <a href="/wiki/Kilobit" class="mw-redirect" title="Kilobit">kbit</a> </td> <td>DRAM (IC) </td> <td>Intel, <a href="/wiki/Honeywell" title="Honeywell">Honeywell</a> </td> <td>? </td> <td>PMOS </td> <td>? </td> <td><a href="#cite_note-shmj-mos-47">[47]</a> </td></tr> <tr> <td><a href="/wiki/Intel_1103" title="Intel 1103">1103</a> </td> <td>1 kbit </td> <td>DRAM </td> <td>Intel </td> <td>8,000 <a href="/wiki/Nanometre" title="Nanometre">nm</a> </td> <td>PMOS </td> <td>10 mm2 </td> <td><a href="#cite_note-Intel2003-62">[62]</a><a href="#cite_note-HC-63">[63]</a><a href="#cite_note-Lojek-1103-24">[24]</a> </td></tr> <tr> <td rowspan="2">1971 </td> <td>μPD403 </td> <td>1 kbit </td> <td>DRAM </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td>? </td> <td><a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a> </td> <td>? </td> <td><a href="#cite_note-64">[64]</a> </td></tr> <tr> <td>? </td> <td>2 kbit </td> <td>DRAM </td> <td><a href="/wiki/General_Instrument" title="General Instrument">General Instrument</a> </td> <td>? </td> <td>PMOS </td> <td>13 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>1972 </td> <td>2107 </td> <td>4 kbit </td> <td>DRAM </td> <td>Intel </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-Intel-Product-Timeline-48">[48]</a><a href="#cite_note-66">[66]</a> </td></tr> <tr> <td>1973 </td> <td>? </td> <td>8 kbit </td> <td>DRAM </td> <td>IBM </td> <td>? </td> <td>PMOS </td> <td>19 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>1975 </td> <td>2116 </td> <td>16 kbit </td> <td>DRAM </td> <td>Intel </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-67">[67]</a><a href="#cite_note-computerhistory1970-10">[10]</a> </td></tr> <tr> <td>1977 </td> <td>? </td> <td>64 kbit </td> <td>DRAM </td> <td><a href="/wiki/Nippon_Telegraph_and_Telephone" title="Nippon Telegraph and Telephone">NTT</a> </td> <td>? </td> <td>NMOS </td> <td>35 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td rowspan="2">1979 </td> <td>MK4816 </td> <td>16 kbit </td> <td><a href="/wiki/PSRAM" class="mw-redirect" title="PSRAM">PSRAM</a> </td> <td><a href="/wiki/Mostek" title="Mostek">Mostek</a> </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-68">[68]</a> </td></tr> <tr> <td>? </td> <td>64 kbit </td> <td>DRAM </td> <td><a href="/wiki/Siemens" title="Siemens">Siemens</a> </td> <td>? </td> <td><a href="/wiki/VMOS" title="VMOS">VMOS</a> </td> <td>25 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>1980 </td> <td>? </td> <td>256 kbit </td> <td>DRAM </td> <td>NEC, NTT </td> <td>1,000–<a href="/wiki/1.5_%CE%BCm_process" title="1.5 μm process">1,500 nm</a> </td> <td>NMOS </td> <td>34–42 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>1981 </td> <td>? </td> <td>288 kbit </td> <td>DRAM </td> <td>IBM </td> <td>? </td> <td>MOS </td> <td>25 mm2 </td> <td><a href="#cite_note-69">[69]</a> </td></tr> <tr> <td rowspan="2">1983 </td> <td rowspan="2">? </td> <td>64 kbit </td> <td>DRAM </td> <td>Intel </td> <td><a href="/wiki/1.5_%CE%BCm_process" title="1.5 μm process">1,500 nm</a> </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td>20 mm2 </td> <td rowspan="2"><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>256 kbit </td> <td>DRAM </td> <td>NTT </td> <td>? </td> <td>CMOS </td> <td>31 mm2 </td></tr> <tr> <td>January 5, 1984 </td> <td>? </td> <td>8 <a href="/wiki/Mbit" class="mw-redirect" title="Mbit">Mbit</a> </td> <td>DRAM </td> <td><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> </td> <td>? </td> <td>MOS </td> <td>? </td> <td><a href="#cite_note-70">[70]</a><a href="#cite_note-71">[71]</a> </td></tr> <tr> <td rowspan="2">February 1984 </td> <td rowspan="2">? </td> <td rowspan="2">1 Mbit </td> <td rowspan="2">DRAM </td> <td>Hitachi, NEC </td> <td><a href="/wiki/1_%CE%BCm_process" title="1 μm process">1,000 nm</a> </td> <td>NMOS </td> <td>74–76 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a><a href="#cite_note-Robinson-72">[72]</a> </td></tr> <tr> <td>NTT </td> <td><a href="/wiki/800_nm" class="mw-redirect" title="800 nm">800 nm</a> </td> <td>CMOS </td> <td>53 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a><a href="#cite_note-Robinson-72">[72]</a> </td></tr> <tr> <td>1984 </td> <td>TMS4161 </td> <td>64 kbit </td> <td><a href="/wiki/DPRAM" class="mw-redirect" title="DPRAM">DPRAM</a> (<a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a>) </td> <td><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-ti1984-73">[73]</a><a href="#cite_note-74">[74]</a> </td></tr> <tr> <td>January 1985 </td> <td>μPD41264 </td> <td>256 kbit </td> <td>DPRAM (VRAM) </td> <td>NEC </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-75">[75]</a><a href="#cite_note-76">[76]</a> </td></tr> <tr> <td>June 1986 </td> <td>? </td> <td>1 Mbit </td> <td>PSRAM </td> <td>Toshiba </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-77">[77]</a> </td></tr> <tr> <td rowspan="2">1986 </td> <td rowspan="2">? </td> <td rowspan="2">4 Mbit </td> <td rowspan="2">DRAM </td> <td>NEC </td> <td>800 nm </td> <td>NMOS </td> <td>99 mm2 </td> <td rowspan="2"><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>Texas Instruments, Toshiba </td> <td>1,000 nm </td> <td>CMOS </td> <td>100–137 mm2 </td></tr> <tr> <td>1987 </td> <td>? </td> <td>16 Mbit </td> <td>DRAM </td> <td>NTT </td> <td>700 nm </td> <td>CMOS </td> <td>148 mm2 </td> <td><a href="#cite_note-Gealow-65">[65]</a> </td></tr> <tr> <td>October 1988 </td> <td>? </td> <td>512 kbit </td> <td>HSDRAM </td> <td>IBM </td> <td>1,000 nm </td> <td>CMOS </td> <td>78 mm2 </td> <td><a href="#cite_note-78">[78]</a> </td></tr> <tr> <td>1991 </td> <td>? </td> <td>64 Mbit </td> <td>DRAM </td> <td><a href="/wiki/Panasonic" title="Panasonic">Matsushita</a>, <a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a>, <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a>, Toshiba </td> <td>400 nm </td> <td>CMOS </td> <td>? </td> <td rowspan="2"><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>1993 </td> <td>? </td> <td>256 Mbit </td> <td>DRAM </td> <td>Hitachi, NEC </td> <td><a href="/wiki/250_nm" class="mw-redirect" title="250 nm">250 nm</a> </td> <td>CMOS </td> <td>? </td></tr> <tr> <td>1995 </td> <td>? </td> <td>4 Mbit </td> <td>DPRAM (VRAM) </td> <td>Hitachi </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-smithsonian-japan-60">[60]</a> </td></tr> <tr> <td rowspan="2">January 9, 1995 </td> <td rowspan="2">? </td> <td rowspan="2">1 <a href="/wiki/Gbit" class="mw-redirect" title="Gbit">Gbit</a> </td> <td rowspan="2">DRAM </td> <td>NEC </td> <td>250 nm </td> <td>CMOS </td> <td>? </td> <td rowspan="2"><a href="#cite_note-HB19950109-79">[79]</a><a href="#cite_note-smithsonian-japan-60">[60]</a> </td></tr> <tr> <td>Hitachi </td> <td>160 nm </td> <td>CMOS </td> <td>? </td></tr> <tr> <td>1996 </td> <td>? </td> <td>4 Mbit </td> <td><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FRAM</a> </td> <td><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> </td> <td>? </td> <td>NMOS </td> <td>? </td> <td><a href="#cite_note-80">[80]</a> </td></tr> <tr> <td>1997 </td> <td>? </td> <td>4 Gbit </td> <td><a href="/wiki/Quad-level_cell" class="mw-redirect" title="Quad-level cell">QLC</a> </td> <td>NEC </td> <td>150 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>1998 </td> <td>? </td> <td>4 Gbit </td> <td>DRAM </td> <td>Hyundai </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix90s-61">[61]</a> </td></tr> <tr> <td>June 2001 </td> <td>TC51W3216XB </td> <td>32 Mbit </td> <td>PSRAM </td> <td><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-81">[81]</a> </td></tr> <tr> <td>February 2001 </td> <td>? </td> <td>4 Gbit </td> <td>DRAM </td> <td>Samsung </td> <td><a href="/wiki/100_nm" class="mw-redirect" title="100 nm">100 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-stol-55">[55]</a><a href="#cite_note-82">[82]</a> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="SDRAM">SDRAM</h3></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable relarticle mainarticle selfreference noprint">Part of this section is <a href="/wiki/Help:Transclusion" title="Help:Transclusion">transcluded</a> from <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a>. (<a class="external text" href="https://en.wikipedia.org/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit">edit</a> | <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Synchronous_dynamic_random-access_memory&action=history">history</a>)</div> <table class="wikitable sortable" style="text-align:center"> <caption>Synchronous dynamic random-access memory (SDRAM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>)<a href="#cite_note-binpre-83">[83]</a> </th> <th>SDRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th data-sort-type="number">Area </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td>1992 </td> <td>KM48SL2000 </td> <td>16 <a href="/wiki/Megabit" class="mw-redirect" title="Megabit">Mbit</a> </td> <td><a href="/wiki/SDR_SDRAM" class="mw-redirect" title="SDR SDRAM">SDR</a> </td> <td><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> </td> <td>? </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td>? </td> <td><a href="#cite_note-KM48SL2000-84">[84]</a><a href="#cite_note-electronic-design-28">[28]</a> </td></tr> <tr> <td rowspan="3">1996 </td> <td>MSM5718C50 </td> <td>18 Mbit </td> <td><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a> </td> <td><a href="/wiki/Oki_Electric_Industry" title="Oki Electric Industry">Oki</a> </td> <td>? </td> <td>CMOS </td> <td>325 mm2 </td> <td><a href="#cite_note-oki-rdram-85">[85]</a> </td></tr> <tr> <td><a href="/wiki/Nintendo_64_technical_specifications" class="mw-redirect" title="Nintendo 64 technical specifications">N64 RDRAM</a> </td> <td>36 Mbit </td> <td>RDRAM </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-86">[86]</a> </td></tr> <tr> <td>? </td> <td>1024 Mbit </td> <td>SDR </td> <td><a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a> </td> <td><a href="/wiki/180_nanometer" class="mw-redirect" title="180 nanometer">150 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>1997 </td> <td>? </td> <td>1024 Mbit </td> <td>SDR </td> <td><a href="/wiki/Hyundai_Electronics" class="mw-redirect" title="Hyundai Electronics">Hyundai</a> </td> <td>? </td> <td><a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a> </td> <td>? </td> <td><a href="#cite_note-hynix90s-61">[61]</a> </td></tr> <tr> <td>1998 </td> <td>MD5764802 </td> <td>64 Mbit </td> <td>RDRAM </td> <td>Oki </td> <td>? </td> <td>CMOS </td> <td>325 mm2 </td> <td><a href="#cite_note-oki-rdram-85">[85]</a> </td></tr> <tr> <td>March 1998 </td> <td>Direct RDRAM </td> <td>72 Mbit </td> <td>RDRAM </td> <td><a href="/wiki/Rambus" title="Rambus">Rambus</a> </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-87">[87]</a> </td></tr> <tr> <td>June 1998 </td> <td>? </td> <td>64 Mbit </td> <td><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a> </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung98-88">[88]</a><a href="#cite_note-samsung99-89">[89]</a><a href="#cite_note-phys-90">[90]</a> </td></tr> <tr> <td rowspan="2">1998 </td> <td rowspan="2">? </td> <td>64 Mbit </td> <td>DDR </td> <td>Hyundai </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix90s-61">[61]</a> </td></tr> <tr> <td>128 Mbit </td> <td>SDR </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung-history-91">[91]</a><a href="#cite_note-samsung99-89">[89]</a> </td></tr> <tr> <td rowspan="2">1999 </td> <td rowspan="2">? </td> <td>128 Mbit </td> <td>DDR </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung99-89">[89]</a> </td></tr> <tr> <td>1024 Mbit </td> <td>DDR </td> <td>Samsung </td> <td><a href="/wiki/130_nanometer" class="mw-redirect" title="130 nanometer">140 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>2000 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">GS eDRAM</a> </td> <td>32 Mbit </td> <td><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> </td> <td><a href="/wiki/Sony" title="Sony">Sony</a>, <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </td> <td><a href="/wiki/180_nm" class="mw-redirect" title="180 nm">180 nm</a> </td> <td>CMOS </td> <td>279 mm2 </td> <td><a href="#cite_note-sony2003-92">[92]</a> </td></tr> <tr> <td rowspan="2">2001 </td> <td rowspan="2">? </td> <td>288 Mbit </td> <td>RDRAM </td> <td>Hynix </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td>? </td> <td><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> </td> <td>Samsung </td> <td><a href="/wiki/100_nm" class="mw-redirect" title="100 nm">100 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-phys-90">[90]</a><a href="#cite_note-stol-55">[55]</a> </td></tr> <tr> <td>2002 </td> <td>? </td> <td>256 Mbit </td> <td>SDR </td> <td>Hynix </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td rowspan="5">2003 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">EE+GS eDRAM</a> </td> <td>32 Mbit </td> <td>eDRAM </td> <td>Sony, Toshiba </td> <td><a href="/wiki/90_nm" class="mw-redirect" title="90 nm">90 nm</a> </td> <td>CMOS </td> <td>86 mm2 </td> <td><a href="#cite_note-sony2003-92">[92]</a> </td></tr> <tr> <td rowspan="4">? </td> <td>72 Mbit </td> <td><a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> </td> <td>Samsung </td> <td>90 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-94">[94]</a> </td></tr> <tr> <td rowspan="2">512 Mbit </td> <td rowspan="2">DDR2 </td> <td>Hynix </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td><a href="/wiki/Elpida_Memory" class="mw-redirect" title="Elpida Memory">Elpida</a> </td> <td><a href="/wiki/110_nanometer" class="mw-redirect" title="110 nanometer">110 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-95">[95]</a> </td></tr> <tr> <td>1024 Mbit </td> <td>DDR2 </td> <td>Hynix </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td>2004 </td> <td>? </td> <td>2048 Mbit </td> <td>DDR2 </td> <td>Samsung </td> <td>80 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung2004-96">[96]</a> </td></tr> <tr> <td rowspan="3">2005 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">EE+GS eDRAM</a> </td> <td>32 Mbit </td> <td>eDRAM </td> <td>Sony, Toshiba </td> <td><a href="/wiki/65_nm" class="mw-redirect" title="65 nm">65 nm</a> </td> <td>CMOS </td> <td>86 mm2 </td> <td><a href="#cite_note-impress-97">[97]</a> </td></tr> <tr> <td><a href="/wiki/Xenos_(graphics_chip)" title="Xenos (graphics chip)">Xenos eDRAM</a> </td> <td>80 Mbit </td> <td>eDRAM </td> <td>NEC </td> <td>90 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-98">[98]</a> </td></tr> <tr> <td>? </td> <td>512 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>80 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-phys-90">[90]</a><a href="#cite_note-samsung2000s-99">[99]</a> </td></tr> <tr> <td>2006 </td> <td>? </td> <td>1024 Mbit </td> <td>DDR2 </td> <td>Hynix </td> <td>60 nm </td> <td rowspan="2">CMOS </td> <td rowspan="2">? </td> <td rowspan="2"><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td>2008 </td> <td>? </td> <td>? </td> <td><a href="/wiki/LPDDR2" class="mw-redirect" title="LPDDR2">LPDDR2</a> </td> <td>Hynix </td> <td>? </td></tr> <tr> <td>April 2008 </td> <td>? </td> <td>8192 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>50 nm </td> <td>CMOS </td> <td>? </td> <td rowspan="2"><a href="#cite_note-100">[100]</a> </td></tr> <tr> <td>2008 </td> <td>? </td> <td>16384 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>50 nm </td> <td>CMOS </td> <td>? </td></tr> <tr> <td rowspan="2">2009 </td> <td rowspan="2">? </td> <td>? </td> <td>DDR3 </td> <td>Hynix </td> <td><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">44 nm</a> </td> <td rowspan="2">CMOS </td> <td rowspan="2">? </td> <td rowspan="2"><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td>2048 Mbit </td> <td>DDR3 </td> <td>Hynix </td> <td><a href="/wiki/40_nanometer" class="mw-redirect" title="40 nanometer">40 nm</a> </td></tr> <tr> <td rowspan="2">2011 </td> <td rowspan="2">? </td> <td>16384 Mbit </td> <td>DDR3 </td> <td>Hynix </td> <td>40 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2010s-101">[101]</a> </td></tr> <tr> <td>2048 Mbit </td> <td><a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> </td> <td>Hynix </td> <td><a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">30 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2010s-101">[101]</a> </td></tr> <tr> <td>2013 </td> <td>? </td> <td>? </td> <td><a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a> </td> <td>Samsung </td> <td><a href="/w/index.php?title=20_nm&action=edit&redlink=1" class="new" title="20 nm (page does not exist)">20 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-hynix2010s-101">[101]</a> </td></tr> <tr> <td>2014 </td> <td>? </td> <td>8192 Mbit </td> <td>LPDDR4 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-102">[102]</a> </td></tr> <tr> <td>2015 </td> <td>? </td> <td>12 Gbit </td> <td>LPDDR4 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung-history-91">[91]</a> </td></tr> <tr> <td rowspan="2">2018 </td> <td rowspan="2">? </td> <td>8192 Mbit </td> <td><a href="/wiki/LPDDR#LP-DDR5" title="LPDDR">LPDDR5</a> </td> <td>Samsung </td> <td><a href="/wiki/10_nm_process" title="10 nm process">10 nm</a> </td> <td><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> </td> <td>? </td> <td><a href="#cite_note-103">[103]</a> </td></tr> <tr> <td>128 Gbit </td> <td>DDR4 </td> <td>Samsung </td> <td>10 nm </td> <td>FinFET </td> <td>? </td> <td><a href="#cite_note-104">[104]</a> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="SGRAM_and_HBM">SGRAM and HBM</h3></div> <table class="wikitable sortable" style="text-align:center"> <caption><a href="/wiki/Synchronous_graphics_random-access_memory" class="mw-redirect" title="Synchronous graphics random-access memory">Synchronous graphics random-access memory</a> (SGRAM) and <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>)<a href="#cite_note-binpre-83">[83]</a> </th> <th>SDRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th data-sort-type="number">Area </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td>November 1994 </td> <td>HM5283206 </td> <td>8 Mbit </td> <td><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> (<a href="/wiki/SDR_SDRAM" class="mw-redirect" title="SDR SDRAM">SDR</a>) </td> <td><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> </td> <td><a href="/wiki/350_nm" class="mw-redirect" title="350 nm">350 nm</a> </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td>58 mm2 </td> <td><a href="#cite_note-HM5283206-105">[105]</a><a href="#cite_note-106">[106]</a> </td></tr> <tr> <td>December 1994 </td> <td>μPD481850 </td> <td>8 Mbit </td> <td>SGRAM (SDR) </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td>? </td> <td>CMOS </td> <td>280 mm2 </td> <td><a href="#cite_note-D481850-107">[107]</a><a href="#cite_note-nec1995-108">[108]</a> </td></tr> <tr> <td>1997 </td> <td>μPD4811650 </td> <td>16 Mbit </td> <td>SGRAM (SDR) </td> <td>NEC </td> <td>350 nm </td> <td>CMOS </td> <td>280 mm2 </td> <td><a href="#cite_note-109">[109]</a><a href="#cite_note-110">[110]</a> </td></tr> <tr> <td>September 1998 </td> <td>? </td> <td>16 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a>) </td> <td><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung98-88">[88]</a> </td></tr> <tr> <td>1999 </td> <td>KM4132G112 </td> <td>32 Mbit </td> <td>SGRAM (SDR) </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>280 mm2 </td> <td><a href="#cite_note-111">[111]</a> </td></tr> <tr> <td>2002 </td> <td>? </td> <td>128 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a>) </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-samsung2003-112">[112]</a> </td></tr> <tr> <td rowspan="2">2003 </td> <td rowspan="2">? </td> <td rowspan="2">256 Mbit </td> <td>SGRAM (GDDR2) </td> <td rowspan="2">Samsung </td> <td rowspan="2">? </td> <td rowspan="2">CMOS </td> <td rowspan="2">? </td> <td rowspan="2"><a href="#cite_note-samsung2003-112">[112]</a> </td></tr> <tr> <td>SGRAM (<a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>) </td></tr> <tr> <td>March 2005 </td> <td>K4D553238F </td> <td>256 Mbit </td> <td>SGRAM (GDDR) </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>77 mm2 </td> <td><a href="#cite_note-113">[113]</a> </td></tr> <tr> <td>October 2005 </td> <td>? </td> <td>256 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>) </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-114">[114]</a> </td></tr> <tr> <td>2005 </td> <td>? </td> <td>512 Mbit </td> <td>SGRAM (GDDR4) </td> <td><a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a> </td> <td>? </td> <td rowspan="3">CMOS </td> <td rowspan="3">? </td> <td rowspan="3"><a href="#cite_note-hynix2000s-93">[93]</a> </td></tr> <tr> <td>2007 </td> <td>? </td> <td>1024 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>) </td> <td>Hynix </td> <td><a href="/wiki/65_nanometer" class="mw-redirect" title="65 nanometer">60 nm</a> </td></tr> <tr> <td>2009 </td> <td>? </td> <td>2048 Mbit </td> <td>SGRAM (GDDR5) </td> <td>Hynix </td> <td><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">40 nm</a> </td></tr> <tr> <td>2010 </td> <td>K4W1G1646G </td> <td>1024 Mbit </td> <td>SGRAM (GDDR3) </td> <td>Samsung </td> <td>? </td> <td>CMOS </td> <td>100 mm2 </td> <td><a href="#cite_note-115">[115]</a> </td></tr> <tr> <td>2012 </td> <td>? </td> <td>4096 Mbit </td> <td>SGRAM (GDDR3) </td> <td rowspan="2"><a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> </td> <td rowspan="2">? </td> <td rowspan="2">CMOS </td> <td rowspan="2">? </td> <td rowspan="2"><a href="#cite_note-hynix2010s-101">[101]</a> </td></tr> <tr> <td>2013 </td> <td>? </td> <td>? </td> <td><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> </td></tr> <tr> <td>March 2016 </td> <td>MT58K256M32JA </td> <td>8 Gbit </td> <td>SGRAM (<a href="/wiki/GDDR5X" class="mw-redirect" title="GDDR5X">GDDR5X</a>) </td> <td><a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a> </td> <td>20 nm </td> <td>CMOS </td> <td>140 mm2 </td> <td><a href="#cite_note-116">[116]</a> </td></tr> <tr> <td>June 2016 </td> <td>? </td> <td>32 Gbit </td> <td><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a> </td> <td>Samsung </td> <td><a href="/w/index.php?title=20_nm&action=edit&redlink=1" class="new" title="20 nm (page does not exist)">20 nm</a> </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-Shilov2017-117">[117]</a><a href="#cite_note-118">[118]</a> </td></tr> <tr> <td>2017 </td> <td>? </td> <td>64 Gbit </td> <td>HBM2 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td>? </td> <td><a href="#cite_note-Shilov2017-117">[117]</a> </td></tr> <tr> <td>January 2018 </td> <td>K4ZAF325BM </td> <td>16 Gbit </td> <td>SGRAM (<a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a>) </td> <td>Samsung </td> <td><a href="/wiki/10_nm_process" title="10 nm process">10 nm</a> </td> <td><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> </td> <td>225 mm2 </td> <td><a href="#cite_note-119">[119]</a><a href="#cite_note-tr_gddr6-120">[120]</a><a href="#cite_note-121">[121]</a> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><a href="/wiki/File:Noun-technology.svg" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/29px-Noun-technology.svg.png" decoding="async" width="29" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/43px-Noun-technology.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/57px-Noun-technology.svg.png 2x" data-file-width="90" data-file-height="88" /></a><a href="/wiki/Portal:Technology" title="Portal:Technology">Technology portal</a></li></ul> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 30em;"> <ul><li><a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a> (CL)</li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li> <li><a href="/wiki/Multi-channel_memory_architecture" title="Multi-channel memory architecture">Multi-channel memory architecture</a></li> <li><a href="/wiki/Registered_memory" title="Registered memory">Registered/buffered memory</a></li> <li><a href="/wiki/RAM_parity" title="RAM parity">RAM parity</a></li> <li><a href="/wiki/List_of_device_bit_rates#Memory_Interconnect/RAM_buses" class="mw-redirect" title="List of device bit rates">Memory Interconnect/RAM buses</a></li> <li><a href="/wiki/Memory_geometry" title="Memory geometry">Memory geometry</a></li> <li><a href="/wiki/Chip_creep" title="Chip creep">Chip creep</a></li> <li><a href="/wiki/Read-mostly_memory" title="Read-mostly memory">Read-mostly memory</a> (RMM)</li> <li><a href="/wiki/Electrochemical_random-access_memory" class="mw-redirect" title="Electrochemical random-access memory">Electrochemical random-access memory</a></li></ul></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output 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Norman, "Solid State Switching and Memory Apparatus", published 9 February 1971<span class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.number=3562721&rft.cc=US&rft.title=Solid+State+Switching+and+Memory+Apparatus&rft.inventor=Robert+H.+Norman&rft.appldate=5 March 1963&rft.pubdate=9 February 1971&rft.prioritydate=5 March 1963">  </li> <li id="cite_note-ibm100-18">^ <a href="#cite_ref-ibm100_18-0">a</a> <a href="#cite_ref-ibm100_18-1">b</a> <a href="#cite_ref-ibm100_18-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram/">"DRAM"</a>. IBM100. <a href="/wiki/IBM" title="IBM">IBM</a>. 9 August 2017. Retrieved 20 September 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=IBM100&rft.atitle=DRAM&rft.date=2017-08-09&rft_id=https%3A%2F%2Fwww.ibm.com%2Fibm%2Fhistory%2Fibm100%2Fus%2Fen%2Ficons%2Fdram%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-19"><a href="#cite_ref-19">^</a> <a rel="nofollow" class="external text" href="http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator">Toscal BC-1411 calculator</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator">Archived</a> 2017-07-29 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, <a href="/wiki/Science_Museum,_London" title="Science Museum, London">Science Museum, London</a>. </li> <li id="cite_note-bc-spec-20">^ <a href="#cite_ref-bc-spec_20-0">a</a> <a href="#cite_ref-bc-spec_20-1">b</a> <a href="#cite_ref-bc-spec_20-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.oldcalculatormuseum.com/s-toshbc1411.html">"Spec Sheet for Toshiba "TOSCAL" BC-1411"</a>. Old Calculator Web Museum. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html">Archived</a> from the original on 3 July 2017. Retrieved 8 May 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Old+Calculator+Web+Museum&rft.atitle=Spec+Sheet+for+Toshiba+%22TOSCAL%22+BC-1411&rft_id=http%3A%2F%2Fwww.oldcalculatormuseum.com%2Fs-toshbc1411.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-bc-21">^ <a href="#cite_ref-bc_21-0">a</a> <a href="#cite_ref-bc_21-1">b</a> <a href="#cite_ref-bc_21-2">c</a> <a rel="nofollow" class="external text" href="http://www.oldcalculatormuseum.com/toshbc1411.html">Toshiba "Toscal" BC-1411 Desktop Calculator</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html">Archived</a> 2007-05-20 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </li> <li id="cite_note-22"><a href="#cite_ref-22">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/">"1966: Semiconductor RAMs Serve High-speed Storage Needs"</a>. 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The resulting product had a 2,400 μm2 memory cell size, a die size just under 10 mm2, and sold for around $21.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=History+of+Semiconductor+Engineering&rft.pages=362-363&rft.pub=Springer+Science+%26+Business+Media&rft.date=2007&rft.isbn=9783540342588&rft.aulast=Lojek&rft.aufirst=Bo&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D2cu1Oh_COv8C%26pg%3DPA362&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-25"><a href="#cite_ref-25">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBellis" class="citation web cs1">Bellis, Mary. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm">"The Invention of the Intel 1103"</a>. Archived from <a rel="nofollow" class="external text" href="http://inventors.about.com/library/weekly/aa100898.htm">the original</a> on 2020-03-14. Retrieved 2015-07-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+Invention+of+the+Intel+1103&rft.aulast=Bellis&rft.aufirst=Mary&rft_id=http%3A%2F%2Finventors.about.com%2Flibrary%2Fweekly%2Faa100898.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-26"><a href="#cite_ref-26">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFP._Darche2020" class="citation book cs1">P. Darche (2020). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=rLC9zQEACAAJ">Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer</a>. John Wiley & Sons. p. 59. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9781786305633" title="Special:BookSources/9781786305633"><bdi>9781786305633</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Microprocessor%3A+Prolegomenes+-+Calculation+and+Storage+Functions+-+Calculation+Models+and+Computer&rft.pages=59&rft.pub=John+Wiley+%26+Sons&rft.date=2020&rft.isbn=9781786305633&rft.au=P.+Darche&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DrLC9zQEACAAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-27"><a href="#cite_ref-27">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFB._JacobS._W._NgD._T._Wang2008" class="citation book cs1">B. Jacob; S. W. Ng; D. T. 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Morgan Kaufmann. p. 324. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9780080553849" title="Special:BookSources/9780080553849"><bdi>9780080553849</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Memory+Systems%3A+Cache%2C+DRAM%2C+Disk&rft.pages=324&rft.pub=Morgan+Kaufmann&rft.date=2008&rft.isbn=9780080553849&rft.au=B.+Jacob&rft.au=S.+W.+Ng&rft.au=D.+T.+Wang&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DSrP3aWed-esC&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-electronic-design-28">^ <a href="#cite_ref-electronic-design_28-0">a</a> <a href="#cite_ref-electronic-design_28-1">b</a> <a href="#cite_ref-electronic-design_28-2">c</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation journal cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=QmpJAQAAIAAJ">"Electronic Design"</a>. <a href="/wiki/Electronic_Design" class="mw-redirect" title="Electronic Design">Electronic Design</a>. 41 (15–21). Hayden Publishing Company. 1993. <q>The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Electronic+Design&rft.atitle=Electronic+Design&rft.volume=41&rft.issue=15%E2%80%9321&rft.date=1993&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DQmpJAQAAIAAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-29"><a href="#cite_ref-29">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html">"KM48SL2000-7 Datasheet"</a>. <a href="/wiki/Samsung" title="Samsung">Samsung</a>. August 1992. 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Jones & Bartlett Learning. 2006. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7637-3769-6" title="Special:BookSources/978-0-7637-3769-6"><bdi>978-0-7637-3769-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+Essentials+of+Computer+Organization+and+Architecture&rft.pub=Jones+%26+Bartlett+Learning&rft.date=2006&rft.isbn=978-0-7637-3769-6&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DQGPHAl9GE-IC%26dq%3Dsize%2Bof%2Ba%2Bmemory%2Baddress%26pg%3DPA321&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-34"><a href="#cite_ref-34">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAnderson2020" class="citation book cs1">Anderson, Alexander John (25 October 2020). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=-vQCEAAAQBAJ">Foundations of Computer Technology</a>. CRC Press. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-000-15371-2" title="Special:BookSources/978-1-000-15371-2"><bdi>978-1-000-15371-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Foundations+of+Computer+Technology&rft.pub=CRC+Press&rft.date=2020-10-25&rft.isbn=978-1-000-15371-2&rft.aulast=Anderson&rft.aufirst=Alexander+John&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D-vQCEAAAQBAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-35"><a href="#cite_ref-35">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://hardwarehell.com/articles/shadowram.htm">"Shadow Ram"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20061029162135/http://hardwarehell.com/articles/shadowram.htm">Archived</a> from the original on 2006-10-29. Retrieved 2007-07-24.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Shadow+Ram&rft_id=http%3A%2F%2Fhardwarehell.com%2Farticles%2Fshadowram.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-36"><a href="#cite_ref-36">^</a> The term was coined in <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf">"Archived copy"</a> (PDF). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120406111104/http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf">Archived</a> (PDF) from the original on 2012-04-06. Retrieved 2011-12-14.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Archived+copy&rft_id=http%3A%2F%2Fwww.eecs.ucf.edu%2F~lboloni%2FTeaching%2FEEL5708_2006%2Fslides%2Fwulf94.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: archived copy as title (<a href="/wiki/Category:CS1_maint:_archived_copy_as_title" title="Category:CS1 maint: archived copy as title">link</a>). </li> <li id="cite_note-37"><a href="#cite_ref-37">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf">"Platform 2015: Intel Processor and Platform Evolution for the Next Decade"</a> (PDF). March 2, 2005. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf">Archived</a> (PDF) from the original on April 27, 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Platform+2015%3A+Intel+Processor+and+Platform+Evolution+for+the+Next+Decade&rft.date=2005-03-02&rft_id=http%3A%2F%2Fepic.hpi.uni-potsdam.de%2Fpub%2FHome%2FTrendsAndConceptsII2010%2FHW_Trends_borkar_2015.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-38"><a href="#cite_ref-38">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAgarwalHrishikeshKecklerBurger2000" class="citation conference cs1">Agarwal, Vikas; Hrishikesh, M. S.; Keckler, Stephen W.; Burger, Doug (June 10–14, 2000). <a rel="nofollow" class="external text" href="http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf">"Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"</a> (PDF). Proceedings of the 27th Annual International Symposium on Computer Architecture. <a rel="nofollow" class="external text" href="https://dl.acm.org/citation.cfm?id=339647">27th Annual International Symposium on Computer Architecture</a>. Vancouver, BC. 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John Wiley & Sons. p. 790. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9783527409273" title="Special:BookSources/9783527409273"><bdi>9783527409273</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160801114150/https://books.google.com/books?id=1PgYS7zDCM8C&pg=PA790&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CDYQ6AEwAg#v=onepage&q=processor-memory%20performance%20gap&f=false">Archived</a> from the original on August 1, 2016. Retrieved March 31, 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Nanoelectronics+and+Information+Technology&rft.pages=790&rft.pub=John+Wiley+%26+Sons&rft.date=2012&rft.isbn=9783527409273&rft.au=Rainer+Waser&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D1PgYS7zDCM8C%26q%3Dprocessor-memory%2Bperformance%2Bgap%26pg%3DPA790&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-40"><a href="#cite_ref-40">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChris_Jesshope_and_Colin_Egan2006" class="citation book cs1">Chris Jesshope and Colin Egan (2006). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=0IY7LW5J4JgC&q=processor-memory+performance+gap&pg=PA109">Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings</a>. Springer. p. 109. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9783540400561" title="Special:BookSources/9783540400561"><bdi>9783540400561</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160801135254/https://books.google.com/books?id=0IY7LW5J4JgC&pg=PA109&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CEkQ6AEwBg#v=onepage&q=processor-memory%20performance%20gap&f=false">Archived</a> from the original on August 1, 2016. Retrieved March 31, 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Advances+in+Computer+Systems+Architecture%3A+11th+Asia-Pacific+Conference%2C+ACSAC+2006%2C+Shanghai%2C+China%2C+September+6-8%2C+2006%2C+Proceedings&rft.pages=109&rft.pub=Springer&rft.date=2006&rft.isbn=9783540400561&rft.au=Chris+Jesshope+and+Colin+Egan&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D0IY7LW5J4JgC%26q%3Dprocessor-memory%2Bperformance%2Bgap%26pg%3DPA109&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-41"><a href="#cite_ref-41">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAhmed_Amine_Jerraya_and_Wayne_Wolf2005" class="citation book cs1">Ahmed Amine Jerraya and Wayne Wolf (2005). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=7i9Z69lrYBoC&q=processor-memory+performance+gap&pg=PA90">Multiprocessor Systems-on-chips</a>. Morgan Kaufmann. pp. 90–91. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9780123852519" title="Special:BookSources/9780123852519"><bdi>9780123852519</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160801105357/https://books.google.com/books?id=7i9Z69lrYBoC&pg=PA90&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CFMQ6AEwCA#v=onepage&q=processor-memory%20performance%20gap&f=false">Archived</a> from the original on August 1, 2016. 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Retrieved 2019-03-28.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=MiniTool&rft.atitle=SSD+Prices+Continue+to+Fall%2C+Now+Upgrade+Your+Hard+Drive%21&rft.date=2018-09-03&rft_id=https%3A%2F%2Fwww.minitool.com%2Fnews%2Fssd-prices-fall.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-44"><a href="#cite_ref-44">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCoppock2017" class="citation web cs1">Coppock, Mark (31 January 2017). <a rel="nofollow" class="external text" href="https://www.digitaltrends.com/computing/ram-prices-are-increasing-until-third-quarter-2017/">"If you're buying or upgrading your PC, expect to pay more for RAM"</a>. www.digitaltrends.com. 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Retrieved 16 July 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=AnandTech&rft.atitle=Micron+Begins+to+Sample+GDDR5X+Memory%2C+Unveils+Specs+of+Chips&rft.date=2016-03-29&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F10193%2Fmicron-begins-to-sample-gddr5x-memory&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-Shilov2017-117">^ <a href="#cite_ref-Shilov2017_117-0">a</a> <a href="#cite_ref-Shilov2017_117-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShilov2017" class="citation news cs1">Shilov, Anton (July 19, 2017). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume">"Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. Retrieved 29 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=AnandTech&rft.atitle=Samsung+Increases+Production+Volumes+of+8+GB+HBM2+Chips+Due+to+Growing+Demand&rft.date=2017-07-19&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F11643%2Fsamsung-increases-8gb-hbm2-production-volume&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-118"><a href="#cite_ref-118">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://samsungsemiconductor-us.com/hbm/">"HBM"</a>. <a href="/wiki/Samsung_Semiconductor" class="mw-redirect" title="Samsung Semiconductor">Samsung Semiconductor</a>. <a href="/wiki/Samsung" title="Samsung">Samsung</a>. Retrieved 16 July 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Samsung+Semiconductor&rft.atitle=HBM&rft_id=https%3A%2F%2Fsamsungsemiconductor-us.com%2Fhbm%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-119"><a href="#cite_ref-119">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems">"Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems"</a>. <a href="/wiki/Samsung" title="Samsung">Samsung</a>. January 18, 2018. Retrieved 15 July 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Samsung+Electronics+Starts+Producing+Industry%27s+First+16-Gigabit+GDDR6+for+Advanced+Graphics+Systems&rft.date=2018-01-18&rft_id=https%3A%2F%2Fnews.samsung.com%2Fglobal%2Fsamsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-tr_gddr6-120"><a href="#cite_ref-tr_gddr6_120-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKillian2018" class="citation news cs1">Killian, Zak (18 January 2018). <a rel="nofollow" class="external text" href="https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory">"Samsung fires up its foundries for mass production of GDDR6 memory"</a>. Tech Report. Retrieved 18 January 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Samsung+fires+up+its+foundries+for+mass+production+of+GDDR6+memory&rft.date=2018-01-18&rft.aulast=Killian&rft.aufirst=Zak&rft_id=https%3A%2F%2Ftechreport.com%2Fnews%2F33129%2Fsamsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> <li id="cite_note-121"><a href="#cite_ref-121">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/">"Samsung Begins Producing The Fastest GDDR6 Memory In The World"</a>. Wccftech. 18 January 2018. Retrieved 16 July 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Wccftech&rft.atitle=Samsung+Begins+Producing+The+Fastest+GDDR6+Memory+In+The+World&rft.date=2018-01-18&rft_id=https%3A%2F%2Fwccftech.com%2Fsamsung-gddr6-16gb-18gbps-mass-production-official%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARandom-access+memory" class="Z3988"> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div> <ul><li><a href="/wiki/File:Commons-logo.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/24px-Commons-logo.svg.png 2x" data-file-width="1024" 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title="Touchscreen">Touchscreen</a></li> <li><a href="/wiki/Trackball" title="Trackball">Trackball</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_keyboard" title="Computer keyboard">Keyboard</a></li> <li><a href="/wiki/Image_scanner" title="Image scanner">Image scanner</a></li> <li><a href="/wiki/Graphics_card" title="Graphics card">Graphics card</a> <ul><li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></li></ul></li> <li><a href="/wiki/Microphone" title="Microphone">Microphone</a></li> <li><a href="/wiki/Refreshable_braille_display" title="Refreshable braille display">Refreshable braille display</a></li> <li><a href="/wiki/Sound_card" title="Sound card">Sound card</a> <ul><li><a href="/wiki/Sound_chip" title="Sound chip">Sound chip</a></li></ul></li> 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title="Hard disk drive">HDD</a></li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">SSD</a> (<a href="/wiki/SATA" title="SATA">SATA</a> / <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a>)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">SSHD</a></li></ul></li> <li><a href="/wiki/Power_supply_unit_(computer)" title="Power supply unit (computer)">Power supply</a> <ul><li><a href="/wiki/Switched-mode_power_supply" title="Switched-mode power supply">SMPS</a></li></ul></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> <ul><li><a href="/wiki/Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li> <li><a href="/wiki/Voltage_regulator_module" title="Voltage regulator module">VRM</a></li></ul></li> <li><a href="/wiki/Network_interface_controller" title="Network interface controller">Network interface controller</a></li> <li><a href="/wiki/Fax_modem" title="Fax modem">Fax modem</a></li> <li><a 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title="DisplayPort">DisplayPort</a></li> <li><a href="/wiki/HDMI" title="HDMI">HDMI</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IEEE_1394" title="IEEE 1394">FireWire</a> (IEEE 1394)</li> <li><a href="/wiki/Parallel_port" title="Parallel port">Parallel port</a></li> <li><a href="/wiki/Serial_port" title="Serial port">Serial port</a></li> <li><a href="/wiki/Game_port" title="Game port">Game port</a></li> <li><a href="/wiki/PS/2_port" title="PS/2 port">PS/2 port</a></li> <li><a href="/wiki/Serial_ATA#eSATA" class="mw-redirect" title="Serial ATA">eSATA</a></li> <li><a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a></li> <li><a href="/wiki/VGA_connector" title="VGA connector">VGA</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" 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