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dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Integrated circuit logic family</div> <p class="mw-empty-elt"> </p> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:ECL.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/ECL.svg/350px-ECL.svg.png" decoding="async" width="350" height="272" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/ECL.svg/525px-ECL.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b2/ECL.svg/700px-ECL.svg.png 2x" data-file-width="851" data-file-height="661" /></a><figcaption>Motorola ECL 10,000 basic gate circuit diagram from 1972.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Note the Q5 and Q6 emitters coupled to the output.</figcaption></figure> <p>In electronics, <b>emitter-coupled logic</b> (<b>ECL</b>) is a high-speed <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> bipolar transistor <a href="/wiki/Logic_family" title="Logic family">logic family</a>. ECL uses an overdriven <a href="/wiki/Bipolar_junction_transistor" title="Bipolar junction transistor">bipolar junction transistor</a> (BJT) differential amplifier with single-ended input and limited emitter current to avoid the <a href="/wiki/Bipolar_junction_transistor#Regions_of_operation" title="Bipolar junction transistor">saturated</a> (fully on) region of operation and the resulting slow turn-off behavior.<sup id="cite_ref-unitd04_2-0" class="reference"><a href="#cite_note-unitd04-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called <i>current-steering logic</i> (CSL),<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> <i>current-mode logic</i> (CML)<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> or <i>current-switch emitter-follower</i> (CSEF) logic.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>In ECL, the transistors are never in saturation, the input and output voltages have a small swing (0.8 V), the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, <a href="/wiki/Gate_delay" class="mw-redirect" title="Gate delay">gate delays</a> are low, and the <a href="/wiki/Fanout" class="mw-redirect" title="Fanout">fanout</a> capability is high.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> In addition, the essentially constant current draw of the differential amplifiers minimizes delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count. </p><p>ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent. </p><p>The equivalent of emitter-coupled logic made from <a href="/wiki/Field-effect_transistor" title="Field-effect transistor">FETs</a> is called <a href="/wiki/Source-coupled_logic" class="mw-redirect" title="Source-coupled logic">source-coupled logic</a> (SCFL).<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p><p>A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:CurrentSwitchLogic.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/06/CurrentSwitchLogic.svg/350px-CurrentSwitchLogic.svg.png" decoding="async" width="350" height="248" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/06/CurrentSwitchLogic.svg/525px-CurrentSwitchLogic.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/06/CurrentSwitchLogic.svg/700px-CurrentSwitchLogic.svg.png 2x" data-file-width="1052" data-file-height="744" /></a><figcaption>Yourke's current switch (around 1955)<sup id="cite_ref-Rymaszewski_9-0" class="reference"><a href="#cite_note-Rymaszewski-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></figcaption></figure> <p>ECL was invented in August 1956 at <a href="/wiki/IBM" title="IBM">IBM</a> by Hannon S. Yourke.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Originally called <i>current-steering logic</i>, it was used in the <a href="/wiki/IBM_7030_Stretch" title="IBM 7030 Stretch">Stretch</a>, <a href="/wiki/IBM_7090" title="IBM 7090">IBM 7090</a>, and <a href="/wiki/IBM_7090#IBM_7094_and_IBM_7040/7044" title="IBM 7090">IBM 7094</a> computers.<sup id="cite_ref-Rymaszewski_9-1" class="reference"><a href="#cite_note-Rymaszewski-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> The logic was also called a current-mode circuit.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> It was also used to make the IBM Advanced <a href="/wiki/Solid_Logic_Technology" title="Solid Logic Technology">Solid Logic Technology</a> (ASLT) circuits in the IBM 360/91.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ASLT_14-0" class="reference"><a href="#cite_note-ASLT-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Blocks_15-0" class="reference"><a href="#cite_note-Blocks-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p>Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level."<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> In Yourke's design, the two logic reference levels differed by 3 volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."<sup id="cite_ref-Rymaszewski_9-2" class="reference"><a href="#cite_note-Rymaszewski-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>Instead of alternating NPN and PNP stages, another coupling method employed <a href="/wiki/Zener_diode" title="Zener diode">Zener diodes</a> and resistors to shift the output logic levels to be the same as the input logic levels.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p><p>Beginning in the early 1960s, ECL circuits were implemented on <a href="/wiki/Monolithic_integrated_circuit" class="mw-redirect" title="Monolithic integrated circuit">monolithic integrated circuits</a> and consisted of a differential-amplifier input stage to perform logic and followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs. The emitter-follower output stages could also be used to perform <a href="/wiki/Wired_logic_connection" title="Wired logic connection">wired-or logic</a>. </p><p><span class="anchor" id="MECL"></span><a href="/wiki/Motorola" title="Motorola">Motorola</a> introduced their first digital monolithic integrated circuit line, MECL I, in 1962.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Motorola developed several improved series, with MECL II in 1966, MECL III in 1968 with 1-nanosecond gate propagation time and 300 MHz flip-flop toggle rates, and the 10,000 series (with lower power consumption and controlled edge speeds) in 1971.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> The MECL 10H family was introduced in 1981.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> Fairchild introduced the F100K family in 1975.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p><p>The ECLinPS ("ECL in picoseconds") family was introduced in 1987.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> ECLinPS has 500 ps single-gate delay and 1.1 GHz flip-flop toggle frequency.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> The ECLinPS family parts are available from multiple sources, including Arizona Microtek, Micrel, National Semiconductor, and ON Semiconductor.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the <a href="/wiki/IBM_ES/9000_family" class="mw-redirect" title="IBM ES/9000 family">Enterprise System/9000</a> members of IBM's <a href="/wiki/ESA/390" class="mw-redirect" title="ESA/390">ESA/390</a> computer family, used ECL,<sup id="cite_ref-barish_26-0" class="reference"><a href="#cite_note-barish-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> as did the <a href="/wiki/Cray-1" title="Cray-1">Cray-1</a>;<sup id="cite_ref-Russell_27-0" class="reference"><a href="#cite_note-Russell-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> and first-generation <a href="/wiki/Amdahl_Corporation" title="Amdahl Corporation">Amdahl</a> mainframes. (Current IBM mainframes use <a href="/wiki/CMOS" title="CMOS">CMOS</a>.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup>) Beginning in 1975, <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a>'s highest performance processors were all based on multi-chip ECL CPUs—from the ECL <a href="/wiki/PDP-10" title="PDP-10">KL10</a> through the ECL <a href="/wiki/VAX_8000" title="VAX 8000">VAX 8000</a> and finally the <a href="/wiki/VAX_9000" title="VAX 9000">VAX 9000</a>. By 1991, the CMOS <a href="/wiki/NVAX" title="NVAX">NVAX</a> was launched which offered comparable performance to the VAX 9000 despite costing 25 times less and consuming considerably less power.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/R6000" title="R6000">MIPS R6000</a> computers also used ECL. Some of these computer designs used ECL <a href="/wiki/Gate_array" title="Gate array">gate arrays</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Implementation">Implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=2" title="Edit section: Implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:ECL_structure_1000.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/5f/ECL_structure_1000.jpg/350px-ECL_structure_1000.jpg" decoding="async" width="350" height="250" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/5f/ECL_structure_1000.jpg/525px-ECL_structure_1000.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/5f/ECL_structure_1000.jpg/700px-ECL_structure_1000.jpg 2x" data-file-width="1000" data-file-height="714" /></a><figcaption>The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and <span style="text-decoration:overline;">Y</span>. Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at <a href="/wiki/File:ECL_logical0_1000.jpg" title="File:ECL logical0 1000.jpg">low input voltage</a> (logical "0"), <a href="/wiki/File:ECL_transition_1000.jpg" title="File:ECL transition 1000.jpg">during the transition</a> and at <a href="/wiki/File:ECL_logical1_1000.jpg" title="File:ECL logical1 1000.jpg">high input voltage</a> (logical "1").</figcaption></figure> <p>ECL is based on an emitter-coupled (<a href="/wiki/Differential_amplifier#Long-tailed_pair" title="Differential amplifier">long-tailed</a>) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor R<sub>E</sub> acts nearly as a <a href="/wiki/Current_source" title="Current source">current source</a>. The output voltages at the collector load resistors R<sub>C1</sub> and R<sub>C3</sub> are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors R<sub>E4</sub> and R<sub>E5</sub> do not exist in all versions of ECL. In some cases 50 Ω line termination resistors connected between the bases of the input transistors and −2 V act as emitter resistors.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=3" title="Edit section: Operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The ECL circuit operation is considered below with assumption that the input voltage is applied to T1 base, while T2 input is unused or a logical "0" is applied. </p><p><a href="/wiki/File:ECL_transition_1000.jpg" title="File:ECL transition 1000.jpg">During the transition</a>, the core of the circuit – the emitter-coupled pair (T1 and T3) – acts as a differential amplifier with single-ended input. The "long-tail" current source (R<sub>E</sub>) sets the total current flowing through the two legs of the pair. The input voltage controls the current flowing through the transistors by sharing it between the two legs, steering it all to one side when not near the switching point. The gain is higher than at the end states (see below) and the circuit switches quickly. </p><p><a href="/wiki/File:ECL_logical0_1000.jpg" title="File:ECL logical0 1000.jpg">At low input voltage</a> (logical "0") or <a href="/wiki/File:ECL_logical1_1000.jpg" title="File:ECL logical1 1000.jpg">at high input voltage</a> (logical "1") the differential amplifier is overdriven. The transistor (T1 or T3) is cutoff and the other (T3 or T1) is in active linear region acting as a <a href="/wiki/Common_emitter#Emitter_degeneration" title="Common emitter">common-emitter stage with emitter degeneration</a> that takes all the current, starving the other cutoff transistor.<br />The active transistor is loaded with the relatively high emitter resistance <i>R</i><sub>E</sub> that introduces a significant negative feedback (emitter degeneration). To prevent saturation of the active transistor so that the diffusion time that slows the recovery from saturation will not be involved in the logic delay,<sup id="cite_ref-unitd04_2-1" class="reference"><a href="#cite_note-unitd04-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> the emitter and collector resistances are chosen such that at maximum input voltage some voltage is left across the transistor. The residual gain is low (<i>K</i> = <i>R</i><sub>C</sub>/<i>R</i><sub>E</sub> < 1). The circuit is insensitive to the input voltage variations and the transistor stays firmly in active linear region. The input resistance is high because of the series negative feedback.<br /> The cutoff transistor breaks the connection between its input and output. As a result, its input voltage does not affect the output voltage. The input resistance is high again since the base-emitter junction is cutoff. </p> <div class="mw-heading mw-heading2"><h2 id="Characteristics">Characteristics</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=4" title="Edit section: Characteristics"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike other logic types which draw more current when switching than quiescent. In cryptographic applications, ECL circuits are also less susceptible to <a href="/wiki/Side_channel_attack" class="mw-redirect" title="Side channel attack">side channel attacks</a> such as <a href="/wiki/Differential_power_analysis" class="mw-redirect" title="Differential power analysis">differential power analysis</a>.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (December 2018)">citation needed</span></a></i>]</sup> </p><p>The <a href="/wiki/Propagation_delay" title="Propagation delay">propagation time</a> for this arrangement can be less than a nanosecond, including the signal delay getting on and off the IC package. Some type of ECL has always been the fastest logic family.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Radiation_hardening" title="Radiation hardening">Radiation hardening</a>: While normal commercial-grade chips can withstand 100 <a href="/wiki/Gray_(unit)" title="Gray (unit)">gray</a> (10 krad), many ECL devices are operational after 100,000 gray (10 Mrad).<sup id="cite_ref-verkasalo_33-0" class="reference"><a href="#cite_note-verkasalo-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Power_supplies_and_logic_levels">Power supplies and logic levels</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=5" title="Edit section: Power supplies and logic levels"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground). Other logic families ground the negative end of the power supply. This is done mainly to minimize the influence of the power supply variations on the logic levels. ECL is more sensitive to noise on the V<sub>CC</sub> and is relatively immune to noise on V<sub>EE</sub>.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> Because ground should be the most stable voltage in a system, ECL is specified with a positive ground. In this connection, when the supply voltage varies, the voltage drops across the collector resistors change slightly (in the case of emitter constant current source, they do not change at all). As the collector resistors are firmly "tied up" to ground, the output voltages "move" slightly (or not at all). If the negative end of the power supply was grounded, the collector resistors would be attached to the positive rail. As the constant voltage drops across the collector resistors change slightly (or not at all), the output voltages follow the supply voltage variations and the two circuit parts act as constant current level shifters. In this case, the voltage divider R1-R2 compensates the voltage variations to some extent. The positive power supply has another disadvantage — the output voltages will vary slightly (±0.4 V) against the background of high constant voltage (+3.9 V). Another reason for using a negative power supply is protection of the output transistors from an accidental short circuit developing between output and ground<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> (but the outputs are not protected from a short circuit with the negative rail). </p><p>The value of the supply voltage is chosen so that sufficient current flows through the compensating diodes D1 and D2 and the voltage drop across the common emitter resistor R<sub>E</sub> is adequate. </p><p>ECL circuits available on the open market usually operated with logic levels incompatible with other families. This meant that interoperation between ECL and other logic families, such as the popular <a href="/wiki/Transistor-transistor_logic" class="mw-redirect" title="Transistor-transistor logic">TTL</a> family, required additional interface circuits. The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome. </p><p>At least one manufacturer, <a href="/wiki/IBM" title="IBM">IBM</a>, made ECL circuits for use in the manufacturer's own products. The power supplies were substantially different from those used in the open market.<sup id="cite_ref-barish_26-1" class="reference"><a href="#cite_note-barish-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="PECL">PECL</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=6" title="Edit section: PECL"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>Positive emitter-coupled logic</b>, also called <b>pseudo-ECL</b>, (PECL) is a further development of ECL using a positive 5 V supply instead of a negative 5.2 V supply.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> Low-voltage positive emitter-coupled logic (LVPECL) is a power-optimized version of PECL, using a positive 3.3 V instead of 5 V supply. PECL and LVPECL are differential-signaling systems and are mainly used in high-speed and clock-distribution circuits. </p><p>A common misconception is that PECL devices are slightly different from ECL devices. In fact, every ECL device is also a PECL device.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>Logic levels:<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <tbody><tr> <th>Type </th> <th>V<sub>ee</sub> </th> <th>V<sub>low</sub> </th> <th>V<sub>high</sub> </th> <th>V<sub>cc</sub> </th> <th>V<sub>cm</sub> </th></tr> <tr> <th>PECL </th> <td>GND </td> <td>3.4 V </td> <td>4.2 V </td> <td>5.0 V </td> <td> </td></tr> <tr> <th>LVPECL </th> <td>GND </td> <td>1.6 V </td> <td>2.4 V </td> <td>3.3 V </td> <td>2.0 V </td></tr></tbody></table> <dl><dd><small>Note: <span class="texhtml"><i>V</i><sub>cm</sub></span> is the common mode voltage range.</small></dd></dl> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=7" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">Original drawing based on <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFBlood_Jr.1972" class="citation book cs1">Blood Jr., William R. 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Motorola Semiconductor Products. p. 1 – via Bitsavers.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=MECL+System+Design+Handbook&rft.pages=1&rft.edition=2nd&rft.pub=Motorola+Semiconductor+Products&rft.date=1972&rft.aulast=Blood+Jr.&rft.aufirst=William+R.&rft_id=http%3A%2F%2Fwww.bitsavers.org%2Fcomponents%2Fmotorola%2F_dataBooks%2F1972_Motorola_MECL_System_Design_Handbook_2ed.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-unitd04-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-unitd04_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-unitd04_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFLawless" class="citation web cs1">Lawless, Brian. <a rel="nofollow" class="external text" href="http://www.physics.dcu.ie/~bl/digi/unitd04.pdf">"Unit4: ECL Emitter Coupled Logic"</a> <span class="cs1-format">(PDF)</span>. <i>Fundamental Digital Electronics</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Fundamental+Digital+Electronics&rft.atitle=Unit4%3A+ECL+Emitter+Coupled+Logic&rft.aulast=Lawless&rft.aufirst=Brian&rft_id=http%3A%2F%2Fwww.physics.dcu.ie%2F~bl%2Fdigi%2Funitd04.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFKumar2008" class="citation book cs1">Kumar, Anand (2008). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=ECeObhzCiLIC&pg=RA2-PA472"><i>Pulse and Digital Circuits</i></a>. PHI Learning. p. 472. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-81-203-3356-7" title="Special:BookSources/978-81-203-3356-7"><bdi>978-81-203-3356-7</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Pulse+and+Digital+Circuits&rft.pages=472&rft.pub=PHI+Learning&rft.date=2008&rft.isbn=978-81-203-3356-7&rft.aulast=Kumar&rft.aufirst=Anand&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DECeObhzCiLIC%26pg%3DRA2-PA472&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFStonham1996" class="citation book cs1">Stonham, T. J. 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Taylor & Francis. p. 173. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-412-54970-0" title="Special:BookSources/978-0-412-54970-0"><bdi>978-0-412-54970-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Digital+Logic+Techniques%3A+Principles+and+Practice&rft.pages=173&rft.pub=Taylor+%26+Francis&rft.date=1996&rft.isbn=978-0-412-54970-0&rft.aulast=Stonham&rft.aufirst=T.+J.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DUE6vFEnGP2kC%26pg%3DPA173&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFTummala2001" class="citation book cs1">Tummala, Rao R. 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McGraw-Hill. p. 930. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-07-137169-8" title="Special:BookSources/978-0-07-137169-8"><bdi>978-0-07-137169-8</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Fundamentals+of+Microsystems+Packaging&rft.pages=930&rft.pub=McGraw-Hill&rft.date=2001&rft.isbn=978-0-07-137169-8&rft.aulast=Tummala&rft.aufirst=Rao+R.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DP93ZrOWHlO0C%26pg%3DPA930&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFMims2000" class="citation book cs1"><a href="/wiki/Forrest_Mims" title="Forrest Mims">Mims, Forrest M.</a> (2000). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=STzitya5iwgC&pg=PA115"><i>The Forrest Mims Circuit Scrapbook</i></a>. Vol. 2. Newnes. p. 115. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-878707-48-2" title="Special:BookSources/978-1-878707-48-2"><bdi>978-1-878707-48-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+Forrest+Mims+Circuit+Scrapbook&rft.pages=115&rft.pub=Newnes&rft.date=2000&rft.isbn=978-1-878707-48-2&rft.aulast=Mims&rft.aufirst=Forrest+M.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DSTzitya5iwgC%26pg%3DPA115&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFFisherBahl1995" class="citation book cs1">Fisher, Dennis; Bahl, I.J. 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Yourke's circuits used commercial transistors and had an average gate delay of 12 ns.</span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFRoehrThorpe1963" class="citation book cs1">Roehr, William D.; Thorpe, Darrell, eds. (1963). <a rel="nofollow" class="external text" href="https://archive.org/details/High-speedSwitchingHandbook"><i>High-Speed Switching Transistor Handbook</i></a>. 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Raven was a simplified VAX design with a single chip CPU and a single chip FPU. Implemented in Fujitsu's ECL standard cells, it was intended to run at 250Mhz and deliver 50 "VUPS" ... Power dissipation would have been a startling (for the day) 150W.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Raven%3A+Introduction%3A+The+ECL+Conundrum&rft.aulast=Supnik&rft.aufirst=Bob&rft_id=http%3A%2F%2Fsimh.trailing-edge.com%2Fsemi%2Fraven.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><a href="#CITEREFBlood_Jr.1972">Blood Jr. 1972</a>, p. 3</span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text">John F. Wakerly. Supplement to Digital Design Principles and Practices. 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Oxford University Press. p. 47. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-19-933913-6" title="Special:BookSources/978-0-19-933913-6"><bdi>978-0-19-933913-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Emitter-Coupled+Logic+%28ECL%29&rft.btitle=Microelectronic+Circuits&rft.pages=47&rft.pub=Oxford+University+Press&rft.date=2015&rft.isbn=978-0-19-933913-6&rft.au=Sedra&rft.au=Smith&rft_id=http%3A%2F%2Fglobal.oup.com%2Fus%2Fcompanion.websites%2Ffdscontent%2Fuscompanion%2Fus%2Fstatic%2Fcompanion.websites%2F9780199339136%2Fpdf%2FAdditional_Material.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-verkasalo-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-verkasalo_33-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFLeppäläVerkasalo1989" class="citation web cs1">Leppälä, Kari; Verkasalo, Raimo (1989). <a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/27782054">"Protection of Instrument Control Computers against Soft and Hard Errors and Cosmic Ray Effects"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Protection+of+Instrument+Control+Computers+against+Soft+and+Hard+Errors+and+Cosmic+Ray+Effects&rft.date=1989&rft.aulast=Lepp%C3%A4l%C3%A4&rft.aufirst=Kari&rft.au=Verkasalo%2C+Raimo&rft_id=https%3A%2F%2Fwww.researchgate.net%2Fpublication%2F27782054&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFMingesASM_International._Handbook_Committee1989" class="citation book cs1">Minges, Merrill L.; ASM International. Handbook Committee (1989). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=c2YxCCaM9RIC&pg=PA163"><i>Electronic Materials Handbook: Packaging</i></a>. ASM International. p. 163. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9780871702852" title="Special:BookSources/9780871702852"><bdi>9780871702852</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Electronic+Materials+Handbook%3A+Packaging&rft.pages=163&rft.pub=ASM+International&rft.date=1989&rft.isbn=9780871702852&rft.aulast=Minges&rft.aufirst=Merrill+L.&rft.au=ASM+International.+Handbook+Committee&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dc2YxCCaM9RIC%26pg%3DPA163&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJain2003" class="citation book cs1">Jain, R.P. (2003). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=dnq3HmDN1ZAC&pg=RA1-PA110"><i>Modern digital electronics</i></a>. McGraw-Hill Education (India) Pvt Limited. p. 111. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9780070494923" title="Special:BookSources/9780070494923"><bdi>9780070494923</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Modern+digital+electronics&rft.pages=111&rft.pub=McGraw-Hill+Education+%28India%29+Pvt+Limited&rft.date=2003&rft.isbn=9780070494923&rft.aulast=Jain&rft.aufirst=R.P.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Ddnq3HmDN1ZAC%26pg%3DRA1-PA110&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGoldie2003" class="citation web cs1">Goldie, John (January 21, 2003). <a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1225744">"LVDS, CML, ECL – differential interfaces with odd voltages"</a>. <i>EE Times</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=LVDS%2C+CML%2C+ECL+%E2%80%93+differential+interfaces+with+odd+voltages&rft.date=2003-01-21&rft.aulast=Goldie&rft.aufirst=John&rft_id=http%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1225744&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFPettyPearson" class="citation web cs1">Petty, Cleon; Pearson, Todd. <a rel="nofollow" class="external text" href="https://www.onsemi.com/pub/Collateral/AN1406-D.PDF">"Designing with PECL (ECL at +5.0 V)"</a> <span class="cs1-format">(PDF)</span>. p. 3. AN1406-D.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Designing+with+PECL+%28ECL+at+%2B5.0+V%29&rft.pages=3&rft.aulast=Petty&rft.aufirst=Cleon&rft.au=Pearson%2C+Todd&rft_id=https%3A%2F%2Fwww.onsemi.com%2Fpub%2FCollateral%2FAN1406-D.PDF&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFHolland2002" class="citation web cs1">Holland, Nick (December 2002). <a rel="nofollow" class="external text" href="http://focus.ti.com/lit/an/slla120/slla120.pdf">"Interfacing Between LVPECL, VML, CML and LVDS Levels"</a> <span class="cs1-format">(PDF)</span>. <i>Application Report</i>. Texas Instruments. SLLA120.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Application+Report&rft.atitle=Interfacing+Between+LVPECL%2C+VML%2C+CML+and+LVDS+Levels&rft.date=2002-12&rft.aulast=Holland&rft.aufirst=Nick&rft_id=http%3A%2F%2Ffocus.ti.com%2Flit%2Fan%2Fslla120%2Fslla120.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=8" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSavard2018" class="citation web cs1">Savard, John J. G. (2018) [2005]. <a rel="nofollow" class="external text" href="http://www.quadibloc.com/comp/cp01.htm">"What Computers Are Made From"</a>. <i>quadibloc</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180702235616/http://www.quadibloc.com/comp/cp01.htm">Archived</a> from the original on July 2, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">July 16,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=quadibloc&rft.atitle=What+Computers+Are+Made+From&rft.date=2018&rft.aulast=Savard&rft.aufirst=John+J.+G.&rft_id=http%3A%2F%2Fwww.quadibloc.com%2Fcomp%2Fcp01.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></li> <li><style data-mw-deduplicate="TemplateStyles:r1041539562">.mw-parser-output .citation{word-wrap:break-word}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}</style><span class="citation patent" id="CITEREFYourke1960"><a rel="nofollow" class="external text" href="https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US2964652">US 2964652</a>, Yourke, Hannon S., "Transistor Switching Circuits", published November 15, 1956, issued December 13, 1960</span><span class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.number=2964652&rft.cc=US&rft.title=Transistor+Switching+Circuits&rft.inventor=Yourke&rft.date=December 13, 1960&rft.pubdate=November 15, 1956"><span style="display: none;"> </span></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFYourke1957" class="citation journal cs1">Yourke, Hannon S. (September 1957). "Millimicrosecond Transistor Current Switching Circuits". <i>IRE Transactions on Circuit Theory</i>. <b>4</b> (3): <span class="nowrap">236–</span>240. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTCT.1957.1086377">10.1109/TCT.1957.1086377</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IRE+Transactions+on+Circuit+Theory&rft.atitle=Millimicrosecond+Transistor+Current+Switching+Circuits&rft.volume=4&rft.issue=3&rft.pages=%3Cspan+class%3D%22nowrap%22%3E236-%3C%2Fspan%3E240&rft.date=1957-09&rft_id=info%3Adoi%2F10.1109%2FTCT.1957.1086377&rft.aulast=Yourke&rft.aufirst=Hannon+S.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFMueller2008" class="citation web cs1">Mueller, Dieter (2008) [2006]. <a rel="nofollow" class="external text" href="http://www.6502.org/users/dieter/decl/decl1.htm">"DECL test run — Differential emitter-coupled logic"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180718215508/http://www.6502.org/users/dieter/decl/decl1.htm">Archived</a> from the original on July 18, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">July 18,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DECL+test+run+%E2%80%94+Differential+emitter-coupled+logic&rft.date=2008&rft.aulast=Mueller&rft.aufirst=Dieter&rft_id=http%3A%2F%2Fwww.6502.org%2Fusers%2Fdieter%2Fdecl%2Fdecl1.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AEmitter-coupled+logic" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Emitter-coupled_logic&action=edit&section=9" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.worldpowersystems.com/archives/solid-state-datasheets/Motorola/MECL/index.html">Motorola MECL logic family datasheets, 1963</a></li></ul> <div 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id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a class="mw-selflink selflink">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer 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