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<span>Generations</span> </div> </a> <button aria-controls="toc-Generations-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Generations subsection</span> </button> <ul id="toc-Generations-sublist" class="vector-toc-list"> <li id="toc-LPDDR(1)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR(1)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>LPDDR(1)</span> </div> </a> <ul id="toc-LPDDR(1)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-LPDDR2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>LPDDR2</span> </div> </a> <ul id="toc-LPDDR2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-LPDDR3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR3"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>LPDDR3</span> </div> </a> <ul id="toc-LPDDR3-sublist" class="vector-toc-list"> <li id="toc-LPDDR3E" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#LPDDR3E"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>LPDDR3E</span> </div> </a> <ul id="toc-LPDDR3E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-LPDDR4" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR4"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>LPDDR4</span> </div> </a> <ul id="toc-LPDDR4-sublist" class="vector-toc-list"> <li id="toc-LPDDR4X" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#LPDDR4X"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>LPDDR4X</span> </div> </a> <ul id="toc-LPDDR4X-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-LPDDR5" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR5"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>LPDDR5</span> </div> </a> <ul id="toc-LPDDR5-sublist" class="vector-toc-list"> <li id="toc-LPDDR5X" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#LPDDR5X"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5.1</span> <span>LPDDR5X</span> </div> </a> <ul id="toc-LPDDR5X-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-LPDDR6" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LPDDR6"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>LPDDR6</span> </div> </a> <ul id="toc-LPDDR6-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">LPDDR</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 14 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-14" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">14 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Mobile_DDR" title="Mobile DDR – Catalan" lang="ca" hreflang="ca" data-title="Mobile DDR" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/LP-SDRAM" title="LP-SDRAM – German" lang="de" hreflang="de" data-title="LP-SDRAM" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/LPDDR" title="LPDDR – Estonian" lang="et" hreflang="et" data-title="LPDDR" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/LPDDR" title="LPDDR – Spanish" lang="es" hreflang="es" data-title="LPDDR" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/LPDDR" title="LPDDR – French" lang="fr" hreflang="fr" data-title="LPDDR" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%AA%A8%EB%B0%94%EC%9D%BC_DDR" title="모바일 DDR – Korean" lang="ko" hreflang="ko" data-title="모바일 DDR" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/LPDDR" title="LPDDR – Dutch" lang="nl" hreflang="nl" data-title="LPDDR" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/LPDDR" title="LPDDR – Japanese" lang="ja" hreflang="ja" data-title="LPDDR" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/LPDDR" title="LPDDR – Polish" lang="pl" hreflang="pl" data-title="LPDDR" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/LPDDR" title="LPDDR – Romanian" lang="ro" hreflang="ro" data-title="LPDDR" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/LPDDR" title="LPDDR – Russian" lang="ru" hreflang="ru" data-title="LPDDR" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/LPDDR" title="LPDDR – Ukrainian" lang="uk" hreflang="uk" data-title="LPDDR" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/LPDDR" title="LPDDR – Vietnamese" lang="vi" hreflang="vi" data-title="LPDDR" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E7%A7%BB%E5%8A%A8DDR" title="移动DDR – Chinese" lang="zh" hreflang="zh" data-title="移动DDR" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a 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class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg/220px-Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg/330px-Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg/440px-Tolino_shine_-_controller_board_-_Samsung_K4X2G323PD-8GD8-1997.jpg 2x" data-file-width="4399" data-file-height="3299" /></a><figcaption>Mobile DDR: Samsung K4X2G323PD-8GD8</figcaption></figure><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output 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.sidebar-below{border-top:1px solid #aaa;border-bottom:1px solid #aaa}.mw-parser-output .sidebar-navbar{text-align:right;font-size:115%;padding:0 0.4em 0.4em}.mw-parser-output .sidebar-list-title{padding:0 0.4em;text-align:left;font-weight:bold;line-height:1.6em;font-size:105%}.mw-parser-output .sidebar-list-title-c{padding:0 0.4em;text-align:center;margin:0 3.3em}@media(max-width:640px){body.mediawiki .mw-parser-output .sidebar{width:100%!important;clear:both;float:none!important;margin-left:0!important;margin-right:0!important}}body.skin--responsive .mw-parser-output .sidebar a>img{max-width:none!important}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar sidebar-collapse nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="/wiki/Computer_memory" title="Computer memory">Computer memory</a> and <a href="/wiki/Computer_data_storage" title="Computer data storage">data storage</a> types</th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">General</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Memory_coherence" title="Memory coherence">Memory coherence</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></li> <li><a href="/wiki/Memory_access_pattern" title="Memory access pattern">Memory access pattern</a></li> <li><a href="/wiki/Memory_map" title="Memory map">Memory map</a></li> <li><a href="/wiki/Computer_data_storage#Secondary_storage" title="Computer data storage">Secondary storage</a></li> <li><a href="/wiki/Semiconductor_memory" title="Semiconductor memory">MOS memory</a> <ul><li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">floating-gate</a></li></ul></li> <li><a href="/wiki/Continuous_availability" title="Continuous availability">Continuous availability</a></li> <li><a href="/wiki/Areal_density_(computer_storage)" class="mw-redirect" title="Areal density (computer storage)">Areal density (computer storage)</a></li> <li><a href="/wiki/Block_(data_storage)" title="Block (data storage)">Block (data storage)</a></li> <li><a href="/wiki/Object_storage" title="Object storage">Object storage</a></li> <li><a href="/wiki/Direct-attached_storage" title="Direct-attached storage">Direct-attached storage</a></li> <li><a href="/wiki/Network-attached_storage" title="Network-attached storage">Network-attached storage</a> <ul><li><a href="/wiki/Storage_area_network" title="Storage area network">Storage area network</a></li> <li><a href="/wiki/Block-level_storage" title="Block-level storage">Block-level storage</a></li></ul></li> <li><a href="/wiki/Single-instance_storage" title="Single-instance storage">Single-instance storage</a></li> <li><a href="/wiki/Data" title="Data">Data</a></li> <li><a href="/wiki/Data_model" title="Data model">Structured data</a></li> <li><a href="/wiki/Unstructured_data" title="Unstructured data">Unstructured data</a></li> <li><a href="/wiki/Big_data" title="Big data">Big data</a></li> <li><a href="/wiki/Metadata" title="Metadata">Metadata</a></li> <li><a href="/wiki/Data_compression" title="Data compression">Data compression</a></li> <li><a href="/wiki/Data_corruption" title="Data corruption">Data corruption</a></li> <li><a href="/wiki/Data_cleansing" title="Data cleansing">Data cleansing</a></li> <li><a href="/wiki/Data_degradation" title="Data degradation">Data degradation</a></li> <li><a href="/wiki/Data_integrity" title="Data integrity">Data integrity</a></li> <li><a href="/wiki/Data_security" title="Data security">Data security</a></li> <li><a href="/wiki/Data_validation" title="Data validation">Data validation</a></li> <li><a href="/wiki/Data_validation_and_reconciliation" title="Data validation and reconciliation">Data validation and reconciliation</a></li> <li><a href="/wiki/Data_recovery" title="Data recovery">Data recovery</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Storage</a></li> <li><a href="/wiki/Data_cluster" class="mw-redirect" title="Data cluster">Data cluster</a></li> <li><a href="/wiki/Directory_(computing)" title="Directory (computing)">Directory</a></li> <li><a href="/wiki/Shared_resource" title="Shared resource">Shared resource</a></li> <li><a href="/wiki/File_sharing" title="File sharing">File sharing</a></li> <li><a href="/wiki/File_system" title="File system">File system</a></li> <li><a href="/wiki/Clustered_file_system" title="Clustered file system">Clustered file system</a></li> <li><a href="/wiki/Clustered_file_system#Distributed_file_systems" title="Clustered file system">Distributed file system</a></li> <li><a href="/wiki/Distributed_file_system_for_cloud" title="Distributed file system for cloud">Distributed file system for cloud</a></li> <li><a href="/wiki/Distributed_data_store" title="Distributed data store">Distributed data store</a></li> <li><a href="/wiki/Distributed_database" title="Distributed database">Distributed database</a></li> <li><a href="/wiki/Database" title="Database">Database</a></li> <li><a href="/wiki/Data_bank" title="Data bank">Data bank</a></li> <li><a href="/wiki/Data_storage" title="Data storage">Data storage</a></li> <li><a href="/wiki/Data_store" title="Data store">Data store</a></li> <li><a href="/wiki/Data_deduplication" title="Data deduplication">Data deduplication</a></li> <li><a href="/wiki/Data_structure" title="Data structure">Data structure</a></li> <li><a href="/wiki/Data_redundancy" title="Data redundancy">Data redundancy</a></li> <li><a href="/wiki/Replication_(computing)" title="Replication (computing)">Replication (computing)</a></li> <li><a href="/wiki/Memory_refresh" title="Memory refresh">Memory refresh</a></li> <li><a href="/wiki/Storage_record" title="Storage record">Storage record</a></li> <li><a href="/wiki/Information_repository" title="Information repository">Information repository</a></li> <li><a href="/wiki/Knowledge_base" title="Knowledge base">Knowledge base</a></li> <li><a href="/wiki/Computer_file" title="Computer file">Computer file</a></li> <li><a href="/wiki/Object_file" title="Object file">Object file</a></li> <li><a href="/wiki/File_deletion" title="File deletion">File deletion</a></li> <li><a href="/wiki/File_copying" title="File copying">File copying</a></li> <li><a href="/wiki/Backup" title="Backup">Backup</a></li> <li><a href="/wiki/Core_dump" title="Core dump">Core dump</a></li> <li><a href="/wiki/Hex_dump" title="Hex dump">Hex dump</a></li> <li><a href="/wiki/Data_communication" title="Data communication">Data communication</a></li> <li><a href="/wiki/Information_transfer" title="Information transfer">Information transfer</a></li> <li><a href="/wiki/Temporary_file" title="Temporary file">Temporary file</a></li> <li><a href="/wiki/Copy_protection" title="Copy protection">Copy protection</a></li> <li><a href="/wiki/Digital_rights_management" title="Digital rights management">Digital rights management</a></li> <li><a href="/wiki/Volume_(computing)" title="Volume (computing)">Volume (computing)</a></li> <li><a href="/wiki/Boot_sector" title="Boot sector">Boot sector</a></li> <li><a href="/wiki/Master_boot_record" title="Master boot record">Master boot record</a></li> <li><a href="/wiki/Volume_boot_record" title="Volume boot record">Volume boot record</a></li> <li><a href="/wiki/Disk_array" title="Disk array">Disk array</a></li> <li><a href="/wiki/Disk_image" title="Disk image">Disk image</a></li> <li><a href="/wiki/Disk_mirroring" title="Disk mirroring">Disk mirroring</a></li> <li><a href="/wiki/Disk_aggregation" title="Disk aggregation">Disk aggregation</a></li> <li><a href="/wiki/Disk_partitioning" title="Disk partitioning">Disk partitioning</a></li> <li><a href="/wiki/Memory_segmentation" title="Memory segmentation">Memory segmentation</a></li> <li><a href="/wiki/Locality_of_reference" title="Locality of reference">Locality of reference</a></li> <li><a href="/wiki/Logical_disk" title="Logical disk">Logical disk</a></li> <li><a href="/wiki/Storage_virtualization" title="Storage virtualization">Storage virtualization</a></li> <li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Memory-mapped_file" title="Memory-mapped file">Memory-mapped file</a></li> <li><a href="/wiki/Software_entropy" class="mw-redirect" title="Software entropy">Software entropy</a></li> <li><a href="/wiki/Software_rot" title="Software rot">Software rot</a></li> <li><a href="/wiki/In-memory_database" title="In-memory database">In-memory database</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory processing</a></li> <li><a href="/wiki/Persistence_(computer_science)" title="Persistence (computer science)">Persistence (computer science)</a></li> <li><a href="/wiki/Persistent_data_structure" title="Persistent data structure">Persistent data structure</a></li> <li><a href="/wiki/RAID" title="RAID">RAID</a></li> <li><a href="/wiki/Non-RAID_drive_architectures" title="Non-RAID drive architectures">Non-RAID drive architectures</a></li> <li><a href="/wiki/Memory_paging" title="Memory paging">Memory paging</a></li> <li><a href="/wiki/Bank_switching" title="Bank switching">Bank switching</a></li> <li><a href="/wiki/Grid_computing" title="Grid computing">Grid computing</a></li> <li><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a></li> <li><a href="/wiki/Cloud_storage" title="Cloud storage">Cloud storage</a></li> <li><a href="/wiki/Fog_computing" title="Fog computing">Fog computing</a></li> <li><a href="/wiki/Edge_computing" title="Edge computing">Edge computing</a></li> <li><a href="/wiki/Dew_computing" title="Dew computing">Dew computing</a></li> <li><a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a></li> <li><a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a></li> <li><a href="/wiki/Mark_Kryder#Kryder's_law_projection" title="Mark Kryder">Kryder's law</a></li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Volatile_memory" title="Volatile memory">Volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Cache_(computing)#HARDWARE" title="Cache (computing)">Hardware cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li></ul></li> <li><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> <ul><li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Synchronous_Graphics_RAM_(SGRAM)" title="Synchronous dynamic random-access memory">SGRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a></li> <li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a class="mw-selflink selflink">LPDDR</a></li> <li><a href="/wiki/Quad_Data_Rate_SRAM" title="Quad Data Rate SRAM">QDRSRAM</a></li> <li><a href="/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM" title="Dynamic random-access memory">EDO DRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a></li></ul></li> <li><a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> <ul><li><a href="/wiki/1T-SRAM" title="1T-SRAM">1T-SRAM</a></li></ul></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">QRAM</a></li> <li><a href="/wiki/Content-addressable_memory" title="Content-addressable memory">Content-addressable memory</a> (CAM)</li> <li><a href="/wiki/Computational_RAM" title="Computational RAM">Computational RAM</a></li> <li><a href="/wiki/Video_random_access_memory" class="mw-redirect" title="Video random access memory">VRAM</a></li> <li><a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">Dual-ported RAM</a> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">Video RAM (dual-ported DRAM)</a></li></ul></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Williams_tube" title="Williams tube">Williams–Kilburn tube</a> (1946–1947)</li> <li><a href="/wiki/Delay-line_memory" title="Delay-line memory">Delay-line memory</a> (1947)</li> <li><a href="/wiki/Mellon_optical_memory" title="Mellon optical memory">Mellon optical memory</a> (1951)</li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a> (1952)</li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/T-RAM" title="T-RAM">T-RAM</a> (2009)</li> <li><a href="/wiki/Z-RAM" title="Z-RAM">Z-RAM</a> (2002–2010)</li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">Non-volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Diode_matrix" title="Diode matrix">Diode matrix</a></li> <li><a href="/wiki/Read-only_memory#Factory-programmed" title="Read-only memory">MROM</a></li> <li><a href="/wiki/Programmable_ROM" title="Programmable ROM">PROM</a> <ul><li><a href="/wiki/EPROM" title="EPROM">EPROM</a></li> <li><a href="/wiki/EEPROM" title="EEPROM">EEPROM</a></li></ul></li> <li><a href="/wiki/ROM_cartridge" title="ROM cartridge">ROM cartridge</a></li> <li><a href="/wiki/Solid-state_storage" title="Solid-state storage">Solid-state storage</a> (SSS) <ul><li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> is used in:</li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state drive</a> (SSD)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">Solid-state hybrid drive</a> (SSHD)</li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li> <li><a href="/wiki/IBM_FlashSystem" title="IBM FlashSystem">IBM FlashSystem</a></li> <li><a href="/wiki/Flash_Core_Module" title="Flash Core Module">Flash Core Module</a></li></ul></li> <li><a href="/wiki/Memory_card" title="Memory card">Memory card</a> <ul><li><a href="/wiki/Memory_Stick" title="Memory Stick">Memory Stick</a></li> <li><a href="/wiki/CompactFlash" title="CompactFlash">CompactFlash</a></li> <li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/MultiMediaCard" title="MultiMediaCard">MultiMediaCard</a></li> <li><a href="/wiki/SD_card" title="SD card">SD card</a></li> <li><a href="/wiki/SIM_card" title="SIM card">SIM card</a></li> <li><a href="/wiki/SmartMedia" title="SmartMedia">SmartMedia</a></li> <li><a href="/wiki/Universal_Flash_Storage" title="Universal Flash Storage">Universal Flash Storage</a></li> <li><a href="/wiki/SxS" title="SxS">SxS</a></li> <li><a href="/wiki/MicroP2" title="MicroP2">MicroP2</a></li> <li><a href="/wiki/XQD_card" title="XQD card">XQD card</a></li></ul></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">Programmable metallization cell</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Phase-change_memory" title="Phase-change memory">PCM</a> (<a href="/wiki/3D_XPoint" title="3D XPoint">3D XPoint</a>)</li> <li><a href="/wiki/Magnetoresistive_RAM" title="Magnetoresistive RAM">MRAM</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">Electrochemical RAM</a> (ECRAM)</li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">Nano-RAM</a></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Early-stage <a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FeRAM</a></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Fe_FET" title="Fe FET">FeFET memory</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Analog_recording" title="Analog recording">Analog recording</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Phonograph_cylinder" title="Phonograph cylinder">Phonograph cylinder</a></li> <li><a href="/wiki/Phonograph_record" title="Phonograph record">Phonograph record</a></li> <li><a href="/wiki/Quadruplex_videotape" title="Quadruplex videotape">Quadruplex videotape</a></li> <li><a href="/wiki/Vision_Electronic_Recording_Apparatus" title="Vision Electronic Recording Apparatus">Vision Electronic Recording Apparatus</a></li> <li><a href="/wiki/Magnetic_recording" class="mw-redirect" title="Magnetic recording">Magnetic recording</a> <ul><li><a href="/wiki/Magnetic_storage" title="Magnetic storage">Magnetic storage</a></li> <li><a href="/wiki/Magnetic_tape" title="Magnetic tape">Magnetic tape</a></li> <li><a href="/wiki/Magnetic-tape_data_storage" title="Magnetic-tape data storage">Magnetic-tape data storage</a></li> <li><a href="/wiki/Tape_drive" title="Tape drive">Tape drive</a></li> <li><a href="/wiki/Tape_library" title="Tape library">Tape library</a></li> <li><a href="/wiki/Digital_Data_Storage" title="Digital Data Storage">Digital Data Storage</a> (DDS)</li> <li><a href="/wiki/Videotape" title="Videotape">Videotape</a></li> <li><a href="/wiki/Videocassette" class="mw-redirect" title="Videocassette">Videocassette</a></li> <li><a href="/wiki/Cassette_tape" class="mw-redirect" title="Cassette tape">Cassette tape</a></li> <li><a href="/wiki/Linear_Tape-Open" title="Linear Tape-Open">Linear Tape-Open</a></li> <li><a href="/wiki/Betamax" title="Betamax">Betamax</a></li> <li><a href="/wiki/8_mm_video_format" title="8 mm video format">8 mm video format</a></li> <li><a href="/wiki/DV_(video_format)" title="DV (video format)">DV</a></li> <li><a href="/wiki/MiniDV" class="mw-redirect" title="MiniDV">MiniDV</a></li> <li><a href="/wiki/MicroMV" title="MicroMV">MicroMV</a></li> <li><a href="/wiki/U-matic" title="U-matic">U-matic</a></li> <li><a href="/wiki/VHS" title="VHS">VHS</a></li> <li><a href="/wiki/S-VHS" title="S-VHS">S-VHS</a></li> <li><a href="/wiki/VHS-C" title="VHS-C">VHS-C</a></li> <li><a href="/wiki/D-VHS" title="D-VHS">D-VHS</a></li></ul></li> <li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">Hard disk drive</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Optical_storage" title="Optical storage">Optical</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/3D_optical_data_storage" title="3D optical data storage">3D optical data storage</a> <ul><li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a></li> <li><a href="/wiki/LaserDisc" title="LaserDisc">LaserDisc</a></li> <li><a href="/wiki/Compact_Disc_Digital_Audio" title="Compact Disc Digital Audio">Compact Disc Digital Audio</a> (CDDA)</li> <li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/CD_Video" title="CD Video">CD Video</a></li> <li><a href="/wiki/CD-R" title="CD-R">CD-R</a></li> <li><a href="/wiki/CD-RW" title="CD-RW">CD-RW</a></li> <li><a href="/wiki/Video_CD" title="Video CD">Video CD</a></li> <li><a href="/wiki/Super_Video_CD" title="Super Video CD">Super Video CD</a></li> <li><a href="/wiki/Mini_CD" title="Mini CD">Mini CD</a></li> <li><a href="/wiki/Nintendo_optical_discs" title="Nintendo optical discs">Nintendo optical discs</a></li> <li><a href="/wiki/CD-ROM" title="CD-ROM">CD-ROM</a></li> <li><a href="/wiki/Hyper_CD-ROM" title="Hyper CD-ROM">Hyper CD-ROM</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/DVD_recordable#DVD+R_and_DVD+RW_(DVD_"plus")" title="DVD recordable">DVD+R</a></li> <li><a href="/wiki/DVD-Video" title="DVD-Video">DVD-Video</a></li> <li><a href="/wiki/DVD_card" title="DVD card">DVD card</a></li> <li><a href="/wiki/DVD-RAM" title="DVD-RAM">DVD-RAM</a></li> <li><a href="/wiki/MiniDVD" title="MiniDVD">MiniDVD</a></li> <li><a href="/wiki/HD_DVD" title="HD DVD">HD DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li> <li><a href="/wiki/Ultra_HD_Blu-ray" title="Ultra HD Blu-ray">Ultra HD Blu-ray</a></li> <li><a href="/wiki/Holographic_Versatile_Disc" title="Holographic Versatile Disc">Holographic Versatile Disc</a></li></ul></li> <li><a href="/wiki/Write_once_read_many" title="Write once read many">WORM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">In development</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li> <li><a href="/wiki/Racetrack_memory" title="Racetrack memory">Racetrack memory</a></li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">NRAM</a></li> <li><a href="/wiki/Millipede_memory" title="Millipede memory">Millipede memory</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">ECRAM</a></li> <li><a href="/wiki/Patterned_media" title="Patterned media">Patterned media</a></li> <li><a href="/wiki/Holographic_data_storage" title="Holographic data storage">Holographic data storage</a> <ul><li><a href="/wiki/Electronic_quantum_holography" title="Electronic quantum holography">Electronic quantum holography</a></li></ul></li> <li><a href="/wiki/5D_optical_data_storage" title="5D optical data storage">5D optical data storage</a></li> <li><a href="/wiki/DNA_digital_data_storage" title="DNA digital data storage">DNA digital data storage</a></li> <li><a href="/wiki/Universal_memory" title="Universal memory">Universal memory</a></li> <li><a href="/wiki/Time_crystal" title="Time crystal">Time crystal</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">Quantum memory</a></li> <li><a href="/wiki/UltraRAM" title="UltraRAM">UltraRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Paper_data_storage" title="Paper data storage">Paper data storage</a> (1725)</li> <li><a href="/wiki/Punched_card" title="Punched card">Punched card</a> (1725)</li> <li><a href="/wiki/Punched_tape" title="Punched tape">Punched tape</a> (1725)</li> <li><a href="/wiki/Plugboard" title="Plugboard">Plugboard</a></li> <li><a href="/wiki/Drum_memory" title="Drum memory">Drum memory</a> (1932)</li> <li><a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">Magnetic-core memory</a> (1949)</li> <li><a href="/wiki/Plated-wire_memory" title="Plated-wire memory">Plated-wire memory</a> (1957)</li> <li><a href="/wiki/Core_rope_memory" title="Core rope memory">Core rope memory</a> (1960s)</li> <li><a href="/wiki/Thin-film_memory" title="Thin-film memory">Thin-film memory</a> (1962)</li> <li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a> (1962)</li> <li><a href="/wiki/Twistor_memory" title="Twistor memory">Twistor memory</a> (~1968)</li> <li><a href="/wiki/Bubble_memory" title="Bubble memory">Bubble memory</a> (~1970)</li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a> (1971)</li></ul></div></div></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Memory_types" title="Template:Memory types"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Memory_types" title="Template talk:Memory types"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Memory_types" title="Special:EditPage/Template:Memory types"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <p><b>Low-Power Double Data Rate</b> (<b>LPDDR</b>), also known as <b>LPDDR SDRAM</b>, is a type of <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">synchronous dynamic random-access memory</a> (SDRAM) that <a href="/wiki/Low-power_electronics" title="Low-power electronics">consumes less power</a> than other random access memory designs and is thus targeted for <a href="/wiki/Mobile_computing" title="Mobile computing">mobile computing</a> devices such as <a href="/wiki/Laptop_computers" class="mw-redirect" title="Laptop computers">laptop computers</a> and <a href="/wiki/Smartphone" title="Smartphone">smartphones</a>. Older variants are also known as Mobile DDR, and abbreviated as mDDR. </p><p>Modern LPDDR SDRAM is distinct from <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, with various differences that make the technology more appropriate for mobile applications.<sup id="cite_ref-:0_1-0" class="reference"><a href="#cite_note-:0-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> LPDDR technology standards are developed independently of DDR standards, with LPDDR4X and even LPDDR5 for example being implemented prior to <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a> and offering far higher data rates than <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Bus_width">Bus width</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=1" title="Edit section: Bus width"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>The "E" and "X" versions mark enhanced versions of the specifications. They formalize overclocking the memory array by usually 33%. </p><p>As with standard SDRAM, most generations double the internal fetch size and external transfer speed. (DDR4 and LPDDR5 being the exceptions.) </p> <div class="mw-heading mw-heading2"><h2 id="Generations">Generations</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=2" title="Edit section: Generations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1232966811">.mw-parser-output .hover-highlight tr:hover,.mw-parser-output .mw-datatable tr:hover{background-color:var(--background-color-progressive-subtle,#eaf3ff);color:var(--color-base,#333)}.mw-parser-output .mw-datatable{background-color:var(--background-color-base,#fff);color:var(--color-base,#333)}</style> <table class="mw-datatable wikitable sortable" style="text-align: center;"> <caption><span class="anchor" id="Comparison"></span> Comparison of LPDDR SDRAM generations </caption> <tbody><tr> <th scope="col" rowspan="2">Gene-<br />ration </th> <th scope="col" rowspan="2">Release<br />year </th> <th scope="col" colspan="3"><a href="/wiki/Chip_(computing)" class="mw-redirect" title="Chip (computing)">Chip</a> </th> <th scope="col" colspan="3"><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a> </th> <th scope="col" rowspan="2"><a href="/wiki/Voltage" title="Voltage">Voltage</a><br />(V) </th></tr> <tr style="line-height:120%"> <th scope="col"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a><br />(MHz) </th> <th scope="col">Cycle time<br />(ns) </th> <th scope="col"><a href="/wiki/Prefetch_buffer" class="mw-redirect" title="Prefetch buffer">Pre-<br />fetch</a> </th> <th scope="col">Clock rate<br />(MHz) </th> <th scope="col"><a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">Transfer rate</a><br />(<a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a>) </th> <th scope="col"><a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">Bandwidth</a><br />(MB/s) </th></tr> <tr> <th scope="row">1 </th> <td rowspan="2">2006 </td> <td>200 </td> <td> </td> <td rowspan="2">2<i>n</i> </td> <td>200 </td> <td>400 </td> <td>50 </td> <td rowspan="2">1.8 </td></tr> <tr> <th scope="row">1E </th> <td>266 </td> <td> </td> <td>266 </td> <td>533 </td> <td>66.63 </td></tr> <tr> <th scope="row">2 </th> <td rowspan="2">2009 </td> <td>200 </td> <td> </td> <td rowspan="2">4<i>n</i> </td> <td>400 </td> <td>800 </td> <td>100 </td> <td rowspan="2"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul style="text-align:center;"><li>1.2</li><li>1.8</li></ul></div> </td></tr> <tr> <th scope="row">2E </th> <td>266 </td> <td> </td> <td>533 </td> <td>1067 </td> <td>133.38 </td></tr> <tr> <th scope="row">3 </th> <td rowspan="2">2012 </td> <td>200 </td> <td> </td> <td rowspan="2">8<i>n</i> </td> <td>800 </td> <td>1600 </td> <td>200 </td> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul style="text-align:center;"><li>1.2</li><li>1.8</li></ul></div> </td></tr> <tr> <th scope="row">3E </th> <td>266 </td> <td> </td> <td>1067 </td> <td>2133 </td> <td>266.63 </td></tr> <tr> <th scope="row">4 </th> <td>2014 </td> <td>200 </td> <td> </td> <td rowspan="2">16<i>n</i> </td> <td>1600 </td> <td>3200 </td> <td>400 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul style="text-align:center;"><li>1.1</li><li>1.8</li></ul></div> </td></tr> <tr> <th scope="row">4X </th> <td>2017 </td> <td>266 </td> <td> </td> <td>2133 </td> <td>4267 </td> <td>533.38 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul style="text-align:center;"><li>0.6</li><li>1.1</li><li>1.8</li></ul></div> </td></tr> <tr> <th scope="row">5 </th> <td>2019 </td> <td>400 </td> <td> </td> <td rowspan="2">16<i>n</i> </td> <td>3200 </td> <td>6400 </td> <td>800 </td> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul style="text-align:center;"><li>0.5</li><li>1.05</li><li>1.8</li></ul></div> </td></tr> <tr> <th scope="row">5X </th> <td>2021 </td> <td>533 </td> <td> </td> <td>4267 </td> <td>8533 </td> <td>1,066.63 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="LPDDR(1)"><span id="LPDDR.281.29"></span>LPDDR(1)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=3" title="Edit section: LPDDR(1)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The original low-power DDR (sometimes retroactively called <b>LPDDR1</b>), released in 2006 is a slightly modified form of <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, with several changes to reduce overall power consumption. </p><p>Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> and <a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a> are two of the main providers of this technology, which is used in tablet and phone devices such as the <a href="/wiki/IPhone_3GS" title="IPhone 3GS">iPhone 3GS</a>, <a href="/wiki/IPad_(1st_generation)" title="IPad (1st generation)">original iPad</a>, <a href="/wiki/Samsung_Galaxy_Tab_7.0" title="Samsung Galaxy Tab 7.0">Samsung Galaxy Tab 7.0</a> and <a href="/wiki/Motorola_Droid_X" class="mw-redirect" title="Motorola Droid X">Motorola Droid X</a>.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="LPDDR2">LPDDR2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=4" title="Edit section: LPDDR2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d5/Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg/220px-Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d5/Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg/330px-Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d5/Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg/440px-Motorola_Xoom_-_Samsung_K4P4G154EC-FGC1_on_main_board-0122.jpg 2x" data-file-width="2886" data-file-height="2886" /></a><figcaption>Samsung K4P4G154EC-FGC1 4 Gbit LPDDR2 chip </figcaption></figure> <p>In 2009, the standards group <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> published JESD209-2, which defined a more dramatically revised low-power DDR interface.<sup id="cite_ref-lpddr2_4-0" class="reference"><a href="#cite_note-lpddr2-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> It is not compatible with either DDR1 or <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a>, but can accommodate any one of: </p> <ul><li>LPDDR2-S2: 2<i>n</i> prefetch memory (like DDR1),</li> <li>LPDDR2-S4: 4<i>n</i> prefetch memory (like DDR2), or</li> <li>LPDDR2-N: Non-volatile (<a href="/wiki/NAND_flash" class="mw-redirect" title="NAND flash">NAND flash</a>) memory.</li></ul> <p>Low-power states are similar to basic LPDDR, with some additional partial array refresh options. </p><p>Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz). </p><p>Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> CA bus. The commands are similar to <a href="/wiki/SDRAM#SDRAM_control_signals" class="mw-redirect" title="SDRAM">those of normal SDRAM</a>, except for the reassignment of the precharge and burst terminate opcodes: </p> <table class="wikitable" style="text-align:center; border-width:0px;"> <caption>LPDDR2/LPDDR3 command encoding<sup id="cite_ref-lpddr2_4-1" class="reference"><a href="#cite_note-lpddr2-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th rowspan="2">Operation </th> <td rowspan="17" style="border-width:0px; background-color:white"> </td> <th colspan="10" style="line-height:110%"><big>↗</big> Rising clock <big>↗</big> </th> <th colspan="10" style="line-height:110%"><big>↘</big> Falling clock <big>↘</big> </th></tr> <tr style="line-height:110%; vertical-align: top;"> <th>CA0<br /><small>(<span style="text-decoration:overline;">RAS</span>)</small></th> <th>CA1<br /><small>(<span style="text-decoration:overline;">CAS</span>)</small></th> <th>CA2<br /><small>(<span style="text-decoration:overline;">WE</span>)</small></th> <th>CA3</th> <th>CA4</th> <th>CA5</th> <th>CA6</th> <th>CA7</th> <th>CA8</th> <th>CA9 </th> <th>CA0<br /><small>(<span style="text-decoration:overline;">RAS</span>)</small></th> <th>CA1<br /><small>(<span style="text-decoration:overline;">CAS</span>)</small></th> <th>CA2<br /><small>(<span style="text-decoration:overline;">WE</span>)</small></th> <th>CA3</th> <th>CA4</th> <th>CA5</th> <th>CA6</th> <th>CA7</th> <th>CA8</th> <th>CA9 </th></tr> <tr> <td>No operation </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td colspan="17" bgcolor="lightgrey">— </td></tr> <tr> <td>Precharge all banks </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td colspan="15" bgcolor="lightgrey">— </td></tr> <tr> <td>Precharge one bank </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td colspan="2" bgcolor="lightgrey">—</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td colspan="10" bgcolor="lightgrey">— </td></tr> <tr> <td>Preactive (LPDDR2-N only) </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td>A30</td> <td>A31</td> <td>A32</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td>A20</td> <td>A21</td> <td>A22</td> <td>A23</td> <td>A24</td> <td>A25</td> <td>A26</td> <td>A27</td> <td>A28</td> <td>A29 </td></tr> <tr> <td>Burst terminate </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td colspan="16" bgcolor="lightgrey">— </td></tr> <tr> <td>Read (AP=auto-precharge) </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td colspan="2" bgcolor="lightgrey"><i>reserved</i></td> <td>C1</td> <td>C2</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C3</td> <td>C4</td> <td>C5</td> <td>C6</td> <td>C7</td> <td>C8</td> <td>C9</td> <td>C10</td> <td>C11 </td></tr> <tr> <td>Write (AP=auto-precharge) </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td colspan="2" bgcolor="lightgrey"><i>reserved</i></td> <td>C1</td> <td>C2</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C3</td> <td>C4</td> <td>C5</td> <td>C6</td> <td>C7</td> <td>C8</td> <td>C9</td> <td>C10</td> <td>C11 </td></tr> <tr> <td>Activate (R0–14=Row address) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td>R8</td> <td>R9</td> <td>R10</td> <td>R11</td> <td>R12</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td>R0</td> <td>R1</td> <td>R2</td> <td>R3</td> <td>R4</td> <td>R5</td> <td>R6</td> <td>R7</td> <td>R13</td> <td>R14 </td></tr> <tr> <td>Activate (LPDDR2-N only) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td>A15</td> <td>A16</td> <td>A17</td> <td>A18</td> <td>A19</td> <td bgcolor="PaleTurquoise">BA0</td> <td bgcolor="PaleTurquoise">BA1</td> <td bgcolor="PaleTurquoise">BA2 </td> <td>A5</td> <td>A6</td> <td>A7</td> <td>A8</td> <td>A9</td> <td>A10</td> <td>A11</td> <td>A12</td> <td>A13</td> <td>A14 </td></tr> <tr> <td>Refresh all banks (LPDDR2-Sx only) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td colspan="16" bgcolor="lightgrey">— </td></tr> <tr> <td>Refresh one bank (round-robin addressing) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td colspan="16" bgcolor="lightgrey">— </td></tr> <tr> <td>Mode register read (MA0–7=address) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td>MA0</td> <td>MA1</td> <td>MA2</td> <td>MA3</td> <td>MA4</td> <td>MA5 </td> <td>MA6</td> <td>MA7</td> <td colspan="8" bgcolor="lightgrey">— </td></tr> <tr> <td>Mode register write (OP0–7=data) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td>MA0</td> <td>MA1</td> <td>MA2</td> <td>MA3</td> <td>MA4</td> <td>MA5 </td> <td>MA6</td> <td>MA7</td> <td>OP0</td> <td>OP1</td> <td>OP2</td> <td>OP3</td> <td>OP4</td> <td>OP5</td> <td>OP6</td> <td>OP7 </td></tr></tbody></table> <p>Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses. </p><p>LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state: </p> <ul><li>If the chip is active, it freezes in place.</li> <li>If the command is a NOP (<span style="text-decoration:overline;">CS</span> low or CA0–2 = HHH), the chip idles.</li> <li>If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.</li> <li>If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)</li></ul> <p>The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a <a href="/wiki/Serial_presence_detect" title="Serial presence detect">serial presence detect</a> EEPROM, enough information is included to eliminate the need for one. </p><p>S2 devices smaller than 4 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">Gbit</a>, and S4 devices smaller than 1 Gbit have only four banks. They ignore the BA2 signal, and do not support per-bank refresh. </p><p>Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command. </p><p>Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array. </p> <div class="mw-heading mw-heading3"><h3 id="LPDDR3">LPDDR3</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=5" title="Edit section: LPDDR3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In May 2012, <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> published the JESD209-3 Low Power Memory Device Standard.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-lpddr3_7-0" class="reference"><a href="#cite_note-lpddr3-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600 MT/s and utilizes key new technologies: write-leveling and command/address training,<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> optional on-die termination (ODT), and low-I/O capacitance. LPDDR3 supports both package-on-package (PoP) and discrete packaging types. </p><p>The command encoding is identical to LPDDR2, using a 10-bit double data rate CA bus.<sup id="cite_ref-lpddr3_7-1" class="reference"><a href="#cite_note-lpddr3-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> However, the standard only specifies 8<i>n</i>-prefetch DRAM, and does not include the flash memory commands. </p><p>Products using LPDDR3 include the 2013 MacBook Air, <a href="/wiki/IPhone_5S" class="mw-redirect" title="IPhone 5S">iPhone 5S</a>, <a href="/wiki/IPhone_6" title="IPhone 6">iPhone 6</a>, <a href="/wiki/Nexus_10" title="Nexus 10">Nexus 10</a>, <a href="/wiki/Samsung_Galaxy_S4" title="Samsung Galaxy S4">Samsung Galaxy S4</a> (GT-I9500) and Microsoft <a href="/wiki/Surface_Pro_3" title="Surface Pro 3">Surface Pro 3</a> and 4.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> LPDDR3 went mainstream in 2013, running at 800 MHz DDR (1600 MT/s), offering bandwidth comparable to PC3-12800 <a href="/wiki/SODIMM" class="mw-redirect" title="SODIMM">notebook memory</a> in 2011 (12.8 GB/s of bandwidth).<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> To achieve this bandwidth, the controller must implement dual-channel memory. For example, this is the case for the Exynos 5 Dual<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> and the 5 Octa.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="LPDDR3E">LPDDR3E</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=6" title="Edit section: LPDDR3E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An "enhanced" version of the specification called LPDDR3E increases the data rate to 2133 MT/s. <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> introduced the first 4 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">gigabit</a> 20 nm-class LPDDR3 modules capable of transmitting data at up to 2,133 MT/s, more than double the performance of the older LPDDR2 which is only capable of 800 MT/s.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> Various <a href="/wiki/System_On_Chip" class="mw-redirect" title="System On Chip">SoCs</a> from various manufacturers also natively support 800 MHz LPDDR3 RAM. Such include the <a href="/wiki/Snapdragon_(system_on_chip)" class="mw-redirect" title="Snapdragon (system on chip)">Snapdragon</a> 600 and 800 from <a href="/wiki/Qualcomm" title="Qualcomm">Qualcomm</a><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> as well as some SoCs from the <a href="/wiki/Exynos_(system_on_chip)" class="mw-redirect" title="Exynos (system on chip)">Exynos</a> and <a href="/wiki/Allwinner_Technology" title="Allwinner Technology">Allwinner</a> series. </p> <div class="mw-heading mw-heading3"><h3 id="LPDDR4">LPDDR4</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=7" title="Edit section: LPDDR4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>On 14 March 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> On 30 December 2013, Samsung announced that it had developed the first 20 nm-class 8 gigabit (1 GB) LPDDR4 capable of transmitting data at 3,200 MT/s, thus providing 50 percent higher performance than the fastest LPDDR3 and consuming around 40 percent less energy at 1.1 volts.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p><p>On 25 August 2014, <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> published the JESD209-4 LPDDR4 Low Power Memory Device Standard.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-lpddr4_20-0" class="reference"><a href="#cite_note-lpddr4-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p><p>Significant changes include: </p> <ul><li>Doubling of the interface speed, and numerous consequent electrical changes, including changing the I/O standard to low-voltage swing-terminated logic (LVSTL)</li> <li>Doubling of the internal prefetch size, and minimum transfer size</li> <li>Change from a 10-bit DDR command/address bus to a 6-bit SDR bus</li> <li>Change from one 32-bit wide bus to two independent 16-bit wide buses</li> <li>Self-refresh is enabled by dedicated commands, rather than being controlled by the CKE line</li></ul> <p>The standard defines SDRAM packages containing two independent 16-bit access channels, each connected to up to two <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">dies</a> per package. Each channel is 16 data bits wide, has its own control/address pins, and allows access to 8 banks of DRAM. Thus, the package may be connected in three ways: </p> <ul><li>Data lines and control connected in parallel to a 16-bit data bus, and only chip selects connected independently per channel.</li> <li>To two halves of a 32-bit wide data bus, and the control lines in parallel, including chip select.</li> <li>To two independent 16-bit wide data buses</li></ul> <p>Each die provides 4, 6, 8, 12, or 16 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">gigabits</a> of memory, half to each channel. Thus, each bank is one sixteenth the device size. This is organized into the appropriate number (16 <a href="/wiki/Kilobit" class="mw-redirect" title="Kilobit">K</a> to 64 K) of 16384-bit (2048-byte) rows. Extension to 24 and 32 gigabits is planned, but it is not yet decided if this will be done by increasing the number of rows, their width, or the number of banks. </p><p>Larger packages providing double width (four channels) and up to four dies per pair of channels (8 dies total per package) are also defined. </p><p>Data is accessed in bursts of either 16 or 32 transfers (256 or 512 bits, 32 or 64 bytes, 8 or 16 cycles DDR). Bursts must begin on 64-bit boundaries. </p><p>Since the clock frequency is higher and the minimum burst length longer than earlier standards, control signals can be more highly multiplexed without the command/address bus becoming a bottleneck. LPDDR4 multiplexes the control and address lines onto a 6-bit single data rate CA bus. Commands require 2 clock cycles, and operations encoding an address (e.g., activate row, read or write column) require two commands. For example, to request a read from an idle chip requires four commands taking 8 clock cycles: Activate-1, Activate-2, Read, CAS-2. </p><p>The chip select line (CS) is active-<i>high</i>. The first cycle of a command is identified by chip select being high; it is low during the second cycle. </p> <table class="wikitable" style="text-align:center; border-width:0px;"> <caption>LPDDR4 command encoding<sup id="cite_ref-lpddr4_20-1" class="reference"><a href="#cite_note-lpddr4-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 151">: 151 </span></sup> </caption> <tbody><tr> <th colspan="6">First cycle (CS high) </th> <td rowspan="20" style="border-width:0px; background-color:#FFF;"> </td> <th colspan="6">Second cycle (CS low) </th> <td rowspan="20" style="border-width:0px; background-color:#FFF;"> </td> <th rowspan="2">Operation </th></tr> <tr> <th>CA5</th> <th>CA4</th> <th>CA3</th> <th>CA2</th> <th>CA1</th> <th>CA0 </th> <th>CA5</th> <th>CA4</th> <th>CA3</th> <th>CA2</th> <th>CA1</th> <th>CA0 </th></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td align="left">No operation </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>0</td> <td>OP4</td> <td>OP3</td> <td>OP2</td> <td>OP1</td> <td>1</td> <td align="left">Multi-purpose command </td></tr> <tr> <td bgcolor="paleturquoise">AB</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="3" bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td align="left">Precharge (AB: all banks) </td></tr> <tr> <td bgcolor="paleturquoise">AB</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="3" bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td align="left">Refresh (AB: all banks) </td></tr> <tr> <td bgcolor="lightgrey">—</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td align="left">Self-refresh entry </td></tr> <tr> <td bgcolor="plum">BL</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C9</td> <td bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td align="left">Write-1 (+CAS-2) </td></tr> <tr> <td bgcolor="lightgrey">—</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td align="left">Self-refresh exit </td></tr> <tr> <td bgcolor="plum">0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C9</td> <td bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td align="left">Masked write-1 (+CAS-2) </td></tr> <tr> <td bgcolor="lightgrey">—</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td bgcolor="plum">BL</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C9</td> <td bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td align="left">Read-1 (+CAS-2) </td></tr> <tr> <td>C8</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>C7</td> <td>C6</td> <td>C5</td> <td>C4</td> <td>C3</td> <td>C2</td> <td align="left">CAS-2 </td></tr> <tr> <td colspan="2" bgcolor="lightgrey">—</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td>OP7</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>MA5</td> <td>MA4</td> <td>MA3</td> <td>MA2</td> <td>MA1</td> <td>MA0</td> <td rowspan="2" align="left">Mode register write-1 and -2<br />MA: address, OP: data </td></tr> <tr> <td>OP6</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>OP5</td> <td>OP4</td> <td>OP3</td> <td>OP2</td> <td>OP1</td> <td>OP0 </td></tr> <tr> <td bgcolor="lightgrey">—</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>MA5</td> <td>MA4</td> <td>MA3</td> <td>MA2</td> <td>MA1</td> <td>MA0</td> <td align="left">Mode register read (+CAS-2) </td></tr> <tr> <td bgcolor="lightgrey">—</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="6" bgcolor="lightgrey">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td>R15</td> <td>R14</td> <td>R13</td> <td>R12</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td>R11</td> <td>R10</td> <td>R16</td> <td bgcolor="paleturquoise">BA2</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0</td> <td rowspan="2" align="left">Activate-1 and -2 </td></tr> <tr> <td>R9</td> <td>R8</td> <td>R7</td> <td>R6</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td>R5</td> <td>R4</td> <td>R3</td> <td>R2</td> <td>R1</td> <td>R0 </td></tr></tbody></table> <p>The CAS-2 command is used as the second half of all commands that perform a transfer across the data bus, and provides low-order column address bits: </p> <ul><li>Read commands must begin on a column address which is a multiple of 4; there is no provision for communicating a non-zero C0 or C1 address bit to the memory.</li> <li>Write commands must begin on a column address which is a multiple of 16; C2 and C3 must be zero for a write command.</li> <li>Mode register read and some multi-purpose commands must also be followed by a CAS-2 command, however all the column bits must be zero (low).</li></ul> <p>The burst length can be configured to be 16, 32, or dynamically selectable by the BL bit of read and write operations. </p><p>One DMI (data mask/invert) signal is associated with each 8 data lines, and can be used to minimize the number of bits driven high during data transfers. When high, the other 8 bits are complemented by both transmitter and receiver. If a byte contains five or more 1 bits, the DMI signal can be driven high, along with three or fewer data lines. As signal lines are terminated low, this reduces power consumption. </p><p>(An alternative usage, where DMI is used to limit the number of data lines which <i>toggle</i> on each transfer to at most 4, minimises crosstalk. This may be used by the memory controller during writes, but is not supported by the memory devices.) </p><p>Data bus inversion can be separately enabled for reads and writes. For masked writes (which have a separate command code), the operation of the DMI signal depends on whether write inversion is enabled. </p> <ul><li>If DBI on writes is disabled, a high level on DMI indicates that the corresponding data byte is to be ignored and not written</li> <li>If DBI on writes is enabled, a <i>low</i> level on DMI, combined with a data byte with 5 or more bits set, indicates a data byte to be ignored and not written.</li></ul> <p>LPDDR4 also includes a mechanism for "targeted row refresh" to avoid corruption due to "<a href="/wiki/Row_hammer" title="Row hammer">row hammer</a>" on adjacent rows. A special sequence of three activate/precharge sequences specifies the row which was activated more often than a device-specified threshold (200,000 to 700,000 per refresh cycle). Internally, the device refreshes <a href="/wiki/Physically_based_rendering" title="Physically based rendering">physically</a> adjacent rows rather than the one specified in the activate command.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-lpddr4_20-2" class="reference"><a href="#cite_note-lpddr4-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 153–54">: 153–54 </span></sup> </p> <div class="mw-heading mw-heading4"><h4 id="LPDDR4X">LPDDR4X</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=8" title="Edit section: LPDDR4X"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Semiconductor</a> proposed an LPDDR4 variant that it called LPDDR4X.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 11">: 11 </span></sup> LPDDR4X is identical to LPDDR4 except additional power is saved by reducing the I/O voltage (Vddq) from 1.1 V to 0.6 V. On 9 January 2017, SK Hynix announced 8 and 16 GB LPDDR4X packages.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> JEDEC published the LPDDR4X standard on 8 March 2017.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> Aside from the lower voltage, additional improvements include a single-channel die option for smaller applications, new MCP, PoP and IoT packages, and additional definition and timing improvements for the highest 4266 MT/s speed grade. </p> <div class="mw-heading mw-heading3"><h3 id="LPDDR5">LPDDR5</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=9" title="Edit section: LPDDR5"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>On 19 February 2019, <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> published the JESD209-5, Standard for Low Power Double Data Rate 5 (LPDDR5).<sup id="cite_ref-lpddr5_26-0" class="reference"><a href="#cite_note-lpddr5-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Samsung" title="Samsung">Samsung</a> announced it had working prototype LPDDR5 chips in July 2018. LPDDR5 introduces the following changes:<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Data transfer rate is increased to 6400 Mbit/s per pin</li> <li><a href="/wiki/Differential_signalling" title="Differential signalling">Differential</a> clocks are used (3200 MHz, DDR)</li> <li>Prefetch is <i>not</i> doubled again, but remains 16<i>n</i></li> <li>The number of banks is increased to 16, divided into four <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-like bank groups</li> <li>Power-saving improvements:<sup id="cite_ref-lpddr5_26-1" class="reference"><a href="#cite_note-lpddr5-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> <ul><li>Data-Copy and Write-X (all one or all zero) commands to decrease data transfer</li> <li>Dynamic frequency and voltage scaling</li></ul></li> <li>A new clocking architecture, where commands use a quarter-speed master clock (CK), while data is transferred using full-speed Write Clock (WCK) & Read Strobe (RDQS) signals which are enabled only when necessary<sup id="cite_ref-lpddr5_26-2" class="reference"><a href="#cite_note-lpddr5-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></li> <li>One set of full-speed clocks per byte (vs. per 16 bits in LPDDR4)</li> <li>Elimination of the Clock Enable (CKE) pin; instead low-power mode is entered by a command over the CA bus, and lasts until the <a href="/wiki/Chip_select" title="Chip select">chip select</a> signal next goes high</li></ul> <p>AMD Van Gogh, Intel <a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake</a>, <a href="/wiki/Apple_silicon" title="Apple silicon">Apple silicon</a> (M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), <a href="/wiki/HiSilicon#Kirin_9000_5G/4G_&_Kirin_9000E" title="HiSilicon">Huawei Kirin 9000</a> and <a href="/wiki/List_of_Qualcomm_Snapdragon_processors#Snapdragon_888/888+_5G_(2021)" class="mw-redirect" title="List of Qualcomm Snapdragon processors">Snapdragon 888</a> memory controllers support LPDDR5. </p><p>The doubling of the transfer rate, and the quarter-speed master clock, results in a master clock which is half the frequency of a similar LPDDR4 clock. The command (CA) bus is widened to 7 bits, and commands are transferred at double data rate, so commands end up being sent at the same rate as LPDDR4. </p> <table class="wikitable" style="text-align:center; border-width:0px;"> <caption>LPDDR5 command encoding<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th colspan="7">↗ Rising clock ↗ </th> <td rowspan="24" style="border-width:0px; background-color:#FFF;"> </td> <th colspan="7">↘ Falling clock ↘ </th> <td rowspan="24" style="border-width:0px; background-color:#FFF;"> </td> <th rowspan="2">Operation </th></tr> <tr> <th>CA6</th> <th>CA5</th> <th>CA4</th> <th>CA3</th> <th>CA2</th> <th>CA1</th> <th>CA0 </th> <th>CA6</th> <th>CA5</th> <th>CA4</th> <th>CA3</th> <th>CA2</th> <th>CA1</th> <th>CA0 </th></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" bgcolor="lightgrey">— </td> <td align="left">No operation </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" bgcolor="lightgrey">— </td> <td align="left">Power-down entry </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>— L —</b> </td> <td align="left">Read <a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a> </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>— L —</b> </td> <td align="left">Write FIFO </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" bgcolor="lightgrey">— </td> <td align="left" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>— L —</b> </td> <td align="left">Read DQ Calibration </td></tr> <tr> <td>OP7</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>OP6</td> <td>OP5</td> <td>OP4</td> <td>OP3</td> <td>OP2</td> <td>OP1</td> <td>OP0 </td> <td align="left">Multi-purpose command </td></tr> <tr> <td>OP7</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>OP6</td> <td>OP5</td> <td>OP4</td> <td>OP3</td> <td>OP2</td> <td>OP1</td> <td>OP0 </td> <td align="left">Mode register write 2 </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td colspan="7" bgcolor="lightgrey">—</td> <td align="left">Self-refresh exit </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>PD</td> <td>DSE</td> <td colspan="5" bgcolor="lightgrey">—</td> <td align="left">Self-refresh entry </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>MA6</td> <td>MA5</td> <td>MA4</td> <td>MA3</td> <td>MA2</td> <td>MA1</td> <td>MA0 </td> <td align="left">Mode register read </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td>MA6</td> <td>MA5</td> <td>MA4</td> <td>MA3</td> <td>MA2</td> <td>MA1</td> <td>MA0 </td> <td align="left">Mode register write 1 </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td bgcolor="paleturquoise">AB</td> <td>SB1</td> <td>SB0</td> <td>RFM</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Refresh </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td bgcolor="paleturquoise">AB</td> <td colspan="2" bgcolor="lightgrey">—</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Precharge </td></tr> <tr> <td>C5</td> <td>C4</td> <td>C3</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C2</td> <td>C1</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Write 32 </td></tr> <tr> <td>WS_<br />FS</td> <td>WS_<br />RD</td> <td>WS_<br />WR</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td><span style="font-size: 85%;">WXSB</span><br />/B3</td> <td><span style="font-size: 85%;">WXSA</span></td> <td>WRX</td> <td>DC3</td> <td>DC2</td> <td>DC1</td> <td>DC0 </td> <td align="left">Column address select </td></tr> <tr> <td>C5</td> <td>C4</td> <td>C3</td> <td>C0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C2</td> <td>C1</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Masked Write </td></tr> <tr> <td>C5</td> <td>C4</td> <td>C3</td> <td>C0</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C2</td> <td>C1</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Write </td></tr> <tr> <td>C5</td> <td>C4</td> <td>C3</td> <td>C0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C2</td> <td>C1</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Read </td></tr> <tr> <td>C5</td> <td>C4</td> <td>C3</td> <td>C0</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">AP</td> <td>C2</td> <td>C1</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Read 32 </td></tr> <tr> <td>R10</td> <td>R9</td> <td>R8</td> <td>R7</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><b>L</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td>R6</td> <td>R5</td> <td>R4</td> <td>R3</td> <td>R2</td> <td>R1</td> <td>R0 </td> <td align="left">Activate 2 </td></tr> <tr> <td>R17</td> <td>R16</td> <td>R15</td> <td>R14</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no"><b>H</b> </td> <td>R13</td> <td>R12</td> <td>R11</td> <td bgcolor="paleturquoise">BG1</td> <td bgcolor="paleturquoise">BG0</td> <td bgcolor="paleturquoise">BA1</td> <td bgcolor="paleturquoise">BA0 </td> <td align="left">Activate 1 </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1216972533">.mw-parser-output .col-begin{border-collapse:collapse;padding:0;color:inherit;width:100%;border:0;margin:0}.mw-parser-output .col-begin-small{font-size:90%}.mw-parser-output .col-break{vertical-align:top;text-align:left}.mw-parser-output .col-break-2{width:50%}.mw-parser-output .col-break-3{width:33.3%}.mw-parser-output .col-break-4{width:25%}.mw-parser-output .col-break-5{width:20%}@media(max-width:720px){.mw-parser-output .col-begin,.mw-parser-output .col-begin>tbody,.mw-parser-output .col-begin>tbody>tr,.mw-parser-output .col-begin>tbody>tr>td{display:block!important;width:100%!important}.mw-parser-output .col-break{padding-left:0!important}}</style><div> <table class="col-begin" role="presentation"> <tbody><tr> <td class="col-break" style="width: 35%;"> <ul><li>B<i>n</i> = Burst address bit</li> <li>C<i>n</i> = Column address bit</li> <li>R<i>n</i> = Column address bit</li> <li>BA<i>n</i> = Bank address bit</li> <li>BG<i>n</i> = Bank group address bit</li> <li>AB = All banks (ignore BG & BA)</li> <li>AP = Auto-precharge</li></ul> </td> <td class="col-break" style="width: 65%;"> <ul><li>MA<i>n</i> = Mode register address bit</li> <li>OP<i>n</i> = Operation, or mode register data</li> <li>WS_<i>xx</i> = WCK synchronization</li> <li>WRX = Write X; do not transfer data, but fill with all-zero or all-one</li> <li>WXSA, WXSB = Write X select, value to be written</li> <li>PD = Power down</li> <li>DSE = Deep sleep enable</li></ul> <p>  </p> </td></tr></tbody></table></div> <p>Compared to earlier standards, the nomenclature for column addresses has changed. Both LPDDR4 and LPDDR5 allow up to 10 bits of column address, but the names are different. LPDDR4's C0–C9 are renamed B0–B3 and C0–C5. As with LPDDR4, writes must start at a multiple-of-16 address with B0–B3 zero, but reads may request a burst be transferred in a different order by specifying a non-zero value for B3. </p><p>As with LPDDR4, to read some data requires 4 commands: two activate commands to select a row, then a CAS and a read command to select a column. Unlike LPDDR4, the CAS command comes <i>before</i> the read or write command. In fact, it is something of a misnomer, in that it does not select a column at all. Instead, its primary function is to prepare the DRAM to synchronize with the imminent start of the high-speed WCK clock. The WS_FS, WS_RD and WS_WR bits select various timings, with the _RD and _WR options optimized for an immediately following read or write command, while the _FS option starts the clock immediately, and may be followed by multiple reads or writes, accessing multiple banks. </p><p>CAS also specifies the "write X" option. If the WRX bit is set, writes do not transfer data, but rather fill the burst with all-zeros or all-ones, under the control of the WXS (write-X select) bit. This takes the same amount of time, but saves energy. </p><p>In addition to the usual bursts of 16, there are commands for performing double-length bursts of 32. Reads (but not writes) may specify a starting position within the 32-word aligned burst using the C0 and B3 bits. </p> <div class="mw-heading mw-heading4"><h4 id="LPDDR5X">LPDDR5X</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=10" title="Edit section: LPDDR5X"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>On 28 July 2021, JEDEC published the JESD209-5B, Standard for Low Power Double Data Rate 5/5X (LPDDR5/5X)<sup id="cite_ref-lpddr5X_30-0" class="reference"><a href="#cite_note-lpddr5X-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> with the following changes: </p> <ul><li>Speed extension up to 8533 Mbit/s</li> <li>Signal integrity improvements with tx/rx equalization</li> <li>Reliability improvements via the new Adaptive Refresh Management feature</li></ul> <p>On 9 November 2021, Samsung announced that the company has developed the industry's first LPDDR5X DRAM. Samsung's implementation involves 16-gigabit (2 GB) dies, on a <a href="/wiki/14_nm_process" title="14 nm process">14 nm process</a> node, with modules with up to 32 dies (64 GB) in a single package. According to the company, the new modules would use 20% less power than LPDDR5.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> According to Andrei Frumusanu of <i><a href="/wiki/AnandTech" title="AnandTech">AnandTech</a></i>, LPDDR5X in <a href="/wiki/System_on_a_chip" title="System on a chip">SoCs</a> and other products was expected for the 2023 generation of devices.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p><p>On 19 November 2021, Micron announced that Mediatek has validated its LPDDR5X DRAM for Mediatek's Dimensity 9000 5G SoC.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </p><p>On 25 January 2023 <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> announced "Low Power Double Data Rate 5 Turbo" (LPDDR5T) chips with a bandwidth of 9.6 Gbit/s.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> It operates in the ultra-low voltage range of <span class="nowrap"><span data-sort-value="7000101000000000000♠"></span>1.01–1.12 V</span> set by <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a>. It has been incorporated into the LPDDR5X standard as LPDDR5X-9600 making "LPDDR5T" a brand name.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><br />MediaTek Dimensity 9300 and Qualcomm Snapdragon 8 Gen 3 supports LPDDR5T. </p><p>On 17 April 2024 <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> announced LPDDR5X-10700 with 25% higher bandwidth, 30% higher capacity and 25% improved power efficiency than previous LPDDR5X generations. This is achieved through a new <a href="/wiki/14_nm_process" title="14 nm process">12 nm process</a> that allows the chips to be more efficient while also being small enough to fit capacities of up to 32 GB in a single package.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p><p>On 16 July 2024 Samsung has completed validation of the industry's fastest LPDDR5X DRAM, capable of operating at speeds up to 10.7Gbit/s, for use in MediaTek's upcoming flagship Dimensity 9400 SoC.<sup id="cite_ref-:0_1-1" class="reference"><a href="#cite_note-:0-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="LPDDR6">LPDDR6</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=11" title="Edit section: LPDDR6"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following standard is under development.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> Planned extensions include: </p> <ul><li>Speed extension to 8.8–17.6 Gbit/s/pin</li> <li>CA bus further narrowed to 4 bits</li> <li>Data bus width of 12 bits per channel</li> <li>Bursts of 24 transfers × 12 pins = 288 bits: <ul><li>256 data bits, plus</li> <li>16 tag/ECC bits stored by array, plus</li> <li>16 bits for data bus inversion <i>or</i> link ECC, not stored.</li></ul></li> <li><a href="/wiki/CAMM2" class="mw-redirect" title="CAMM2">CAMM2</a><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=12" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns 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class="mw-cite-backlink">^ <a href="#cite_ref-:0_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:0_1-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://blogs.synopsys.com/committedtomemory/2014/01/10/when-is-lpddr3-not-lpddr3-when-its-ddr3l/">"When is LPDDR3 not LPDDR3? When it's DDR3L..."</a> <i>Committed to Memory blog</i><span class="reference-accessdate">. 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title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=TomsHardware.com&rft.atitle=Leak+suggests+that+DDR6+development+has+already+started%2C+aiming+for+21+GT%2Fs&rft.date=2024-05-23&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fpc-components%2Fdram%2Fleak-suggests-that-ddr6-development-has-already-started-aiming-for-21-gts&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALPDDR" class="Z3988"></span></span> </li> <li id="cite_note-40"><span class="mw-cite-backlink"><b><a href="#cite_ref-40">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://www.jedec.org/news/pressreleases/jedec-unveils-plans-ddr5-mrdimm-and-lpddr6-camm-standards-propel-high-performance">"JEDEC Unveils Plans for DDR5 MRDIMM and LPDDR6 CAMM Standards to Propel High-Performance Computing and AI"</a> (Press release). <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a>. 22 July 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=JEDEC+Unveils+Plans+for+DDR5+MRDIMM+and+LPDDR6+CAMM+Standards+to+Propel+High-Performance+Computing+and+AI&rft.pub=JEDEC&rft.date=2024-07-22&rft_id=https%3A%2F%2Fwww.jedec.org%2Fnews%2Fpressreleases%2Fjedec-unveils-plans-ddr5-mrdimm-and-lpddr6-camm-standards-propel-high-performance&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALPDDR" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=LPDDR&action=edit&section=14" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://www.micron.com/products/memory/dram-components/lpddr">Micron</a></li> <li><a rel="nofollow" class="external text" href="https://semiconductor.samsung.com/dram/lpddr/">Samsung</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110829044651/http://www.elpida.com/en/products/mobile.html">Elpida</a></li> <li><a rel="nofollow" class="external text" href="http://www.nanya.com/PageEdition1.aspx?Menu_ID=138&lan=en-us&def=230&isPrint=&KeyWords=">Nanya</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20141021194351/http://www.nanya.com/PageEdition1.aspx?Menu_ID=138&lan=en-us&def=230&isPrint=&KeyWords=">Archived</a> 21 October 2014 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li> <li>JEDEC pages: <a rel="nofollow" class="external text" href="http://www.jedec.org/standards-documents/docs/jesd209-3c">LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)</a></li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output 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title="Template talk:DRAM"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:DRAM" title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)148" style="font-size:114%;margin:0 4em"><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a></li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a></li></ul></li> <li><a class="mw-selflink selflink">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Timeline" title="Synchronous dynamic random-access memory">SDRAM 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