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<span class="vector-toc-numb">1.4</span> <span>Licensing</span> </div> </a> <ul id="toc-Licensing-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Continued_availability" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Continued_availability"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5</span> <span>Continued availability</span> </div> </a> <ul id="toc-Continued_availability-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-J_Core" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#J_Core"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6</span> <span>J Core</span> </div> </a> <ul id="toc-J_Core-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Models" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Models"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Models</span> </div> </a> <button aria-controls="toc-Models-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Models subsection</span> </button> <ul id="toc-Models-sublist" class="vector-toc-list"> <li id="toc-SH-2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>SH-2</span> </div> </a> <ul id="toc-SH-2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SH-2A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-2A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>SH-2A</span> </div> </a> <ul id="toc-SH-2A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SH-3_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-3_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>SH-3</span> </div> </a> <ul id="toc-SH-3_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SH-4_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-4_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>SH-4</span> </div> </a> <ul id="toc-SH-4_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SH-5" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-5"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>SH-5</span> </div> </a> <ul id="toc-SH-5-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SH-6" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SH-6"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>SH-6</span> </div> </a> <ul id="toc-SH-6-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>References</span> </div> </a> <button aria-controls="toc-References-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle References subsection</span> </button> <ul id="toc-References-sublist" class="vector-toc-list"> <li id="toc-Citations" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Citations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Citations</span> </div> </a> <ul id="toc-Citations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bibliography" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bibliography"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Bibliography</span> </div> </a> <ul id="toc-Bibliography-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">SuperH</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" 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Available in 17 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-17" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">17 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/SuperH" title="SuperH – German" lang="de" hreflang="de" data-title="SuperH" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/SuperH" title="SuperH – Spanish" lang="es" hreflang="es" data-title="SuperH" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/SuperH" title="SuperH – French" lang="fr" hreflang="fr" data-title="SuperH" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%8A%88%ED%8D%BCH" title="슈퍼H – Korean" lang="ko" hreflang="ko" data-title="슈퍼H" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/SuperH" title="SuperH – Italian" lang="it" hreflang="it" data-title="SuperH" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/SuperH" title="SuperH – Lithuanian" lang="lt" hreflang="lt" data-title="SuperH" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/SuperH" title="SuperH – Hungarian" lang="hu" hreflang="hu" data-title="SuperH" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/SuperH" title="SuperH – Dutch" lang="nl" hreflang="nl" data-title="SuperH" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/SuperH" title="SuperH – Japanese" lang="ja" hreflang="ja" data-title="SuperH" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/SuperH" title="SuperH – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="SuperH" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/SuperH" title="SuperH – Polish" lang="pl" hreflang="pl" data-title="SuperH" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/SuperH" title="SuperH – Portuguese" lang="pt" hreflang="pt" data-title="SuperH" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/SuperH" title="SuperH – Russian" lang="ru" hreflang="ru" data-title="SuperH" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/SuperH" title="SuperH – Serbian" lang="sr" hreflang="sr" data-title="SuperH" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/SuperH" title="SuperH – Finnish" lang="fi" hreflang="fi" data-title="SuperH" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/SuperH" title="SuperH – Ukrainian" lang="uk" hreflang="uk" data-title="SuperH" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/SuperH" title="SuperH – Chinese" lang="zh" hreflang="zh" data-title="SuperH" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q1205020#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/SuperH" title="View the content page [c]" accesskey="c"><span>Article</span></a></li><li id="ca-talk" class="vector-tab-noicon mw-list-item"><a href="/wiki/Talk:SuperH" rel="discussion" title="Discuss improvements to the content page [t]" accesskey="t"><span>Talk</span></a></li> </ul> </div> </div> <div id="vector-variants-dropdown" class="vector-dropdown emptyPortlet" > <input type="checkbox" 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class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-appearance.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-appearance.unpin">hide</button> </div> </div> </div> </nav> </div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=Hitachi_SH-4&redirect=no" class="mw-redirect" title="Hitachi SH-4">Hitachi SH-4</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Instruction set architecture by Hitachi</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">SuperH (SH)</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data"><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a></td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data">32-bit (32 → 64)</td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">1992<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data">RISC</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">SH-2: 16-bit instructions<br />SH-2A and newer: mixed 16- and 32-bit instructions</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Bi</td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Yes, and royalty-free<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></td></tr></tbody></table> <p><b>SuperH</b> (or <b>SH</b>) is a <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> <a href="/wiki/Reduced_instruction_set_computing" class="mw-redirect" title="Reduced instruction set computing">reduced instruction set computing</a> (RISC) <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA) developed by <a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> and currently produced by <a href="/wiki/Renesas" class="mw-redirect" title="Renesas">Renesas</a>. It is implemented by <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> and <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> for <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>. </p><p>At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the <a href="/wiki/Processor_register" title="Processor register">register file</a> was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and <a href="/wiki/Processor_cache" class="mw-redirect" title="Processor cache">processor cache</a> efficiency. </p><p>Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the <a href="/wiki/Machine_code" title="Machine code">machine code</a> to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a <a href="/wiki/Compressed_instruction_set" title="Compressed instruction set">compressed instruction set</a> and is also used by other companies, the most notable example being <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> for its <a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb</a> instruction set. </p><p>In 2015, many of the original <a href="/wiki/Patent" title="Patent">patents</a> for the SuperH architecture expired and the SH-2 CPU was reimplemented as <a href="/wiki/Open_source_hardware" class="mw-redirect" title="Open source hardware">open source hardware</a> under the name <a href="#J_Core">J2</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="SH-1_and_SH-2">SH-1 and SH-2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=2" title="Edit section: SH-1 and SH-2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:HD6417095_01.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HD6417095_01.jpg/250px-HD6417095_01.jpg" decoding="async" width="150" height="139" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HD6417095_01.jpg/330px-HD6417095_01.jpg 2x" data-file-width="560" data-file-height="519" /></a><figcaption>SH-2 on Sega 32X and Sega Saturn</figcaption></figure> <p>The SuperH processor core family was first developed by <a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> in the early 1990s. The design concept was for a single <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> (ISA) that would be <a href="/wiki/Upward_compatible" class="mw-redirect" title="Upward compatible">upward compatible</a> across a series of <a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">CPU cores</a>. </p><p>In the past, this sort of design problem would have been solved using <a href="/wiki/Microcode" title="Microcode">microcode</a>, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models. </p><p>One of the key realizations during the development of the <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">MUL</code>, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">DMULS</code> and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">DMULU</code>, whereas the SH-1 would cause a trap if these were encountered.<sup id="cite_ref-FOOTNOTEProgram19961_3-0" class="reference"><a href="#cite_note-FOOTNOTEProgram19961-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.<sup id="cite_ref-FOOTNOTEProgram19961_3-1" class="reference"><a href="#cite_note-FOOTNOTEProgram19961-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> The SH-1 and the SH-2 were used in the <a href="/wiki/Sega_Saturn" title="Sega Saturn">Sega Saturn</a>, <a href="/wiki/Sega_32X" class="mw-redirect" title="Sega 32X">Sega 32X</a> and <a href="/wiki/Capcom_CPS-3" class="mw-redirect" title="Capcom CPS-3">Capcom CPS-3</a>.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>The ISA uses <a href="/wiki/16-bit" class="mw-redirect" title="16-bit">16-bit</a> instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">main memory</a> and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.<sup id="cite_ref-FOOTNOTEProgram199630–33_5-0" class="reference"><a href="#cite_note-FOOTNOTEProgram199630–33-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one <a href="/wiki/Delay_slot" title="Delay slot">delay slot</a>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="SH-3">SH-3</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=3" title="Edit section: SH-3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A few years later, the SH-3 core was added to the family; new features included another <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> concept, a <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.<sup id="cite_ref-FOOTNOTEProgram19961_3-2" class="reference"><a href="#cite_note-FOOTNOTEProgram19961-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> The SH-3 was <a href="/wiki/Endianness#Bi-endian_hardware" title="Endianness">bi-endian</a>, running in either big-endian or little-endian byte ordering. </p><p>The SH-3 core also added a <a href="/wiki/Digital_signal_processing" title="Digital signal processing">DSP</a> extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated <a href="/wiki/Multiply%E2%80%93accumulate" class="mw-redirect" title="Multiply–accumulate">MAC</a>-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core. </p><p>Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="SH-4">SH-4</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=4" title="Edit section: SH-4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1997, Hitachi and <a href="/wiki/STMicroelectronics" title="STMicroelectronics">STMicroelectronics</a> (STM) started collaborating on the design of the SH-4 for the <a href="/wiki/Dreamcast" title="Dreamcast">Dreamcast</a>. SH-4 featured <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> (2-way) instruction execution and a <a href="/wiki/Vector_processor" title="Vector processor">vector</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (particularly suited to <a href="/wiki/3D_graphics" class="mw-redirect" title="3D graphics">3D graphics</a>). Standard chips based on the SH-4 were introduced around 1998.<sup id="cite_ref-sh5_8-0" class="reference"><a href="#cite_note-sh5-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Licensing">Licensing</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=5" title="Edit section: Licensing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In early 2001, Hitachi and STM formed the <a href="/wiki/Patent_holding_company" title="Patent holding company">IP company</a> SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.<sup id="cite_ref-sh5_8-1" class="reference"><a href="#cite_note-sh5-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>In 2003, Hitachi and <a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi Electric</a> formed a joint-venture called <a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas Technology</a>, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Renesas Technology later became Renesas Electronics, following their merger with <a href="/wiki/NEC_Electronics" class="mw-redirect" title="NEC Electronics">NEC Electronics</a>. </p><p>The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> instructions. In SHmedia mode the destination of a <a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">branch</a> (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> processors have a 16-bit <a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb</a> mode (ARM licensed several patents from SuperH for Thumb<sup id="cite_ref-lwn_11-0" class="reference"><a href="#cite_note-lwn-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>) and <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding. </p><p>The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Continued_availability">Continued availability</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=6" title="Edit section: Continued availability"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Since 2010, the SuperH CPU cores, architecture and products are with <a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas Electronics</a> and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from <a href="/wiki/Arm_Ltd." class="mw-redirect" title="Arm Ltd.">Arm Ltd.</a>, with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including <a href="/wiki/Arm_architecture" class="mw-redirect" title="Arm architecture">Arm</a>, <a href="/wiki/RX_microcontroller_family" class="mw-redirect" title="RX microcontroller family">RX</a>, and <a href="/wiki/V850" title="V850">RH850</a>. </p> <div class="mw-heading mw-heading3"><h3 id="J_Core">J Core</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=7" title="Edit section: J Core"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/Samsung_Galaxy_J2_Core" title="Samsung Galaxy J2 Core">Samsung Galaxy J2 Core</a>.</div> <p>The last of the SH-2 patents expired in 2014. At <a href="/wiki/LinuxCon" class="mw-redirect" title="LinuxCon">LinuxCon</a> Japan 2015, j-core developers presented a <a href="/wiki/Clean_room_design" class="mw-redirect" title="Clean room design">cleanroom reimplemention</a> of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired <a href="/wiki/Trademarks" class="mw-redirect" title="Trademarks">trademarks</a>).<sup id="cite_ref-lwn_11-1" class="reference"><a href="#cite_note-lwn-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-0pf_jcore_13-0" class="reference"><a href="#cite_note-0pf_jcore-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> Subsequently, a design walkthrough was presented at ELC 2016.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>The <a href="/wiki/Open-source_license" title="Open-source license">open source</a> <a href="/wiki/Berkeley_Software_Distribution" title="Berkeley Software Distribution">BSD</a>-licensed <a href="/wiki/VHDL" title="VHDL">VHDL</a> code for the J2 core has been proven on <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGAs</a> and on <a href="/wiki/ASIC" class="mw-redirect" title="ASIC">ASICs</a> manufactured on <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s <a href="/wiki/180_nm" class="mw-redirect" title="180 nm">180 nm</a> process, and is capable of booting <a href="/wiki/%CE%9CClinux" title="ΜClinux">μClinux</a>.<sup id="cite_ref-lwn_11-2" class="reference"><a href="#cite_note-lwn-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016–2017.<sup id="cite_ref-lwn_11-3" class="reference"><a href="#cite_note-lwn-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The date of the event predicted near this tag has passed. (June 2022)">needs update</span></a></i>]</sup> </p><p>Several features of SuperH have been cited as motivations for designing new cores based on this architecture:<sup id="cite_ref-lwn_11-4" class="reference"><a href="#cite_note-lwn-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p> <ul><li>High <a href="/wiki/Code_density" class="mw-redirect" title="Code density">code density</a> compared to other 32-bit <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">ISAs</a> such as <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> or <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a><sup id="cite_ref-weaver2015_15-0" class="reference"><a href="#cite_note-weaver2015-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> important for cache and memory bandwidth performance</li> <li>Existing <a href="/wiki/C_compiler" class="mw-redirect" title="C compiler">compiler</a> and <a href="/wiki/Operating_system" title="Operating system">operating system</a> support (<a href="/wiki/Linux" title="Linux">Linux</a>, <a href="/wiki/Windows_Embedded" class="mw-redirect" title="Windows Embedded">Windows Embedded</a>, <a href="/wiki/QNX" title="QNX">QNX</a><sup id="cite_ref-0pf_jcore_13-1" class="reference"><a href="#cite_note-0pf_jcore-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup>)</li> <li>Extremely low ASIC <a href="/wiki/Semiconductor_fabrication" class="mw-redirect" title="Semiconductor fabrication">fabrication</a> costs now that the patents are expiring (around <span style="white-space: nowrap">US$0.03</span> for a dual-core J2 core on TSMC's 180 nm process).</li> <li>Patent- and royalty-free (BSD-licensed) implementation</li> <li>Full and vibrant community support</li> <li>Availability of low cost hardware development platform for zero cost FPGA tools</li> <li>CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation</li> <li>Clean, modern design with open source design, generation, simulation and verification environment</li></ul> <div class="mw-heading mw-heading2"><h2 id="Models">Models</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=8" title="Edit section: Models"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="float:right; text-align:right"> <caption>Generation comparison<sup id="cite_ref-FumioArakawa_16-0" class="reference"><a href="#cite_note-FumioArakawa-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th rowspan="2"></th> <th rowspan="2">Clock<br />[MHz]</th> <th colspan="3"><a href="/wiki/Computer_performance" title="Computer performance">Computer performance</a></th> <th rowspan="2">Image </th></tr> <tr> <th><a href="/wiki/Million_instructions_per_second" class="mw-redirect" title="Million instructions per second">MIPS</a></th> <th>MOPS</th> <th><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a> </th></tr> <tr> <th>SH-1 </th> <td>20</td> <td>20</td> <td></td> <td></td> <td><span typeof="mw:File"><a href="/wiki/File:Casio-Loopy-Motherboard-FL_(cropped)_SuperH_HD6437021.jpg" class="mw-file-description"><img alt="SH-1-Prozessor" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/be/Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg/130px-Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg" decoding="async" width="130" height="130" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/be/Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg/195px-Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/be/Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg/260px-Casio-Loopy-Motherboard-FL_%28cropped%29_SuperH_HD6437021.jpg 2x" data-file-width="285" data-file-height="285" /></a></span> </td></tr> <tr> <th>SH-2 </th> <td>28,7</td> <td>78</td> <td>120</td> <td></td> <td><span typeof="mw:File"><a href="/wiki/File:HD6417095_01.jpg" class="mw-file-description"><img alt="SH-2-Prozessor" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HD6417095_01.jpg/250px-HD6417095_01.jpg" decoding="async" width="130" height="120" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HD6417095_01.jpg/330px-HD6417095_01.jpg 2x" data-file-width="560" data-file-height="519" /></a></span> </td></tr> <tr> <th>SH-3 </th> <td>200</td> <td>260</td> <td>400</td> <td></td> <td><span typeof="mw:File"><a href="/wiki/File:HD6417709A_02.jpg" class="mw-file-description"><img alt="SH-3-Prozessor" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a5/HD6417709A_02.jpg/250px-HD6417709A_02.jpg" decoding="async" width="130" height="99" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a5/HD6417709A_02.jpg/330px-HD6417709A_02.jpg 2x" data-file-width="640" data-file-height="488" /></a></span> </td></tr> <tr> <th>SH-4 </th> <td>200</td> <td>480</td> <td></td> <td>1,9</td> <td><span typeof="mw:File"><a href="/wiki/File:SH7091_01.jpg" class="mw-file-description"><img alt="SH-4-Prozessor" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/11/SH7091_01.jpg/130px-SH7091_01.jpg" decoding="async" width="130" height="124" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/11/SH7091_01.jpg/195px-SH7091_01.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/11/SH7091_01.jpg/260px-SH7091_01.jpg 2x" data-file-width="800" data-file-height="761" /></a></span> </td></tr> <tr> <th>SH-5 </th> <td>400</td> <td>700</td> <td>9600</td> <td>2,8</td> <td> </td></tr> <tr> <th><i>SH-6</i> </th> <td></td> <td>>2000</td> <td>>24000</td> <td>>7,0</td> <td> </td></tr></tbody></table> <p>The family of SuperH CPU cores includes: </p> <ul><li>SH-1 – used in microcontrollers for deeply embedded applications (<a href="/wiki/CD-ROM" title="CD-ROM">CD-ROM</a> drives, <a href="/wiki/Major_appliance" title="Major appliance">major appliances</a>, etc.)</li> <li>SH-2 – used in microcontrollers with higher performance requirements, networking applications, and also in video game consoles, like the <a href="/wiki/Sega_Saturn" title="Sega Saturn">Sega Saturn</a> and <a href="/wiki/Sega_32X" class="mw-redirect" title="Sega 32X">Sega 32X</a> add-on. The SH-2 has also found home in many automotive <a href="/wiki/Engine_control_unit" title="Engine control unit">engine control unit</a> applications, including <a href="/wiki/Subaru" title="Subaru">Subaru</a>, <a href="/wiki/Mitsubishi_Motors" title="Mitsubishi Motors">Mitsubishi</a>, and <a href="/wiki/Mazda" title="Mazda">Mazda</a>.</li> <li>SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation</li> <li>SH-DSP – initially developed for the <a href="/wiki/Mobile_phone" title="Mobile phone">mobile phone</a> market, used later in many consumer applications requiring DSP performance for <a href="/wiki/JPEG" title="JPEG">JPEG</a> compression etc.</li> <li>SH-3 – used for mobile and handheld applications such as the <a href="/wiki/Jornada_(PDA)" class="mw-redirect" title="Jornada (PDA)">Jornada</a>, strong in <a href="/wiki/Windows_CE" title="Windows CE">Windows CE</a> applications and market for many years in the car navigation market. The <a href="/wiki/Arcade_system_board#Cave" class="mw-redirect" title="Arcade system board">Cave CV1000</a>, similar to the <a href="/wiki/Sega_NAOMI" class="mw-redirect" title="Sega NAOMI">Sega NAOMI</a> hardware's CPU, also made use of this CPU. The Korg Electribe EMX and ESX music production units also use the SH-3.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></li> <li>SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines</li> <li>SH-4 – used whenever high performance is required such as car multimedia terminals, <a href="/wiki/Video_game_console" title="Video game console">video game consoles</a>, most notably the <a href="/wiki/Dreamcast" title="Dreamcast">Dreamcast</a>, or <a href="/wiki/Set-top_box" title="Set-top box">set-top boxes</a></li> <li>SH-5 – used in high-end 64-bit multimedia applications</li> <li>SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones</li> <li>SH-Mobile – SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI</li></ul> <div class="mw-heading mw-heading3"><h3 id="SH-2">SH-2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=9" title="Edit section: SH-2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Denso-SH2.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/38/Denso-SH2.jpg/170px-Denso-SH2.jpg" decoding="async" width="170" height="136" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/38/Denso-SH2.jpg/255px-Denso-SH2.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/38/Denso-SH2.jpg/340px-Denso-SH2.jpg 2x" data-file-width="1575" data-file-height="1261" /></a><figcaption>Hitachi SH-2 CPU</figcaption></figure> <p>The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware <a href="/wiki/Multiply%E2%80%93accumulate" class="mw-redirect" title="Multiply–accumulate">multiply–accumulate</a> (MAC) block for DSP algorithms and has a five-stage pipeline. </p><p>The SH-2 has a cache on all <a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a>-less devices. </p><p>It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register. </p><p>Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others. </p> <div class="mw-heading mw-heading3"><h3 id="SH-2A">SH-2A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=10" title="Edit section: SH-2A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006. </p><p>New features on the SH-2A core include: </p> <ul><li>Superscalar architecture: execution of 2 instructions simultaneously</li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a></li> <li>Two 5-stage pipelines</li> <li>Mixed 16-bit and 32-bit instructions</li> <li>15 register banks for interrupt response in 6 cycles.</li> <li>Optional FPU</li></ul> <p>The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as <a href="/wiki/Controller-area_network" class="mw-redirect" title="Controller-area network">CAN</a>, <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a>, <a href="/wiki/USB" title="USB">USB</a> and more as well as more application-specific peripherals such as <a href="/wiki/Motor_controller" title="Motor controller">motor control</a> timers, <a href="/wiki/Thin-film_transistor" title="Thin-film transistor">TFT</a> controllers and peripherals dedicated to automotive powertrain applications. </p> <div class="mw-heading mw-heading3"><h3 id="SH-3_2">SH-3</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=11" title="Edit section: SH-3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Hitachi_SH3.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Hitachi_SH3.jpg/170px-Hitachi_SH3.jpg" decoding="async" width="170" height="142" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Hitachi_SH3.jpg/255px-Hitachi_SH3.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Hitachi_SH3.jpg/340px-Hitachi_SH3.jpg 2x" data-file-width="545" data-file-height="455" /></a><figcaption>Hitachi SH-3 CPU (<a href="/wiki/Ball_grid_array" title="Ball grid array">BGA</a> version)</figcaption></figure> <div class="mw-heading mw-heading3"><h3 id="SH-4_2">SH-4</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=12" title="Edit section: SH-4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's <a href="/wiki/Dreamcast" title="Dreamcast">Dreamcast</a> and <a href="/wiki/List_of_Sega_arcade_system_boards#Sega_Naomi" title="List of Sega arcade system boards">NAOMI</a> game systems. It includes a much more powerful floating-point unit<sup class="plainlinks nourlexpansion citation" id="ref_casio"><a href="#endnote_casio">[note]</a></sup> and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size. </p><p>SH-4 features include: </p> <ul><li>FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats</li> <li>4D floating-point <a href="/wiki/Dot-product_operation" class="mw-redirect" title="Dot-product operation">dot-product operation</a> and <a href="/wiki/Matrix%E2%80%93vector_multiplication" class="mw-redirect" title="Matrix–vector multiplication">matrix–vector multiplication</a></li> <li>128-bit floating-point bus allowing 3.2 GB/sec transfer rate from the data cache</li> <li>64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4 GB addressable memory (see <a href="/wiki/Byte_addressing" title="Byte addressing">Byte addressing</a>) with a transfer rate of 800 MB/sec</li> <li>Built-in interrupt, DMA, and power management controllers</li></ul> <p><style data-mw-deduplicate="TemplateStyles:r1041539562">.mw-parser-output .citation{word-wrap:break-word}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}</style><span class="citation wikicite" id="endnote_casio"><b><a href="#ref_casio">^</a></b></span> There is no FPU in the custom SH-4 made for Casio, the SH7305. </p> <div class="mw-heading mw-heading3"><h3 id="SH-5">SH-5</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=13" title="Edit section: SH-5"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SH-5 is a 64-bit RISC CPU.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p><p>Almost no non-simulated SH-5 hardware was ever released,<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> and, unlike the still-live SH-4, support for SH-5 was dropped from <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> and Linux. </p> <div class="mw-heading mw-heading3"><h3 id="SH-6">SH-6</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=14" title="Edit section: SH-6"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SH-6 was an announced but never implemented further development. It was supposed to achieve over 2 GIPS, over 7 GFLOPS and over 24 GOPS.<sup id="cite_ref-FumioArakawa_16-1" class="reference"><a href="#cite_note-FumioArakawa-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=15" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Citations">Citations</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=16" title="Edit section: Citations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230227165625/https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn">"The Story of the Hitachi SH-2 and the Sega Saturn"</a>. <i>www.sega-16.com</i>. Renesas. Archived from <a rel="nofollow" class="external text" href="https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn">the original</a> on 2023-02-27<span class="reference-accessdate">. Retrieved <span class="nowrap">27 February</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.sega-16.com&rft.atitle=The+Story+of+the+Hitachi+SH-2+and+the+Sega+Saturn&rft_id=https%3A%2F%2Fwww.sega-16.com%2Fforum%2Fshowthread.php%3F33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://j-core.org">J-core Open Processor</a></span> </li> <li id="cite_note-FOOTNOTEProgram19961-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-FOOTNOTEProgram19961_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-FOOTNOTEProgram19961_3-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-FOOTNOTEProgram19961_3-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><a href="#CITEREFProgram1996">Program 1996</a>, p. 1.</span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.system16.com/hardware.php?id=799">"CP System III (CPS3) Hardware (Capcom)"</a>. <i>www.system16.com</i>. System 16<span class="reference-accessdate">. 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Archived from <a rel="nofollow" class="external text" href="http://segatech.com/technical/cpu/tech_sh4.html">the original</a> on 5 March 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=360-MIPS+SuperH+RISC+Processor+Enables+Personal+Access+Systems+SH7750+Launches+the+SH-4+Series&rft.date=1997-11&rft_id=http%3A%2F%2Fsegatech.com%2Ftechnical%2Fcpu%2Ftech_sh4.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> <li id="cite_note-sh5-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-sh5_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-sh5_8-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1180485">"STMicro, Hitachi plan new company to develop RISC cores"</a>. <i>EE Times</i>. 3 April 2001. <q>Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. 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Archived from <a rel="nofollow" class="external text" href="http://dealers.korgusa.com/svcfiles/ESX1_Svc_%20man.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 13 July 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Korg+EMX+%2F+ESX+Service+Manual&rft.date=2019-07-25&rft.aulast=Kuwabara&rft.aufirst=M.&rft_id=http%3A%2F%2Fdealers.korgusa.com%2Fsvcfiles%2FESX1_Svc_%2520man.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf">"SH-5 CPU Core, Volume1: Architecture"</a> <span class="cs1-format">(PDF)</span>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090320050543/http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2009-03-20.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=SH-5+CPU+Core%2C+Volume1%3A+Architecture&rft_id=http%3A%2F%2Flars.nocrew.org%2Fcomputers%2Fprocessors%2FSuperH%2Fcpush5v1.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.bsdnewsletter.com/2002/10/News47.html">"Wasabi SH-5 Press Release"</a>. 8 March 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Wasabi+SH-5+Press+Release&rft.date=2016-03-08&rft_id=http%3A%2F%2Fwww.bsdnewsletter.com%2F2002%2F10%2FNews47.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://gcc.gnu.org/gcc-7/changes.html">"GCC 7 Release Series Changes, New Features, and Fixes"</a>. 2 February 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=GCC+7+Release+Series+Changes%2C+New+Features%2C+and+Fixes&rft.date=2018-02-02&rft_id=https%3A%2F%2Fgcc.gnu.org%2Fgcc-7%2Fchanges.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Bibliography">Bibliography</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=17" title="Edit section: Bibliography"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFProgram1996" class="citation book cs1"><a rel="nofollow" class="external text" href="https://antime.kapsi.fi/sega/files/h12p0.pdf"><i>SuperH RISC Engine SH-1/SH-2 Programming Manual</i></a> <span class="cs1-format">(PDF)</span>. Hitachi Americal Ltd. 3 September 1996<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-12-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=SuperH+RISC+Engine+SH-1%2FSH-2+Programming+Manual&rft.pub=Hitachi+Americal+Ltd.&rft.date=1996-09-03&rft_id=https%3A%2F%2Fantime.kapsi.fi%2Fsega%2Ffiles%2Fh12p0.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00147165.pdf"><i>SH-4 CPU Core Architecture</i></a> <span class="cs1-format">(PDF)</span>. STMicroelectronics and Hitachi Ltd. 12 September 2002. ADCS 7182230F<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-12-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=SH-4+CPU+Core+Architecture&rft.pub=STMicroelectronics+and+Hitachi+Ltd.&rft.date=2002-09-12&rft_id=http%3A%2F%2Fwww.st.com%2Fst-web-ui%2Fstatic%2Factive%2Fen%2Fresource%2Ftechnical%2Fdocument%2Fuser_manual%2FCD00147165.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SuperH&action=edit&section=18" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/superh.html">Renesas SuperH</a>, Products, Tools, Manuals, App.Notes, Information</li> <li><a rel="nofollow" class="external text" href="http://j-core.org">J-core Open Processor</a></li> <li><a rel="nofollow" class="external text" href="https://github.com/j-core">J-core</a> on <a href="/wiki/GitHub" title="GitHub">GitHub</a></li> <li><a rel="nofollow" class="external text" href="https://lore.kernel.org/linux-sh/">Linux SuperH development list</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160810170747/http://segatech.com/technical/cpu/index.html">DCTP - Hitachi 200 MHz SH-4</a> at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived August 10, 2016)</li> <li><a rel="nofollow" class="external text" href="http://wiki.debian.org/SH4">in-progress Debian port for SH4</a></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFChen2019" class="citation web cs1">Chen, Raymond (5 August 2019). <a rel="nofollow" class="external text" href="https://devblogs.microsoft.com/oldnewthing/20190805-00/?p=102749">"The SuperH-3, part 1: Introduction"</a>. <i>The Old New Thing</i> (blog)<span class="reference-accessdate">. Retrieved <span class="nowrap">2024-01-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Old+New+Thing&rft.atitle=The+SuperH-3%2C+part+1%3A+Introduction&rft.date=2019-08-05&rft.aulast=Chen&rft.aufirst=Raymond&rft_id=https%3A%2F%2Fdevblogs.microsoft.com%2Foldnewthing%2F20190805-00%2F%3Fp%3D102749&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASuperH" class="Z3988"></span> A 15-part series on programming for the microprocessor.</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl 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.navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Renesas_Electronics31" style="padding:3px"><table class="nowraplinks hlist mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Renesas_Electronics" title="Template:Renesas Electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Renesas_Electronics" title="Template talk:Renesas Electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Renesas_Electronics" title="Special:EditPage/Template:Renesas Electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Renesas_Electronics31" style="font-size:114%;margin:0 4em"><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas Electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RL78" title="RL78">RL78</a></li> <li><a href="/wiki/RX_microcontroller_family" class="mw-redirect" title="RX microcontroller family">RX</a></li> <li><a href="/wiki/V850" title="V850">RH850</a></li> <li><a class="mw-selflink selflink">SuperH</a></li> <li><a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/78K" title="78K">78K</a></li> <li><a href="/wiki/R8C" title="R8C">R8C</a></li> <li><a href="/wiki/R8C_Tiny" title="R8C Tiny">R8C Tiny</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8</a></li> <li><a href="/wiki/Renesas_740" class="mw-redirect" title="Renesas 740">740</a></li> <li><a href="/wiki/IEBus" title="IEBus">IEBus</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="Hitachi530" style="padding:3px"><table class="nowraplinks hlist mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Hitachi" title="Template:Hitachi"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Hitachi" title="Template talk:Hitachi"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Hitachi" title="Special:EditPage/Template:Hitachi"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Hitachi530" style="font-size:114%;margin:0 4em"><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Divisions and<br />subsidiaries</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GlobalLogic" title="GlobalLogic">GlobalLogic</a></li> <li><a href="/wiki/Hitachi_Cable" title="Hitachi Cable">Hitachi Cable</a> <ul><li><span style="font-size:85%;"><a href="/wiki/Hitachi_Cable_Manchester" class="mw-redirect" title="Hitachi Cable Manchester">Hitachi Cable Manchester</a></span></li></ul></li> <li><a href="/wiki/Hitachi_Canadian_Industries" class="mw-redirect" title="Hitachi Canadian Industries">Hitachi Canadian Industries</a></li> <li><a href="/wiki/Hitachi" title="Hitachi">Hitachi Capital</a></li> <li><a href="/wiki/Hitachi_Construction_Machinery" title="Hitachi Construction Machinery">Hitachi Construction Machinery</a> <ul><li><span style="font-size:85%;"><a href="/wiki/Bradken" title="Bradken">Bradken</a></span></li> <li><span style="font-size:85%;"><a href="/wiki/Hitachi_Construction_Machinery_(Europe)" title="Hitachi Construction Machinery (Europe)">Hitachi Construction Machinery (Europe)</a></span></li></ul></li> <li><a href="/wiki/Hitachi_Consulting" title="Hitachi Consulting">Hitachi Consulting</a></li> <li><a href="/wiki/Hitachi_Data_Systems" title="Hitachi Data Systems">Hitachi Data Systems</a> <span style="font-size:85%;">(<a href="/wiki/BlueArc" class="mw-redirect" title="BlueArc">BlueArc</a>)</span></li> <li><a href="/wiki/Hitachi#Hitachi_Electronics" title="Hitachi">Hitachi Electronics</a></li> <li><a href="/wiki/Hitachi_Energy" title="Hitachi Energy">Hitachi Energy</a></li> <li><a href="/wiki/Hitachi" title="Hitachi">Hitachi Medical Systems</a></li> <li><a href="/wiki/Hitachi#Hitachi_Rail" title="Hitachi">Hitachi Rail</a> <ul><li><span style="font-size:85%;"><a href="/wiki/Hitachi_Rail_STS" title="Hitachi Rail STS">Hitachi Rail STS</a></span></li> <li><span style="font-size:85%;"><a href="/wiki/Hitachi_Rail_Italy" title="Hitachi Rail Italy">Hitachi Rail Italy</a></span></li></ul></li> <li><a href="/wiki/Horizon_Nuclear_Power" title="Horizon Nuclear Power">Horizon Nuclear Power</a></li> <li><a href="/wiki/JECS" title="JECS">JECS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Former</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Clarion_(company)" title="Clarion (company)">Clarion</a></li> <li><a href="/wiki/Euclid_Trucks" title="Euclid Trucks">Euclid Trucks</a><sup>1</sup></li> <li><a href="/wiki/Fabrik_Inc." title="Fabrik Inc.">Fabrik</a><sup>1</sup></li> <li><a href="/wiki/HGST" title="HGST">Hitachi Global Storage Technologies</a><sup>2</sup></li> <li><a href="/wiki/Maxell" title="Maxell">Maxell</a></li></ul> </div></td></tr></tbody></table><div></div></td><td class="noviewer navbox-image" rowspan="6" style="width:1px;padding:0 0 0 2px"><div><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Hitachi_logo.svg/150px-Hitachi_logo.svg.png" decoding="async" width="150" height="24" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Hitachi_logo.svg/225px-Hitachi_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Hitachi_logo.svg/300px-Hitachi_logo.svg.png 2x" data-file-width="850" data-file-height="136" /></span></span></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Joint ventures and<br />shareholdings</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GE_Hitachi_Nuclear_Energy" title="GE Hitachi Nuclear Energy">GE Hitachi Nuclear Energy</a> <span style="font-size:85%;">(40%)</span></li> <li>Hitachi Astemo <span style="font-size:85%;">(66.6%)</span> <ul><li><a href="/wiki/Keihin_Corporation" title="Keihin Corporation">Keihin</a></li> <li><a href="/wiki/Nissin_Kogyo" title="Nissin Kogyo">Nissin</a></li> <li><a href="/wiki/Showa_Corporation" title="Showa Corporation">Showa</a></li> <li><a href="/wiki/Tokico" title="Tokico">Tokico</a></li></ul></li> <li><a href="/wiki/Hitachi-LG_Data_Storage" title="Hitachi-LG Data Storage">Hitachi-LG Data Storage</a></li> <li><a href="/wiki/Johnson_Controls_Hitachi" title="Johnson Controls Hitachi">Johnson Controls-Hitachi Air Conditioning</a> <span style="font-size:85%;">(40%)</span></li> <li><a href="/wiki/Tata_Hitachi_Construction_Machinery" title="Tata Hitachi Construction Machinery">Tata Hitachi Construction Machinery</a> <span style="font-size:85%;">(60%)</span></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Former</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Agility_Trains" title="Agility Trains">Agility Trains</a></li> <li><a href="/wiki/Alaxala_Networks" title="Alaxala Networks">Alaxala Networks</a></li> <li><a href="/wiki/Japan_Display" title="Japan Display">Japan Display</a></li> <li><a href="/wiki/NEC_Mobile_Communications" title="NEC Mobile Communications">Casio Hitachi Mobile Communications</a></li> <li><a href="/wiki/Nippon_Columbia" title="Nippon Columbia">Nippon Columbia</a></li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas Electronics</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Products, services<br />and standards</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Alternate_lighting_of_surfaces" title="Alternate lighting of surfaces">ALiS</a></li> <li><a href="/wiki/EMIEW" title="EMIEW">EMIEW</a></li> <li><a href="/wiki/Hitachi_Adaptable_Modular_Storage_2000" title="Hitachi Adaptable Modular Storage 2000">Adaptable Modular Storage 2000</a></li> <li><a href="/wiki/Hitachi_Starboard" title="Hitachi Starboard">Hitachi Starboard</a></li> <li><a href="/wiki/Category:Hitachi_locomotives" title="Category:Hitachi locomotives">Locomotives</a></li> <li><a href="/wiki/Hitachi_Magic_Wand" title="Hitachi Magic Wand">Hitachi Magic Wand</a></li> <li><a href="/wiki/Category:Hitachi_multiple_units" title="Category:Hitachi multiple units">Multiple units</a></li> <li><a href="/wiki/Hitachi_917" title="Hitachi 917">Hitachi 917</a></li> <li><a href="/wiki/Hitachi_SR8000" title="Hitachi SR8000">Hitachi SR8000</a></li> <li><a href="/wiki/Hitachi_TrueCopy" class="mw-redirect" title="Hitachi TrueCopy">Hitachi TrueCopy</a></li> <li><a href="/wiki/LS-R" title="LS-R">LS-R</a></li> <li><a href="/wiki/M8_(cipher)" title="M8 (cipher)">M8</a></li> <li><a href="/wiki/Stacked_Volumetric_Optical_Disk" class="mw-redirect" title="Stacked Volumetric Optical Disk">Stacked Volumetric Optical Disk</a></li> <li><a class="mw-selflink selflink">SuperH</a></li> <li><a href="/wiki/Universal_Storage_Platform" title="Universal Storage Platform">Universal Storage Platform</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Defunct</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/D-VHS" title="D-VHS">D-VHS</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8 Family</a></li> <li><a href="/wiki/HD64180" class="mw-redirect" title="HD64180">HD64180</a></li> <li><a href="/wiki/HITAC" title="HITAC">HITAC</a></li> <li><a href="/wiki/HITAC_S-810" title="HITAC S-810">HITAC S-810</a></li> <li><a href="/wiki/Hitachi_6309" title="Hitachi 6309">Hitachi 6309</a></li> <li><a href="/wiki/Deskstar" title="Deskstar">Deskstar</a></li> <li><a href="/wiki/Hitachi_Flora_Prius" title="Hitachi Flora Prius">Hitachi Flora Prius</a></li> <li><a href="/wiki/Hitachi_SH-G1000" title="Hitachi SH-G1000">Hitachi G1000</a></li> <li><a href="/wiki/Hitachi_Hatsukaze" title="Hitachi Hatsukaze">Hitachi Hatsukaze</a></li> <li><a href="/wiki/Hitachi_SR2201" title="Hitachi SR2201">Hitachi SR2201</a></li> <li><a href="/wiki/Hitachi_T.2" title="Hitachi T.2">Hitachi T.2</a></li> <li><a href="/wiki/Hitachi_TR.1" title="Hitachi TR.1">Hitachi TR.1</a></li> <li><a href="/wiki/M6_(cipher)" title="M6 (cipher)">M6</a></li> <li><a href="/wiki/Microdrive" title="Microdrive">Microdrive</a></li> <li><a href="/wiki/Travelstar" title="Travelstar">Travelstar</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">People</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Namihei_Odaira" title="Namihei Odaira">Namihei Odaira</a></li> <li><a href="/wiki/Kenichi_Ohmae" title="Kenichi Ohmae">Kenichi Ohmae</a></li> <li><a href="/wiki/Hiroaki_Nakanishi" title="Hiroaki Nakanishi">Hiroaki Nakanishi</a></li> <li><a href="/wiki/Takashi_Kawamura_(businessman)" title="Takashi Kawamura (businessman)">Takashi Kawamura</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Places</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hitachi_Kashiwa_Soccer_Stadium" class="mw-redirect" title="Hitachi Kashiwa Soccer Stadium">Hitachi Kashiwa Soccer Stadium</a></li> <li><a href="/wiki/Hitachi,_Ibaraki" title="Hitachi, Ibaraki">Hitachi, Ibaraki</a></li> <li><a href="/wiki/Hitachi_Tower" class="mw-redirect" title="Hitachi Tower">Hitachi Tower</a></li> <li><a href="/wiki/Ts%C5%ABtenkaku" title="Tsūtenkaku">Tsūtenkaku</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DKB_Group" title="DKB Group">DKB Group</a></li> <li><a href="/wiki/HDMI_Licensing" class="mw-redirect" title="HDMI Licensing">HDMI Licensing</a></li> <li><a href="/wiki/Hitachi_3Tours_Championship" title="Hitachi 3Tours Championship">Hitachi 3Tours Championship</a></li> <li><a href="/wiki/Hitachi_Data_Systems_History" class="mw-redirect" title="Hitachi Data Systems History">Hitachi Data Systems History</a></li> <li><a href="/wiki/The_Hitachi_Foundation" class="mw-redirect" title="The Hitachi Foundation">The Hitachi Foundation</a></li> <li><a href="/wiki/Hitachi_Sundiva" title="Hitachi Sundiva">Hitachi Sundiva</a></li> <li><a href="/wiki/Hitachi_SunRockers" class="mw-redirect" title="Hitachi SunRockers">Hitachi SunRockers</a></li> <li><a href="/wiki/Hitachi_Rivale" class="mw-redirect" title="Hitachi Rivale">Hitachi Rivale</a></li> <li><a href="/wiki/Kashiwa_Reysol" title="Kashiwa Reysol">Kashiwa Reysol</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="3"><div> <ul><li><span style="font-size:85%;"><sup>1</sup><i>Now integrated into other Hitachi divisions or business groupings</i> <sup>2</sup><i>Sold to <a href="/wiki/Western_Digital" title="Western Digital">Western Digital</a></i></span></li></ul> <ul><li><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" data-file-height="185" /></span></span> <b><a href="/wiki/Category:Hitachi" title="Category:Hitachi">Category</a></b></li> <li><span class="noviewer" typeof="mw:File"><span title="Commons page"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/20px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/40px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></span></span> <b><a href="https://commons.wikimedia.org/wiki/Category:Hitachi" class="extiw" title="commons:Category:Hitachi">Commons</a></b></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="Reduced_instruction_set_computer_(RISC)_architectures109" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:RISC_architectures" title="Template:RISC architectures"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:RISC_architectures" title="Template talk:RISC architectures"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:RISC_architectures" title="Special:EditPage/Template:RISC architectures"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Reduced_instruction_set_computer_(RISC)_architectures109" style="font-size:114%;margin:0 4em"><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_801" title="IBM 801">IBM 801</a></li> <li><a href="/wiki/Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">In active development</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> <a href="/wiki/Blackfin" title="Blackfin">Blackfin</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/ESi-RISC" title="ESi-RISC">eSi-RISC</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="/wiki/M32R" title="M32R">M32R</a>, <a class="mw-selflink selflink">SuperH</a>, <a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/Sunway_(processor)" title="Sunway (processor)">Sunway</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> <a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a></li> <li><a href="/wiki/AMD_Am29000" title="AMD Am29000">AMD Am29000</a></li> <li><a href="/wiki/Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li> <li><a href="/wiki/Atmel" title="Atmel">Atmel</a> <a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16</a></li> <li><a href="/wiki/AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li> <li><a href="/wiki/DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li> <li><a href="/wiki/Intel_i860" title="Intel i860">Intel i860</a>, <a href="/wiki/Intel_i960" title="Intel i960">i960</a></li> <li><a href="/wiki/Imagination_META" title="Imagination META">META</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li><a href="/wiki/Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="/wiki/M%C2%B7CORE" title="M·CORE">M·CORE</a></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a></li> <li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <i>(active use in space exploration as <a href="/wiki/RAD750" title="RAD750">RAD750</a>)</i>, <a href="/wiki/IBM_ROMP" title="IBM ROMP">ROMP</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies439" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a class="mw-selflink selflink">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="Instruction_set_extensions480" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Multimedia_extensions" title="Template:Multimedia extensions"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Multimedia_extensions" title="Template talk:Multimedia extensions"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Multimedia_extensions" title="Special:EditPage/Template:Multimedia extensions"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Instruction_set_extensions480" style="font-size:114%;margin:0 4em"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Instruction set</a> <a href="/wiki/Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <ul><li><a href="/wiki/DEC_Alpha#Motion_Video_Instructions_(MVI)" title="DEC Alpha">MVI</a></li></ul></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> <ul><li><a href="/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)" title="ARM architecture family">NEON</a></li> <li><a href="/wiki/AArch64#Scalable_Vector_Extension_(SVE)" title="AArch64">SVE</a></li></ul></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <ul><li><a href="/wiki/MDMX" title="MDMX">MDMX</a></li> <li><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></li> <li><a href="/wiki/Media_Extension_Unit" class="mw-redirect" title="Media Extension Unit">MXU</a></li> <li><a href="/wiki/MIPS_architecture#MIPS_SIMD_architecture" title="MIPS architecture">MIPS SIMD</a></li></ul></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> <ul><li><a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">MAX</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/AltiVec" title="AltiVec">VMX</a></li></ul></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a> <ul><li><a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">VIS</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/X86" title="X86">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (1996)</li> <li><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> (1998)</li> <li><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> (1999)</li> <li><a href="/wiki/SSE2" title="SSE2">SSE2</a> (2001)</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a> (2004)</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (2006)</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a> (2006)</li> <li><a href="/wiki/SSE5" title="SSE5">SSE5</a> <s>(2007)</s></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> (2008)</li> <li><a href="/wiki/F16C" title="F16C">F16C</a> (2009)</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a> (2009)</li> <li><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> (FMA4: 2011, FMA3: 2012)</li> <li><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> (2013)</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (2015)</li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> (2022)</li> <li><a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bit_manipulation" title="Bit manipulation">Bit manipulation</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a> (2014)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS16e ASE</a></li> <li><a href="/wiki/RISC-V#Compressed_subset" title="RISC-V">RVC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li> <li><a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li> <li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> (2012)</li> <li><a href="/wiki/Intel_SHA_extensions" class="mw-redirect" title="Intel SHA extensions">SHA</a> (2013)</li> <li><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> (2015)</li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> (2015)</li> <li><a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> (2021)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> (2013)</li> <li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/X86_virtualization#Intel_virtualization_(VT-x)" title="X86 virtualization">VT-x</a> (2005)</li> <li><a href="/wiki/X86_virtualization#AMD_virtualization_(AMD-V)" title="X86 virtualization">AMD-V</a> (2006)</li> <li><a href="/wiki/X86_virtualization#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" title="X86 virtualization">VT-d</a> (AMD-Vi)</li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck through</s>.</div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=0" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=SuperH&oldid=1271518179#SH-4">https://en.wikipedia.org/w/index.php?title=SuperH&oldid=1271518179#SH-4</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:SuperH_architecture" title="Category:SuperH architecture">SuperH architecture</a></li><li><a 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