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window.loswp.shouldShowBulkDownload = true; window.loswp.showSignupCaptcha = false window.loswp.willEdgeCache = false; window.loswp.work = {"work":{"id":75609696,"created_at":"2022-04-06T02:27:18.937-07:00","from_world_paper_id":200780512,"updated_at":"2025-01-24T17:38:14.211-08:00","_data":{"grobid_abstract":"Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.","publication_date":"2003,,","publication_name":"Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign \u0026 system synthesis - CODES+ISSS '03","grobid_abstract_attachment_id":"83310244"},"document_type":"paper","pre_hit_view_count_baseline":null,"quality":"high","language":"en","title":"Seas","broadcastable":false,"draft":null,"has_indexable_attachment":true,"indexable":true,"seo_quality":null}}["work"]; window.loswp.workCoauthors = [17709009]; window.loswp.locale = "en"; window.loswp.countryCode = "SG"; window.loswp.cwvAbTestBucket = ""; window.loswp.designVariant = "ds_vanilla"; window.loswp.fullPageMobileSutdModalVariant = "control"; window.loswp.useOptimizedScribd4genScript = false; window.loginModal = {}; window.loginModal.appleClientId = 'edu.academia.applesignon'; window.userInChina = "false";</script><script defer="" src="https://accounts.google.com/gsi/client"></script><div class="ds-loswp-container"><div class="ds-work-card--grid-container"><div class="ds-work-card--container js-loswp-work-card"><div class="ds-work-card--cover"><div class="ds-work-cover--wrapper"><div class="ds-work-cover--container"><button class="ds-work-cover--clickable js-swp-download-button" data-signup-modal="{"location":"swp-splash-paper-cover","attachmentId":83310244,"attachmentType":"pdf"}"><img alt="First page of “Seas”" class="ds-work-cover--cover-thumbnail" src="https://0.academia-photos.com/attachment_thumbnails/83310244/mini_magick20220406-5811-1jlqiqd.png?1649237357" /><img alt="PDF Icon" class="ds-work-cover--file-icon" src="//a.academia-assets.com/images/single_work_splash/adobe_icon.svg" /><div class="ds-work-cover--hover-container"><span class="material-symbols-outlined" style="font-size: 20px" translate="no">download</span><p>Download Free PDF</p></div><div class="ds-work-cover--ribbon-container">Download Free PDF</div><div class="ds-work-cover--ribbon-triangle"></div></button></div></div></div><div class="ds-work-card--work-information"><h1 class="ds-work-card--work-title">Seas</h1><div class="ds-work-card--work-authors ds-work-card--detail"><a class="ds-work-card--author js-wsj-grid-card-author ds2-5-body-md ds2-5-body-link" data-author-id="17709009" href="https://iitkgp.academia.edu/SubhrajitBhattacharya"><img alt="Profile image of Subhrajit Bhattacharya" class="ds-work-card--author-avatar" src="//a.academia-assets.com/images/s65_no_pic.png" />Subhrajit Bhattacharya</a></div><div class="ds-work-card--detail"><p class="ds-work-card--detail ds2-5-body-sm">2003, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis - CODES+ISSS '03</p><div class="ds-work-card--work-metadata"><div class="ds-work-card--work-metadata__stat"><span class="material-symbols-outlined" style="font-size: 20px" translate="no">visibility</span><p class="ds2-5-body-sm" id="work-metadata-view-count">…</p></div><div class="ds-work-card--work-metadata__stat"><span class="material-symbols-outlined" style="font-size: 20px" translate="no">description</span><p class="ds2-5-body-sm">6 pages</p></div><div class="ds-work-card--work-metadata__stat"><span class="material-symbols-outlined" style="font-size: 20px" translate="no">link</span><p class="ds2-5-body-sm">1 file</p></div></div><script>(async () => { const workId = 75609696; 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Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.</p></div></div><div class="ds-top-related-works--grid-container"><div class="ds-related-content--container ds-top-related-works--container"><h2 class="ds-related-content--heading">Related papers</h2><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="0" data-entity-id="19475148" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/19475148/Early_analysis_tools_for_system_on_a_chip_design">Early analysis tools for system-on-a-chip design</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="39749569" href="https://independent.academia.edu/BrandDaniel">Daniel Brand</a></div><p class="ds-related-work--metadata ds2-5-body-xs">IBM Journal of Research and Development, 2000</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Early analysis tools for system-on-a-chip design","attachmentId":40640905,"attachmentType":"pdf","work_url":"https://www.academia.edu/19475148/Early_analysis_tools_for_system_on_a_chip_design","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/19475148/Early_analysis_tools_for_system_on_a_chip_design"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="1" data-entity-id="98759469" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/98759469/FARSI_An_Early_stage_Design_Space_Exploration_Framework_to_Tame_the_Domain_specific_System_on_chip_Complexity">FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="55188855" href="https://independent.academia.edu/VivekVenkatesan1">Vivek Venkatesan</a></div><p class="ds-related-work--metadata ds2-5-body-xs">ACM Transactions on Embedded Computing Systems</p><p class="ds-related-work--abstract ds2-5-body-sm">Domain-specific SoCs (DSSoCs) are an attractive solution for domains with extremely stringent power, performance, and area constraints. However, DSSoCs suffer from two fundamental complexities. On the one hand, their many specialized hardware blocks result in complex systems and thus high development effort. On the other hand, their many system knobs expand the complexity of design space, making the search for the optimal design difficult. Thus to reach prevalence, taming such complexities is necessary. To address these challenges, in this work, we identify the necessary features of an early-stage design space exploration framework that targets the complex design space of DSSoCs and provide an instance of one such framework that we refer to as FARSI. FARSI provides an agile system-level simulator with speed up and accuracy of 8,400× and 98.5% compared to Synopsys Platform Architect. FARSI also provides an efficient exploration heuristic and achieves up to 62× and 35× improvement in ...</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity","attachmentId":100023741,"attachmentType":"pdf","work_url":"https://www.academia.edu/98759469/FARSI_An_Early_stage_Design_Space_Exploration_Framework_to_Tame_the_Domain_specific_System_on_chip_Complexity","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/98759469/FARSI_An_Early_stage_Design_Space_Exploration_Framework_to_Tame_the_Domain_specific_System_on_chip_Complexity"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="2" data-entity-id="104848640" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/104848640/High_level_analysis_of_multiprocessor_system_on_chip">High level analysis of multiprocessor system on chip</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="264263575" href="https://independent.academia.edu/MohamedAbid45">Mohamed Abid</a></div><p class="ds-related-work--abstract ds2-5-body-sm">Traditionally codesign flow aims to help the designers to take decisions about the system architecture, however due to the complexity of both system architectures and applications it is now necessary to perform before any codesign flow a first application analysis step in order to highlight the application's specificity. An efficient way to analyze the application is to define accurate metrics that exhibit the application's specificity impacting the system performance. In this paper, we propose several metrics that allow an efficient analysis of a system right after the specification of the application (tasks graph) before any design flow step. These metrics enable to measure some characteristics of the application as communication data size and data sharing between tasks... As they are defined before any design flow step they do not measure directly the system performance or the costs but they provide information that leads to optimize these costs. Several experimental results performed on an UMTS application demonstrate the efficiency of these metrics to exhibit the main characteristics of an application. The results also show the ability of the proposed metrics to correctly measure the applications specificity. Finally, the results show the interest of the metrics to be used in a clustering approach or other codesign flow.</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"High level analysis of multiprocessor system on chip","attachmentId":104467336,"attachmentType":"pdf","work_url":"https://www.academia.edu/104848640/High_level_analysis_of_multiprocessor_system_on_chip","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/104848640/High_level_analysis_of_multiprocessor_system_on_chip"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="3" data-entity-id="81176935" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/81176935/Specification_Modeling_and_Design_Tools_for_System_on_Chip">Specification, Modeling and Design Tools for System-on-Chip</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="202499" href="https://ucsd.academia.edu/RajeshGupta">Rajesh Gupta</a></div><p class="ds-related-work--abstract ds2-5-body-sm">Ubiquitous embedded systems are revolutionizing our daily lives. Whole systems on a chip deliver unprecedented computation power at ever decreasing costs. However, their complexity makes their design with traditional RTL-based flows extremely challenging. Complexity in such systems arises not only from the diversity of the technologies, from RF front-ends to baseband DSP software, that must be integrated on-chip, but also from the fact that such systems must be increasingly built from parts that have been designed separately and using different tools and flows. High abstraction levels and component reuse are essential. Often such systems are highly networked and rely on sophisticated communication mechanisms. Architectural design and performance analysis of such networked system-chips is a crucial part of the embedded system design process.Two basic methods for tackling the growing complexity of system-on-chip design are emerging. Formal specification and design methods, and platfor...</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Specification, Modeling and Design Tools for System-on-Chip","attachmentId":87312994,"attachmentType":"pdf","work_url":"https://www.academia.edu/81176935/Specification_Modeling_and_Design_Tools_for_System_on_Chip","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/81176935/Specification_Modeling_and_Design_Tools_for_System_on_Chip"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="4" data-entity-id="112901472" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/112901472/SoCCom_Automated_Synthesis_of_System_on_Chip_Architectures">SoCCom: Automated Synthesis of System-on-Chip Architectures</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="192503560" href="https://independent.academia.edu/CkKSHITIJRaj">Ck KSHITIJ Raj</a></div><p class="ds-related-work--metadata ds2-5-body-xs">IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022</p><p class="ds-related-work--abstract ds2-5-body-sm">We present CAD framework and EDA tool, SOCCOM, for automated synthesis of optimized SoC architectures. We delineate a disciplined and streamlined methodology to enable automated IP integration and design optimization. SOCCOM supports generation of a wide variety of optimized SoCs by: 1) automating the entire process of intellectual property (IP) standardization and integration; 2) allowing configurable assembly of complex, scalable systems with application-specific subsystems; and 3) enabling optimization and evaluation of generated designs based on area and power constraints. Applications of SOCCOM include development of heterogeneous, domainspecific SoCs, rapid register-transfer level (RTL) prototyping of wide-varieties of SoC benchmarks, and many others.</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"SoCCom: Automated Synthesis of System-on-Chip Architectures","attachmentId":109999344,"attachmentType":"pdf","work_url":"https://www.academia.edu/112901472/SoCCom_Automated_Synthesis_of_System_on_Chip_Architectures","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/112901472/SoCCom_Automated_Synthesis_of_System_on_Chip_Architectures"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="5" data-entity-id="13239837" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/13239837/Efficient_design_space_exploration_for_application_specific_systems_on_a_chip">Efficient design space exploration for application specific systems-on-a-chip</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="32496183" href="https://shu.academia.edu/adinuovo">Alessandro Di Nuovo</a><span>, </span><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="32568856" href="https://unict.academia.edu/DPatti">D. Patti</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Journal of Systems Architecture, 2007</p><p class="ds-related-work--abstract ds2-5-body-sm">A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Efficient design space exploration for application specific systems-on-a-chip","attachmentId":45560156,"attachmentType":"pdf","work_url":"https://www.academia.edu/13239837/Efficient_design_space_exploration_for_application_specific_systems_on_a_chip","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/13239837/Efficient_design_space_exploration_for_application_specific_systems_on_a_chip"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="6" data-entity-id="72159487" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/72159487/SoCRocket_A_virtual_platform_for_SoC_design">SoCRocket: A virtual platform for SoC design</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="258168" href="https://tu-braunschweig.academia.edu/MladenBerekovic">Mladen Berekovic</a></div><p class="ds-related-work--metadata ds2-5-body-xs">2013</p><p class="ds-related-work--abstract ds2-5-body-sm">Both in the commercial and in the aerospace domain, the continuous increase of transistor density on a single die is leading towards the production of more and more complex systems on a single chip, with an increasing number of components. This brought to the introduction of the System-On-Chip (SoC) architecture, that integrates on a single circuit all the elements of a full system. This strive for efficient utilization of the available silicon has triggered several paradigm shifts in system design. Similarly to what happened in the early 1990s, when VHDL and Verilog took over from schematic design, today SystemC and Transaction Level Modeling [1] are about to further raise the design abstraction level. Such descriptions have to be accurate enough to describe the entire system throughout the phases of its development, and has to provide enough flexibility to be refined iteratively up to the point where the actual device can be produced using current process technology. Besides requi...</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"SoCRocket: A virtual platform for SoC design","attachmentId":81200183,"attachmentType":"pdf","work_url":"https://www.academia.edu/72159487/SoCRocket_A_virtual_platform_for_SoC_design","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/72159487/SoCRocket_A_virtual_platform_for_SoC_design"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="7" data-entity-id="50675237" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/50675237/V_SAT_A_visual_specification_and_analysis_tool_for_system_on_chip_exploration">V-SAT: A visual specification and analysis tool for system-on-chip exploration</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="86587124" href="https://uci.academia.edu/ANicolau">Alex Nicolau</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Journal of Systems Architecture, 2001</p><p class="ds-related-work--abstract ds2-5-body-sm">We describe V-SAT, a tool for performing design space exploration of system-on-chip (SOC) architectures. The key components of V-SAT include EXPRESSION, a language for speci®cation of the architecture, SIMPRESS, a simulator generator for analysis/evaluation of the architecture, and the V-SAT GUI front-end for easy speci®cation and detailed analysis. We give a brief overview of the components (EXPRESSION, SIMPRESS and GUI) and, using an example DLX architecture, demonstrate V-SAT's usefulness in exploration for an embedded SOC codesign¯ow by specifying and evaluating several modi®cations to the pipeline structure of the processor. We believe that V-SAT provides a powerful environment, both for early design space exploration, as well as for the detailed design of SOC architectures.</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"V-SAT: A visual specification and analysis tool for system-on-chip exploration","attachmentId":68565942,"attachmentType":"pdf","work_url":"https://www.academia.edu/50675237/V_SAT_A_visual_specification_and_analysis_tool_for_system_on_chip_exploration","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/50675237/V_SAT_A_visual_specification_and_analysis_tool_for_system_on_chip_exploration"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="8" data-entity-id="269263" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/269263/Casse_a_System_Level_Modeling_and_Design_Space_Exploration_Tool_for_Multiprocessor_Systems_On_chip">Casse: a System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-On-chip</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="220155" href="https://ulpgc.academia.edu/GustavoCallico">Gustavo Callico</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Euromicro Symposium on Digital …</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Casse: a System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-On-chip","attachmentId":51475922,"attachmentType":"pdf","work_url":"https://www.academia.edu/269263/Casse_a_System_Level_Modeling_and_Design_Space_Exploration_Tool_for_Multiprocessor_Systems_On_chip","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/269263/Casse_a_System_Level_Modeling_and_Design_Space_Exploration_Tool_for_Multiprocessor_Systems_On_chip"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-wsj-grid-card" data-collection-position="9" data-entity-id="104848639" data-sort-order="default"><a class="ds-related-work--title js-wsj-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/104848639/Metrics_for_high_level_analysis_of_multiprocessor_system_on_chip">Metrics for high level analysis of multiprocessor system on chip</a><div class="ds-related-work--metadata"><a class="js-wsj-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="264263575" href="https://independent.academia.edu/MohamedAbid45">Mohamed Abid</a></div><p class="ds-related-work--abstract ds2-5-body-sm">Traditionally codesign flow aims to help the designers to take decisions about the system architecture, however due to the complexity of both system architectures and applications it is now necessary to perform before any codesign flow a first application analysis step in order to highlight the application's specificity. An efficient way to analyze the application is to define accurate metrics that exhibit the application's specificity impacting the system performance. In this paper, we propose several metrics that allow an efficient analysis of a system right after the specification of the application (tasks graph) before any design flow step. These metrics enable to measure some characteristics of the application as communication data size and data sharing between tasks... As they are defined before any design flow step they do not measure directly the system performance or the costs but they provide information that leads to optimize these costs. Several experimental results performed on an UMTS application demonstrate the efficiency of these metrics to exhibit the main characteristics of an application. The results also show the ability of the proposed metrics to correctly measure the applications specificity. Finally, the results show the interest of the metrics to be used in a clustering approach or other codesign flow.</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Metrics for high level analysis of multiprocessor system on chip","attachmentId":104467335,"attachmentType":"pdf","work_url":"https://www.academia.edu/104848639/Metrics_for_high_level_analysis_of_multiprocessor_system_on_chip","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-wsj-grid-card-view-pdf" href="https://www.academia.edu/104848639/Metrics_for_high_level_analysis_of_multiprocessor_system_on_chip"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div></div></div><div class="ds-sticky-ctas--wrapper js-loswp-sticky-ctas hidden"><div class="ds-sticky-ctas--grid-container"><div class="ds-sticky-ctas--container"><button class="ds2-5-button js-swp-download-button" data-signup-modal="{"location":"continue-reading-button--sticky-ctas","attachmentId":83310244,"attachmentType":"pdf","workUrl":null}">See full PDF</button><button class="ds2-5-button ds2-5-button--secondary js-swp-download-button" data-signup-modal="{"location":"download-pdf-button--sticky-ctas","attachmentId":83310244,"attachmentType":"pdf","workUrl":null}"><span class="material-symbols-outlined" style="font-size: 20px" translate="no">download</span>Download PDF</button></div></div></div><div class="ds-below-fold--grid-container"><div class="ds-work--container js-loswp-embedded-document"><div class="attachment_preview" data-attachment="Attachment_83310244" style="display: none"><div class="js-scribd-document-container"><div class="scribd--document-loading js-scribd-document-loader" style="display: block;"><img alt="Loading..." src="//a.academia-assets.com/images/loaders/paper-load.gif" /><p>Loading Preview</p></div></div><div style="text-align: center;"><div class="scribd--no-preview-alert js-preview-unavailable"><p>Sorry, preview is currently unavailable. You can download the paper by clicking the button above.</p></div></div></div></div><div class="ds-sidebar--container js-work-sidebar"><div class="ds-related-content--container"><h2 class="ds-related-content--heading">Related papers</h2><div class="ds-related-work--container js-related-work-sidebar-card" data-collection-position="0" data-entity-id="52157456" data-sort-order="default"><a class="ds-related-work--title js-related-work-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/52157456/STATS_A_framework_for_microprocessor_and_system_level_design_space_exploration">STATS: A framework for microprocessor and system-level design space exploration</a><div class="ds-related-work--metadata"><a class="js-related-work-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="34214211" href="https://umass.academia.edu/IKoren">Israel Koren</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Journal of Systems Architecture, 1999</p><div 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Design","attachmentId":79608602,"attachmentType":"pdf","work_url":"https://www.academia.edu/69558116/Microarchitecture_Level_SoC_Design","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-related-work-grid-card-view-pdf" href="https://www.academia.edu/69558116/Microarchitecture_Level_SoC_Design"><span class="ds2-5-text-link__content">View PDF</span><span class="material-symbols-outlined" style="font-size: 18px" translate="no">chevron_right</span></a></div></div><div class="ds-related-work--container js-related-work-sidebar-card" data-collection-position="2" data-entity-id="53005088" data-sort-order="default"><a class="ds-related-work--title js-related-work-grid-card-title ds2-5-body-md ds2-5-body-link" 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href="https://independent.academia.edu/GerdAscheid">Gerd Ascheid</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Proceedings of the Design Automation & Test in Europe Conference, 2006</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"A SW performance estimation framework for early system-level-design using fine-grained instrumentation","attachmentId":39806969,"attachmentType":"pdf","work_url":"https://www.academia.edu/17971852/A_SW_performance_estimation_framework_for_early_system_level_design_using_fine_grained_instrumentation","alternativeTracking":true}"><span class="material-symbols-outlined" style="font-size: 18px" translate="no">download</span><span class="ds2-5-text-link__content">Download free PDF</span></button><a class="ds2-5-text-link ds2-5-text-link--inline js-related-work-grid-card-view-pdf" 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data-collection-position="12" data-entity-id="91291977" data-sort-order="default"><a class="ds-related-work--title js-related-work-grid-card-title ds2-5-body-md ds2-5-body-link" href="https://www.academia.edu/91291977/Validation_in_a_component_based_design_flow_for_multicore_SoCs">Validation in a component-based design flow for multicore SoCs</a><div class="ds-related-work--metadata"><a class="js-related-work-grid-card-author ds2-5-body-sm ds2-5-body-link" data-author-id="100194997" href="https://sesame.academia.edu/AimenBouchhima">Aimen Bouchhima</a></div><p class="ds-related-work--metadata ds2-5-body-xs">Proceedings of the 15th international symposium on System Synthesis - ISSS '02, 2002</p><div class="ds-related-work--ctas"><button class="ds2-5-text-link ds2-5-text-link--inline js-swp-download-button" data-signup-modal="{"location":"wsj-grid-card-download-pdf-modal","work_title":"Validation in a component-based design flow for multicore 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