High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure

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Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure</title> <meta name="description" content="High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure"> <meta name="keywords" content="discrete wavelet transform, VLSI architecture, QMF lattice filter, pipelining."> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <meta name="citation_title" content="High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure"> <meta name="citation_author" content="Juyoung Kim"> <meta name="citation_author" content="Taegeun Park"> <meta name="citation_publication_date" content="2009/06/21"> <meta name="citation_journal_title" content="International Journal of Electronics and Communication Engineering"> <meta name="citation_volume" content="3"> <meta name="citation_issue" content="6"> <meta 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href="https://publications.waset.org/search?q=Juyoung%20Kim">Juyoung Kim</a>, <a href="https://publications.waset.org/search?q=Taegeun%20Park"> Taegeun Park</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.</p> <iframe src="https://publications.waset.org/7661.pdf" style="width:100%; height:400px;" frameborder="0"></iframe> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=discrete%20wavelet%20transform" title="discrete wavelet transform">discrete wavelet transform</a>, <a href="https://publications.waset.org/search?q=VLSI%20architecture" title=" VLSI architecture"> VLSI architecture</a>, <a href="https://publications.waset.org/search?q=QMF%20lattice%20filter" title=" QMF lattice filter"> QMF lattice filter</a>, <a href="https://publications.waset.org/search?q=pipelining." title=" pipelining."> pipelining.</a> </p> <p class="card-text"><strong>Digital Object Identifier (DOI):</strong> <a href="https://doi.org/10.5281/zenodo.1334205" target="_blank">doi.org/10.5281/zenodo.1334205</a> </p> <a href="https://publications.waset.org/7661/high-performance-vlsi-architecture-of-2d-discrete-wavelet-transform-with-scalable-lattice-structure" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7661/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7661/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/7661/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/7661/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/7661/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/7661/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/7661/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/7661/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/7661/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/7661/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/7661.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1781</span> </span> <p class="card-text"><strong>References:</strong></p> <br>[1] P. P. Vaidyanathan, Multirate systems and Filter Banks, Englewood Cliffs, Prenctice-Hall, 1993 <br>[2] O. Rioul and M. Vetterli, "Wavelets and signal processing," IEEE Signal Process. Magazine, vol.8, no.4, pp.14-38, 1991 <br>[3] S. Mallat, "A theory for multiresolution signal decomposition: The wavelet representation," IEEE Trans. Pattern Anal. and Machine Intell., vol.11, no.7, pp.674-693, 1989 <br>[4] K. Pahri, VLSI digital signal processing systems, John Wiley & Sons, 1999 <br>[5] J. T. Kim, Y. H. Lee, T. Isshiki, and H. Kunieda, "Scalable VLSI architectures for lattice structure-based discrete wavelet transform," IEEE Trans. Circuits Systems II, Analog Digit. Process., vol.45, no.8, pp.1031-1043, 1998 <br>[6] C. Chakrabarti and M. Vishwanath, "Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers," IEEE Trans. Signal Process., vol.43, no.3, pp.759-771, 1995 <br>[7] M. Vishwanath, R. M. Owens, and M. J. Irwin, "VLSI architectures for the discrete wavelet transform," IEEE Trans. Circuits Systems II, Analog Digit. Process., vol.42, no.5, pp.305-316, 1995 <br>[8] F. Marino, "Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform," IEEE Trans. Circuits Systems II, Analog Digit. Process., vol.47, no.12, pp.1476-1491, 2000 <br>[9] T. C. Denk and K. K. Pahri, "Architectures for lattice structure based orthogonal discrete wavelet transform," IEEE Trans. Circuits Systems II, Analog Digit. Process., vol.44, no.2, pp.129-132, 1997 <br>[10] C. Yu and S.-J. Chen, "Design of an efficient VLSI architecture for 2-D discrete wavelet transforms," IEEE Trans. Consumer Elect., vol.45, no.1, pp.135-140, 1999 <br>[11] P. Wu and L.-G. Chen, "An efficient architecture for two-dimensional discrete wavelet transform," IEEE Trans. Circuits Systems, Video Technol., vol.11, no.4, pp.536-545, 2001 <br>[12] T. Park and S. Jung, "High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing," IEEE Trans. Consumer Elect., vol.48, no.4, pp.1026-1032, 2002 <br>[13] C.-T. Huang, P.-C. Tseng, and L.-G. Chen, "Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method," IEEE Trans. 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High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure