<?xml version="1.0" encoding="UTF-8"?> <article key="pdf/15296" mdate="2010-05-28 00:00:00"> <author>Arash Azizi Mazreah and Mohammad Reza Sahebi and Mohammad T. Manzuri Shalmani</author> <title>A Novel NanoScaled SRAM Cell</title> <pages>781 - 783</pages> <year>2010</year> <volume>4</volume> <number>5</number> <journal>International Journal of Electronics and Communication Engineering</journal> <ee>https://publications.waset.org/pdf/15296</ee> <url>https://publications.waset.org/vol/41</url> <publisher>World Academy of Science, Engineering and Technology</publisher> <abstract>To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a fourtransistor SRAM cell. The newly developed CMOS fourtransistor SRAM cell uses one wordline and one bitline during readwrite operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19 smaller than a conventional sixtransistor cell using same design rules. Also the leakage current of new cell is 60 smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during readwrite operation and idle mode. </abstract> <index>Open Science Index 41, 2010</index> </article>