Gridless Clock Distribution - Intel's Atom Architecture: The Journey Begins

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<section class="main_cont"> <div class="breadcrumb_area hide_resp2"> <nav class="breadcrumb"> <ul> <li><a href="/">Home</a><span>></span></li> <li><a href="/tag/cpus">CPUs</a></li> </ul> <div class="clear"></div> </nav> <div class="clear"></div> </div> <div class="review_blog"> <div class="blog_top_left"> <a href="/show/2493"><h1>Intel's Atom Architecture: The Journey Begins</h1></a> <span>by <a href="#"><a class='b' href='mailto:anand.shimpi@anandtech.com'>Anand Lal Shimpi</a></a> <em>on April 2, 2008 12:05 AM EST</em> </span> <ul class="hide_resp2"> <li>Posted in</li> <li><a href="/tag/cpus">CPUs</a></li> </ul> </div> <div class="blog_top_right show_resp2"> <span><a href="#comments">46 <small>Comments</small></a></span> | <strong><a class="icAddComment" href="/Comment/NewComment/2493?page=14&commentPage=1&showAllComments=False">Add A Comment</a></strong> </div> <div class="blog_top_right hide_resp2"> <span><a href="#comments">46 <small>Comments</small></a></span> </div> <div class="clear"></div> </div> <script type='text/javascript'> function go_here(navigation_list) { var new_ContentPagesURL = navigation_list.options[navigation_list.selectedIndex].value; if (new_ContentPagesURL != "") { self.location = new_ContentPagesURL; } } </script> <div class="article_links_top"> <select name="ContentPagesListTop" onchange="go_here(this)"> <option value="/show/2493">Index</option> <option value="/show/2493/2">Intel Aims at the Mainstream</option> <option value="/show/2493/3">What AMD Taught Me: x86 Everywhere</option> <option value="/show/2493/4">A Prelude to Success</option> <option value="/show/2493/5">Atom at a Glance</option> <option value="/show/2493/6">Intel's Atom: Changing Intel from the Inside</option> <option value="/show/2493/7">2-Issue and In-Order: Intel's Version of the Cell's PPE</option> <option value="/show/2493/8">Instructions Gone Wild: Safe Instruction Recognition</option> <option value="/show/2493/9">Return of the CISC: Macro-op Execution</option> <option value="/show/2493/10">It Does Multiple Threads Though: The Case for SMT</option> <option value="/show/2493/11">Fighting Power Consumption...with a Longer Pipeline?</option> <option value="/show/2493/12">An Unbalanced L1 Cache: We Know Why</option> <option value="/show/2493/13">Building by FUBs</option> <option selected="selected" value="/show/2493/14">Gridless Clock Distribution</option> <option value="/show/2493/15">Atom's FSB and Multi-Core Aspirations</option> <option value="/show/2493/16">Poulsbo: An Unusually Revolutionary Chipset</option> <option value="/show/2493/17">Poulsbo's Graphics: Full HD Decode and not Made by Intel</option> <option value="/show/2493/18">Lower Power than Centrino</option> <option value="/show/2493/19">Performance Expectations</option> <option value="/show/2493/20">The Product Lineup and Centrino Atom</option> <option value="/show/2493/21">Final Words</option> </select> </div> <div class="sidepadding review"> <div style="float: right; margin: 13px 0px 15px 15px;"> <div id="middle_ad"> </div> <div class="clear"></div> </div> <div class="articleContent"> <h3>Gridless Clock Distribution</h3> <p>As you push the frequency limits in large, high performance CPUs like the Core 2, you need to minimize overhead in each clock period so you can do the maximum amount of work. Timing is key.</p> <p>All functional blocks within a microprocessor operate on the same clock signal. You can think of the clock signal like a metronome or a heart beat; work only happens at every tick of the metronome, every beat of the heart or whenever the clock is logically "1" or "high". </p> <p>There's a single clock signal that's distributed across the chip, but the more complex the chip and the more times the clock changes per second, the tougher it becomes to just make sure the clock gets to all parts of the chip.</p> <p>In order to reach the absolute maximum frequencies possible, making sure the clock signal arrives at all parts of the chip at the same time with very little variation becomes increasingly important. </p> <p>The most effective method of distributing this single clock across the chip is by using a metal grid to distribute this critical signal across a large, complex die. The problem with this metal grid is that although it makes sure the clock gets to all parts of the chip with very little skew, it has a huge capacitance and consumes tremendous amounts of power. Large CPU cores can spend 30 - 35% of their power budget simply on clock distribution. This would obviously not work for Atom.</p> <p>While the Atom processor needs to run at relatively high frequencies, we're not talking about pushing 4GHz here. Without strenuous frequency requirements, a simpler form of clock distribution is ok. Atom uses a binary tree for clock distribution; the clock signal is sent from the PLL to the point of divergence, then fanned out into multiple trees of inverters and finally distributed vertically from each point of divergence to each FUB. </p> <p>The binary tree approach significantly reduces the amount of current consumed to the point that less than 10% of Atom's power budget is spent on distributing the clock.</p> </div> <div class="article_links"> <a href="/show/2493/13" class="fl-lt">Building by FUBs</a> <a href="/show/2493/15" class="fl-rt">Atom's FSB and Multi-Core Aspirations</a> <select name="ContentPagesList" onchange="go_here(this)"> <option value="/show/2493">Index</option> <option value="/show/2493/2">Intel Aims at the Mainstream</option> <option value="/show/2493/3">What AMD Taught Me: x86 Everywhere</option> <option value="/show/2493/4">A Prelude to Success</option> <option value="/show/2493/5">Atom at a Glance</option> <option value="/show/2493/6">Intel's Atom: Changing Intel from the Inside</option> <option value="/show/2493/7">2-Issue and In-Order: Intel's Version of the Cell's PPE</option> <option value="/show/2493/8">Instructions Gone Wild: Safe Instruction Recognition</option> <option value="/show/2493/9">Return of the CISC: Macro-op Execution</option> <option value="/show/2493/10">It Does Multiple Threads Though: The Case for SMT</option> <option value="/show/2493/11">Fighting Power Consumption...with a Longer Pipeline?</option> <option value="/show/2493/12">An Unbalanced L1 Cache: We Know Why</option> <option value="/show/2493/13">Building by FUBs</option> <option selected="selected" value="/show/2493/14">Gridless Clock Distribution</option> <option value="/show/2493/15">Atom's FSB and Multi-Core Aspirations</option> <option value="/show/2493/16">Poulsbo: An Unusually Revolutionary Chipset</option> <option value="/show/2493/17">Poulsbo's Graphics: Full HD Decode and not Made by Intel</option> <option value="/show/2493/18">Lower Power than Centrino</option> <option value="/show/2493/19">Performance Expectations</option> <option value="/show/2493/20">The Product Lineup and Centrino Atom</option> <option value="/show/2493/21">Final Words</option> </select> </div> <div class="clear"></div> <div class="fl-rt" style="margin: 22px 0px 15px;"> <div class="button left"><a href="/print/2493/" class="print_article"><span>PRINT THIS ARTICLE</span></a></div> </div> <div class="fl-rt" style="margin: 22px 8px 15px; height: 0px;"> </div> <div class="clear"></div> <div style="text-align: center;" id="resp_middle_ad"> </div> </div> <div class="discussion" id="comments"> <script type="text/javascript"> $(document).ready(function () { window.hasCommenting = true; $('#icTopPost').click(DoTopPost); $("#icLoginLink").click(function (e) { window.gotoComment = true; $.fancybox.open([ { href: '#inlineLogin' } ], { padding: 0, titlePosition: 'inside', transitionIn: 'none', transitionOut: 'none', afterShow: function (current, previous) { $('#UserName').focus(); } }); e.preventDefault(); return false; }); $("#inlineComment").click(function (e) { DoComment(); e.preventDefault(); return false; }); $("div#comments a.jqc").click(function () { $.get(this.href, scrollComments); return false; }); }); </script> <div><a id="commentsAnchor"></a></div> <ul id="icReplyHolder"> <li id="replybox" class="blog_post_area" style="display: none;"> <div class="blog_post_btm"> <h3>Post Your Comment</h3> <span id="icMessage"> Please <a id="icLoginLink" href="/Account/Login?r=%2fshow%2f2493%2f14">log in</a> or <a href="/Account/Register?r=%2fshow%2f2493%2f14">sign up</a> to comment. </span> <textarea cols="10" rows="10" class="comment_txtarea" placeholder="Enter your comment" id="CommentInput" name="CommentInput"></textarea> <input name="" type="button" id="inlineComment" class="submit_comment_btn" value="Submit Comment" disabled="disabled"> <img alt="" src="/Content/images/ajax-loader13.gif" id="icAjaxLoader"/> <input type="hidden" name="ParentCommentId" id="ParentCommentId" /> <input type="hidden" name="ReplyLevel" id="ReplyLevel" /> <input data-val="true" data-val-number="The field ContentId must be a number." data-val-required="The ContentId field is required." id="ContentId" name="ContentId" type="hidden" value="2493" /> <div class="clear"></div> </div> </li> </ul> <div class="blog_comments"> <div>Comments Locked</div> <h2>46 Comments</h2> <h3><a href="/comments/2493/">View All Comments</a></h3> <ul id="ulComments"> <li id="cid48321" style=""> <h4><a>adntaylor</a> - Tuesday, April 8, 2008 - <a href="/comments/2493//48321" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>On that chart with price / power, you need to be clearer... <br /> <br />For price, you show the combined price for CPU + Chipset. For power, you say just the CPU... so 0.65W for the CPU... but you're conveniently ignoring the >2W figure for the chipset!!! This absolutely flatters Intel wherever possible. <br /> <br />AMD are just as misleading - they describe the Geode LX as "1W" which excludes the non-CPU core parts of the chip (which is an integrated CPU + GMCH) <br /> <br />Just please be honest - the figures are out there in the Intel datasheets... it takes 10 minutes to check. </span> <div class="clear"></div> </li> <li id="cid48323" style=""> <h4><a>Clauzii</a> - Friday, April 4, 2008 - <a href="/comments/2493//48323" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>I still have a PowerVR 4MB addon card, runnung in tandem with a Rage128Pro. Quite a combination w. 15 FPS in Tombraider. Constant(!) 15FPS, that is.. <br /> <br />Amazing what they actually achieved back in 95! </span> <div class="clear"></div> </li> <li id="cid48322" style="padding-left:18px;"> <h4><a>Clauzii</a> - Friday, April 4, 2008 - <a href="/comments/2493//48322" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>Ooops! <br /> <br />Totally misplaced that. Sorry. </span> <div class="clear"></div> </li> <li id="cid48324" style=""> <h4><a>wimaxltepro</a> - Friday, April 4, 2008 - <a href="/comments/2493//48324" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>The Atom represents a shift in processor architecture that is the most dramatic departure for Intel since introduction of x86 processors... the philosophy of how computing itself occurs from centralized processors to distributed processing based on an extension of the popular x86 instruction set. <br /> <br />The Atom is not about the immediate prospects for the Atom or Nehalem products: we will likely see members of Intel's new product family be used in embedded applications in consumer products and in areas where specialized communications processors are more the rule. While not optimized for use in specific networking applications, the products capitalize on the wide range of support available in IT/Networking to develop common functions that leverage the low cost, low power/processing capability to be used as a common denominator for a wide range of applications. <br /> <br />Intel has been built on the 'Wintel' architecture: massively integrated chips needed to handle the massively integrated operating systems and applications of Windows (and Apple) environments. The Atom allows migration and broadening out from that architectural motif to a very highly distributed architecture. So, the increased parallelism found in the internal chip architecture is enabling of changes in external system architectures and device applications that go well beyond the typical domain of Intel.. and right into the domain of 'personal wireless broadband' and SDWN, Smart Distributed Wireless broadband Network. <br /> <br />The decisions about in-order vs. out of-order instruction streams, memory architecture, I/O architecture have been made in light of the broad vision for how computing, networking and, out of hand, how wireless enabled broadband networking including WiMAX will occur. This should be understood for what it represents as a shift in direction for Intel both in response to broad industry shifts and as a trend setting development. </span> <div class="clear"></div> </li> <li id="cid48326" style=""> <h4><a>jtleon</a> - Friday, April 4, 2008 - <a href="/comments/2493//48326" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span> Thanks to all the flash player ads, etc., a mobile web device will continuously avoid switching to low power states. Thus one could argue that advertising will be carbon footprint enemy of the internet's future. This is already becoming the case for desktop/laptop machines. <br /> <br /> Without such continuous (arguably wasted) consumption of CPU power, then Intel's engineered power management might have a significant impact on the value of the Atom. <br /> <br />Regards, <br />jtleon </span> <div class="clear"></div> </li> <li id="cid48327" style=""> <h4><a>0WaxMan0</a> - Friday, April 4, 2008 - <a href="/comments/2493//48327" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>I am definatly much impressed and enthused by intels work here, the future looks interesting esp for those of us who like low power cross compatible computing products. <br /> <br />However I have to point out that a low power modern x86 cpu has allready been done infact 4 years ago with AMD's Geode. While technically much weaker than the Atom and with out any where near the scalability (single core design etc.) the Geode has been available in the same TDP ranges for a good long while. Take a look here <a target=_blank class=ftalternatingbarlinklarge href="<a href="http://www.amdboard.com/geode.html" target="_blank" rel="nofollow">http://www.amdboard.com/geode.html</a>"><a href="http://www.amdboard.com/geode.html" target="_blank" rel="nofollow">http://www.amdboard.com/geode.html</a></a> for some old stuff. <br /> <br />I do hope that the Intel name and hype makes more of an impact than AMD managed. </span> <div class="clear"></div> </li> <li id="cid48332" style=""> <h4><a>whycode</a> - Thursday, April 3, 2008 - <a href="/comments/2493//48332" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>Does the TDP quoted include the chipset? Or is that CPU only? </span> <div class="clear"></div> </li> <li id="cid48337" style=""> <h4><a>IntelUser2000</a> - Thursday, April 3, 2008 - <a href="/comments/2493//48337" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>Anand, the Pentium M does not feature Macro Ops Fusion. Its Core 2 Duo that started Macro Ops Fusion. </span> <div class="clear"></div> </li> <li id="cid48336" style="padding-left:18px;"> <h4><a>Anand Lal Shimpi</a> - Thursday, April 3, 2008 - <a href="/comments/2493//48336" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>You're correct, I was referencing micro-op fusion. I've made the appropriate correction :) <br /> <br />Take care, <br />Anand </span> <div class="clear"></div> </li> <li id="cid48339" style=""> <h4><a>squito</a> - Wednesday, April 2, 2008 - <a href="/comments/2493//48339" style="font-weight:normal; color:#8E8C8C;">link</a></h4> <span>Am I the only one shocked to see that Poulsbo is a 130nm part... </span> <div class="clear"></div> </li> </ul> </div> <nav class="page_nav"> <ul> <li> <div class="a"><label for="">1</label></div> </li> <li> <a class="jqc" href="/Show/Index/2493?cPage=2&all=False&sort=0&page=14&slug=#comments">2</a> </li> <li> <a class="jqc" href="/Show/Index/2493?cPage=3&all=False&sort=0&page=14&slug=#comments">3</a> </li> <li> <a class="jqc" href="/Show/Index/2493?cPage=4&all=False&sort=0&page=14&slug=#comments">4</a> </li> <li> <a class="jqc" href="/Show/Index/2493?cPage=5&all=False&sort=0&page=14&slug=#comments">5</a> </li> <li class="arrow"> <a class="jqc" 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Gridless Clock Distribution - Intel's Atom Architecture: The Journey Begins