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Open RAN continues to attract interest from service providers looking to reduce cost, improve competition, and drive technology innovation. The desire for a… Network elements must meet certain frequency, phase, and time requirements to ensure proper end-to-end network operation. Synchronization architectures defined by the O-RAN alliance dictate how Open RAN equipment can meet these requirements." /> <link rel="canonical" href="https://www.analogictips.com/open-ran-networks-pass-the-time/" /> <meta property="og:locale" content="en_US" /> <meta property="og:type" content="article" /> <meta property="og:title" content="Open RAN networks pass the time" /> <meta property="og:description" content="Network elements must meet certain frequency, phase, and time requirements to ensure proper end-to-end network operation. Synchronization architectures defined by the O-RAN alliance dictate how Open RAN equipment can meet these requirements. Open RAN continues to attract interest from service providers looking to reduce cost, improve competition, and drive technology innovation. The desire for a… Network elements must meet certain frequency, phase, and time requirements to ensure proper end-to-end network operation. Synchronization architectures defined by the O-RAN alliance dictate how Open RAN equipment can meet these requirements." /> <meta property="og:url" content="https://www.analogictips.com/open-ran-networks-pass-the-time/" /> <meta property="og:site_name" content="Analog IC Tips" /> <meta property="article:published_time" content="2023-04-04T09:00:45+00:00" /> <meta property="article:modified_time" content="2024-05-23T18:41:42+00:00" /> <meta property="og:image" content="https://www.analogictips.com/wp-content/uploads/2023/04/5GHB23_Microchip_Feature_art.jpg" /> <meta property="og:image:width" content="1488" /> <meta property="og:image:height" content="897" /> <meta property="og:image:type" content="image/jpeg" /> <meta name="author" content="Emma Lutjen" /> <meta name="twitter:card" content="summary_large_image" /> <meta name="twitter:creator" content="@AnalogICTips" /> <meta name="twitter:site" content="@AnalogICTips" /> <meta name="twitter:label1" content="Written by" /> <meta name="twitter:data1" content="By Darrin Gile, Microchip Technology" /> <meta name="twitter:label2" content="Est. reading time" /> <meta name="twitter:data2" content="7 minutes" /> <script type="application/ld+json" class="yoast-schema-graph">{"@context":"https://schema.org","@graph":[{"@type":"WebPage","@id":"https://www.analogictips.com/open-ran-networks-pass-the-time/","url":"https://www.analogictips.com/open-ran-networks-pass-the-time/","name":"Open RAN networks pass the time","isPartOf":{"@id":"https://www.analogictips.com/#website"},"primaryImageOfPage":{"@id":"https://www.analogictips.com/open-ran-networks-pass-the-time/#primaryimage"},"image":{"@id":"https://www.analogictips.com/open-ran-networks-pass-the-time/#primaryimage"},"thumbnailUrl":"https://www.analogictips.com/wp-content/uploads/2023/04/5GHB23_Microchip_Feature_art.jpg","datePublished":"2023-04-04T09:00:45+00:00","dateModified":"2024-05-23T18:41:42+00:00","author":{"@id":"https://www.analogictips.com/#/schema/person/f135a4291b66f8dd25ca65eb060e5ea9"},"description":"Network elements must meet certain frequency, phase, and time requirements to ensure proper end-to-end network operation. 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href="https://www.addtoany.com/share"></a></div></div><p><em>Network elements must meet certain frequency, phase, and time requirements to ensure proper end-to-end network operation. Synchronization architectures defined by the O-RAN alliance dictate how Open RAN equipment can meet these requirements.</em></p> <p>Open RAN continues to attract interest from service providers looking to reduce cost, improve competition, and drive technology innovation. The desire for a disaggregated and virtual RAN architecture has introduced more flexibility, competition, and openness to the 5G networks.</p> <p>The <a href="https://www.o-ran.org/" target="_blank" rel="noopener">O-RAN Alliance</a> was formed in 2018 to standardize hardware and define open interfaces that ensure interoperability between vendor equipment. Protocols, architectures, and requirements for the control, user, and synchronization planes are defined in <a href="https://orandownloadsweb.azurewebsites.net/specifications" target="_blank" rel="noopener">O-RAN.WG4.CUS.0-v10.00</a>.</p> <p><strong>The S-Plane and accuracy</strong><br /> The <a href="https://orandownloadsweb.azurewebsites.net/specifications" target="_blank" rel="noopener">synchronization plane</a> (S-Plane) addresses network topologies and timing accuracy limits for the fronthaul network connection between the O-RAN radio unit (RU) and distributed unit (DU). The requirements for frequency, phase, and time synchronization follow the 3GPP recommendations and align with the ITU-T network and equipment limits. For time-division duplex (TDD) cellular networks, the base requirement for TDD cellular networks is 3 µsec between base stations, or ±1.5 µsec (<a href="https://www.itu.int/rec/T-REC-G.8271/en" target="_blank" rel="noopener">G.8271</a>) between the end application and a common point. More stringent accuracy requirements exist for equipment used with advanced radio technologies such as coordinated multipoint or MIMO. To meet these tighter network limits, equipment will need to meet the Class C (30 nsec) maximum absolute time error defined in <a href="https://www.itu.int/rec/T-REC-G.8272/en" target="_blank" rel="noopener">G.8372.2</a>.</p> <p><strong>Timing configurations</strong><br /> The S-Plane consists of four topologies for distributing timing through the <a href="https://www.5gtechnologyworld.com/5g-fronthaul-networks-add-flexibility/" target="_blank" rel="noopener">fronthaul network</a> (RU to DU). These configurations rely on a combination of time-based and frequency-based synchronization techniques. A primary reference time clock (PRTC or ePRTC) located in the network will provide a base time for each network element. The use of GNSS, <a href="https://www.5gtechnologyworld.com/how-virtual-primary-reference-time-clocks-improve-5g-network-timing/" target="_blank" rel="noopener">precision time protocol</a> (PTP), and a physical layer frequency source, most commonly <a href="https://www.5gtechnologyworld.com/how-timing-design-and-management-synchronizes-5g-networks/" target="_blank" rel="noopener">Synchronous Ethernet</a> (SyncE), ensures the RU reliably receives the frequency and, more importantly, the phase and time synchronization required to operate the network.</p> <p><strong>Figures 1 and 2</strong> show the four defined configurations for supporting network synchronization in the Open RAN fronthaul network.</p> <div id="attachment_18922" class="wp-caption aligncenter" style="width: 750px;"> <p><a href="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1.jpg"><img decoding="async" class="size-large wp-image-18922" src="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-1024x274.jpg" sizes="(max-width: 740px) 100vw, 740px" srcset="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-1024x274.jpg 1024w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-300x80.jpg 300w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-768x205.jpg 768w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-1536x411.jpg 1536w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1-368x98.jpg 368w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig1.jpg 1772w" alt="" width="740" height="198" aria-describedby="caption-attachment-18922" /></a></p> <p id="caption-attachment-18922" class="wp-caption-text">Figure 1. In these configurations, timing comes from upstream (left) or from T-BC’s in the fronthaul (right).</p> </div> <div id="attachment_18923" class="wp-caption aligncenter" style="width: 750px;"> <p><a href="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2.jpg"><img decoding="async" class="size-large wp-image-18923" src="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-1024x268.jpg" sizes="(max-width: 740px) 100vw, 740px" srcset="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-1024x268.jpg 1024w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-300x79.jpg 300w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-768x201.jpg 768w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-1536x402.jpg 1536w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2-368x96.jpg 368w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig2.jpg 1764w" alt="" width="740" height="194" aria-describedby="caption-attachment-18923" /></a></p> <p id="caption-attachment-18923" class="wp-caption-text">Figure 2. The DU and RU get time from a PRTC (left) while timing comes from GNSS through switches (right).</p> </div> <p><em>Configuration LLS-C1</em><br /> Synchronization for the first configuration occurs through a direct connection between the DU and RU. The O-DU will receive network time from a precision real-time-clock/telecom grandmaster (PRTC/T-GM) that is either co-located with the O-DU or from a remote PRTC/T-GM located further back in the network.</p> <p><em>Configuration LLS-C2</em><br /> For configuration LLS-C2, the DU still receives network time from a co-located PRTC or one further upstream in the network. Network time passes from the DU through additional switches that reside in the fronthaul network. For best performance, these switches should comprise a fully aware (<a href="https://www.itu.int/rec/T-REC-G.8275/en" target="_blank" rel="noopener">G.8275.1</a>) network where each node acts as a <a href="https://www.5gtechnologyworld.com/how-virtual-primary-reference-time-clocks-improve-5g-network-timing/" target="_blank" rel="noopener">telecom boundary clock</a> (T-BC). Partially aware networks where one or more switches don’t participate in the filtering of PTP are also allowed. Depending on the type of fronthaul network, the type and number of hops present through the fronthaul network will limit the overall performance of the network. For example, a fully aware network comprised of Class C (30 nsec) T-BC’s can facilitate more hops than a fully-aware network comprised of Class B (70 nsec) T-BC’s.</p> <p><em>Configuration LLS-C3</em><br /> For the third configuration, both the DU and RU will receive network time from a PRTC located in the fronthaul network.<br /> As with LLS-C2, network time can propagate through the fronthaul network via fully-aware or partially-aware switches. In some cases, the DU may participate as a T-BC in passing time to the RU.</p> <p><em>Configuration LLS-C4</em><br /> Configuration LLS-C4 is the most preferred and easiest to implement but potentially the costliest of the four topologies. In this configuration, the RU gets time from GNSS as a pulse per second (PPS) clock or from a co-located PRTC/T-GM. The sheer number of 5G NR sites and the location requirements of the GNSS antenna can make this a costly or impractical configuration to deploy. GNSS at the radio sites may also be more susceptible to spoofing or jamming, which can disrupt proper operation.</p> <p><strong>Equipment design</strong><br /> Like network deployments, the synchronization design of network equipment requires proper planning and design. To satisfy network synchronization limits, equipment will use a combination of timestampers, advanced phase lock loops (PLL), robust software for PTP support, and precision oscillators (<strong>Figure 3</strong>).</p> <div id="attachment_18924" class="wp-caption aligncenter" style="width: 750px;"> <p><a href="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3.jpg"><img loading="lazy" decoding="async" class="size-large wp-image-18924" src="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-1024x246.jpg" sizes="auto, (max-width: 740px) 100vw, 740px" srcset="https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-1024x246.jpg 1024w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-300x72.jpg 300w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-768x184.jpg 768w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-1536x368.jpg 1536w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3-368x88.jpg 368w, https://www.5gtechnologyworld.com/wp-content/uploads/2023/03/5GHB23_Microchip_Fig3.jpg 1734w" alt="" width="740" height="178" aria-describedby="caption-attachment-18924" /></a></p> <p id="caption-attachment-18924" class="wp-caption-text">Figure 3. Network equipment uses a combination of PTP software, a system synchronizer, PLL’s, and a timestamper.</p> </div> <p>The first key piece of the design is the system synchronizer, which consists of several advanced PLLs. The synchronizer provides <a href="https://www.eeworldonline.com/measuring-and-abating-jitter/" target="_blank" rel="noopener">jitter</a> and wander filtering for SyncE clocks, input reference-clock monitoring, hitless reference switching, and a numerically controlled oscillator for fine PPS/PTP clock control. The PLLs also provide bandwidths capable of locking directly to PPS clock sources.</p> <p>Accurate timestampers, PTP software, and an advanced algorithm will manage PTP traffic and provide the tuning calculations needed to accurately track T-GM phase and time. Finally, the precision oscillator is critical to ensure proper holdover and overall performance parameters.</p> <p>These building blocks are the same for the DU, RU, and any switch participating in timing distribution. The actual implementation of the functional blocks may differ depending on the use case. For example, the precision oscillator may vary depending on the holdover requirements for each network element. A DU needs more stability and must support longer holdover times than an RU. Because of this, RU designs may be able to use higher-end temperature-controlled oscillators (TCXOs) or mini-oven-controlled oscillators (OCXOs) while a DU may use a more expensive OCXO.</p> <p><strong>Improving timing latency</strong><br /> You can employ any of several techniques to improve overall time accuracy within a piece of equipment. These techniques range from basic design items such as placing the timestamper as close to the edge of the equipment as possible, to more complex system calibration for phase management within the system. The use of SyncE and more specifically the Enhanced Synchronous Equipment Slave Clock (eEEC), as defined in <a href="https://www.itu.int/rec/dologin_pub.asp?lang=e&id=T-REC-G.8262.1-202211-I!!PDF-E" target="_blank" rel="noopener">G.8262.1</a>, provides a stable frequency reference that greatly improves overall phase performance for hybrid configurations.</p> <p>When used with security protocols such as <a href="https://www.juniper.net/documentation/us/en/software/junos/security-services/topics/topic-map/understanding_media_access_control_security_qfx_ex.html" target="_blank" rel="noopener">MACsec</a>, take care to ensure that the encryption/decryption adds little or no delay to the timestamping function. Properly design and select the performance of the advanced algorithm and precision oscillator stability to provide the needed performance. For more complex designs, ensuring all timing components involved in the distribution of the PPS clock minimize input-to-output delay variation and output-to-output skew is critical to satisfy even the tightest equipment limits. Some synchronizers take advantage of calibration functionality that provides fine phase control measurements and adjustments. Additional compensation for phase error caused by the temperature and aging of the precision oscillator temperature can also be accomplished. You can use some or all these methods to ensure that equipment meets time and accuracy limits.</p> <p>Initially, rural and private greenfield networks have been good launching points for deploying Open RAN. As more macro deployments begin to come online, providing high-accuracy network synchronization will be critical for delivering the performance that ultra-low latency applications and advanced radios technologies demand.</p> <p>Darrin Gile is a senior technical staff engineer for Microchip Technology’s timing and communications business unit, with more than 26 years of experience in the semiconductor industry. For the past 20 years, he has held field applications and business development roles assisting clients with network synchronization and advanced timing applications. Mr. Gile specializes in customer engagements related to Synchronous Ethernet and IEEE-1588. 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